1 /*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/kobj.h> 33 #include <sys/module.h> 34 #include <sys/malloc.h> 35 #include <sys/rman.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/cpu.h> 41 42 #include <dev/extres/clk/clk_div.h> 43 #include <dev/extres/clk/clk_fixed.h> 44 #include <dev/extres/clk/clk_gate.h> 45 #include <dev/extres/clk/clk_mux.h> 46 #include <dev/extres/hwreset/hwreset.h> 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dt-bindings/clock/tegra124-car.h> 52 53 #include "clkdev_if.h" 54 #include "hwreset_if.h" 55 #include "tegra124_car.h" 56 57 static struct ofw_compat_data compat_data[] = { 58 {"nvidia,tegra124-car", 1}, 59 {NULL, 0}, 60 }; 61 62 #define PLIST(x) static const char *x[] 63 64 /* Pure multiplexer. */ 65 #define MUX(_id, cname, plists, o, s, w) \ 66 { \ 67 .clkdef.id = _id, \ 68 .clkdef.name = cname, \ 69 .clkdef.parent_names = plists, \ 70 .clkdef.parent_cnt = nitems(plists), \ 71 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 72 .offset = o, \ 73 .shift = s, \ 74 .width = w, \ 75 } 76 77 /* Fractional divider (7.1). */ 78 #define DIV7_1(_id, cname, plist, o, s) \ 79 { \ 80 .clkdef.id = _id, \ 81 .clkdef.name = cname, \ 82 .clkdef.parent_names = (const char *[]){plist}, \ 83 .clkdef.parent_cnt = 1, \ 84 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 85 .offset = o, \ 86 .i_shift = (s) + 1, \ 87 .i_width = 7, \ 88 .f_shift = s, \ 89 .f_width = 1, \ 90 } 91 92 /* Integer divider. */ 93 #define DIV(_id, cname, plist, o, s, w, f) \ 94 { \ 95 .clkdef.id = _id, \ 96 .clkdef.name = cname, \ 97 .clkdef.parent_names = (const char *[]){plist}, \ 98 .clkdef.parent_cnt = 1, \ 99 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 100 .offset = o, \ 101 .i_shift = s, \ 102 .i_width = w, \ 103 .div_flags = f, \ 104 } 105 106 /* Gate in PLL block. */ 107 #define GATE_PLL(_id, cname, plist, o, s) \ 108 { \ 109 .clkdef.id = _id, \ 110 .clkdef.name = cname, \ 111 .clkdef.parent_names = (const char *[]){plist}, \ 112 .clkdef.parent_cnt = 1, \ 113 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 114 .offset = o, \ 115 .shift = s, \ 116 .mask = 3, \ 117 .on_value = 3, \ 118 .off_value = 0, \ 119 } 120 121 /* Standard gate. */ 122 #define GATE(_id, cname, plist, o, s) \ 123 { \ 124 .clkdef.id = _id, \ 125 .clkdef.name = cname, \ 126 .clkdef.parent_names = (const char *[]){plist}, \ 127 .clkdef.parent_cnt = 1, \ 128 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 129 .offset = o, \ 130 .shift = s, \ 131 .mask = 1, \ 132 .on_value = 1, \ 133 .off_value = 0, \ 134 } 135 136 /* Inverted gate. */ 137 #define GATE_INV(_id, cname, plist, o, s) \ 138 { \ 139 .clkdef.id = _id, \ 140 .clkdef.name = cname, \ 141 .clkdef.parent_names = (const char *[]){plist}, \ 142 .clkdef.parent_cnt = 1, \ 143 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 144 .offset = o, \ 145 .shift = s, \ 146 .mask = 1, \ 147 .on_value = 0, \ 148 .off_value = 1, \ 149 } 150 151 /* Fixed rate clock. */ 152 #define FRATE(_id, cname, _freq) \ 153 { \ 154 .clkdef.id = _id, \ 155 .clkdef.name = cname, \ 156 .clkdef.parent_names = NULL, \ 157 .clkdef.parent_cnt = 0, \ 158 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 159 .freq = _freq, \ 160 } 161 162 /* Fixed rate multipier/divider. */ 163 #define FACT(_id, cname, pname, _mult, _div) \ 164 { \ 165 .clkdef.id = _id, \ 166 .clkdef.name = cname, \ 167 .clkdef.parent_names = (const char *[]){pname}, \ 168 .clkdef.parent_cnt = 1, \ 169 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 170 .mult = _mult, \ 171 .div = _div, \ 172 } 173 174 static uint32_t osc_freqs[16] = { 175 [0] = 13000000, 176 [1] = 16800000, 177 [4] = 19200000, 178 [5] = 38400000, 179 [8] = 12000000, 180 [9] = 48000000, 181 [12] = 260000000, 182 }; 183 184 /* Parent lists. */ 185 PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 186 PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 187 PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"}; 188 PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"}; 189 PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"}; 190 PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"}; 191 192 /* Clocks adjusted online. */ 193 static struct clk_fixed_def fixed_clk_m = 194 FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000); 195 static struct clk_fixed_def fixed_osc_div_clk = 196 FACT(0, "osc_div_clk", "clk_m", 1, 1); 197 198 static struct clk_fixed_def tegra124_fixed_clks[] = { 199 /* Core clocks. */ 200 FRATE(0, "clk_s", 32768), 201 FACT(0, "clk_m_div2", "clk_m", 1, 2), 202 FACT(0, "clk_m_div4", "clk_m", 1, 3), 203 FACT(0, "pllU_60", "pllU_out", 1, 8), 204 FACT(0, "pllU_48", "pllU_out", 1, 10), 205 FACT(0, "pllU_12", "pllU_out", 1, 40), 206 FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 207 FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1), 208 FACT(0, "pllX_out0", "pllX_out", 1, 2), 209 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 210 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 211 212 /* Audio clocks. */ 213 FRATE(0, "audio0", 10000000), 214 FRATE(0, "audio1", 10000000), 215 FRATE(0, "audio2", 10000000), 216 FRATE(0, "audio3", 10000000), 217 FRATE(0, "audio4", 10000000), 218 FRATE(0, "ext_vimclk", 10000000), 219 220 /* XUSB */ 221 FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2), 222 223 }; 224 225 static struct clk_mux_def tegra124_mux_clks[] = { 226 /* Core clocks. */ 227 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 228 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 229 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 230 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 231 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 232 233 /* Base peripheral clocks. */ 234 MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1), 235 MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1), 236 237 /* USB. */ 238 MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1), 239 MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1), 240 241 }; 242 243 static struct clk_gate_def tegra124_gate_clks[] = { 244 /* Core clocks. */ 245 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 246 GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0), 247 GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22), 248 GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0), 249 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 250 GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16), 251 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 252 GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 253 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 254 GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0), 255 256 /* Base peripheral clocks. */ 257 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 258 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 259 GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7), 260 GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3), 261 }; 262 263 static struct clk_div_def tegra124_div_clks[] = { 264 /* Core clocks. */ 265 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2), 266 DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8), 267 DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2), 268 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 269 DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24), 270 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 271 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 272 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 273 DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8), 274 275 /* Base peripheral clocks. */ 276 DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0), 277 DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0), 278 }; 279 280 /* Initial setup table. */ 281 static struct tegra124_init_item clk_init_table[] = { 282 /* clock, partent, frequency, enable */ 283 {"uarta", "pllP_out0", 408000000, 0}, 284 {"uartb", "pllP_out0", 408000000, 0}, 285 {"uartc", "pllP_out0", 408000000, 0}, 286 {"uartd", "pllP_out0", 408000000, 0}, 287 {"pllA_out", NULL, 282240000, 1}, 288 {"pllA_out0", NULL, 11289600, 1}, 289 {"extperiph1", "pllA_out0", 0, 1}, 290 {"i2s0", "pllA_out0", 11289600, 0}, 291 {"i2s1", "pllA_out0", 11289600, 0}, 292 {"i2s2", "pllA_out0", 11289600, 0}, 293 {"i2s3", "pllA_out0", 11289600, 0}, 294 {"i2s4", "pllA_out0", 11289600, 0}, 295 {"vde", "pllP_out0", 0, 0}, 296 {"host1x", "pllP_out0", 136000000, 1}, 297 {"sclk", "pllP_out2", 102000000, 1}, 298 {"dvfs_soc", "pllP_out0", 51000000, 1}, 299 {"dvfs_ref", "pllP_out0", 51000000, 1}, 300 {"pllC_out0", NULL, 600000000, 0}, 301 {"pllC_out1", NULL, 100000000, 0}, 302 {"spi4", "pllP_out0", 12000000, 1}, 303 {"tsec", "pllC3_out0", 0, 0}, 304 {"msenc", "pllC3_out0", 0, 0}, 305 {"pllREFE_out", NULL, 672000000, 0}, 306 {"pc_xusb_ss", "pllU_480", 120000000, 0}, 307 {"xusb_ss", "pc_xusb_ss", 120000000, 0}, 308 {"pc_xusb_fs", "pllU_48", 48000000, 0}, 309 {"xusb_hs", "pllU_60", 60000000, 0}, 310 {"pc_xusb_falcon", "pllREFE_out", 224000000, 0}, 311 {"xusb_core_host", "pllREFE_out", 112000000, 0}, 312 {"sata", "pllP_out0", 102000000, 0}, 313 {"sata_oob", "pllP_out0", 204000000, 0}, 314 {"sata_cold", NULL, 0, 1}, 315 {"emc", NULL, 0, 1}, 316 {"mselect", NULL, 0, 1}, 317 {"csite", NULL, 0, 1}, 318 {"tsensor", "clk_m", 400000, 0}, 319 320 /* tegra124 only*/ 321 {"soc_therm", "pllP_out0", 51000000, 0}, 322 {"cclk_g", NULL, 0, 1}, 323 {"hda", "pllP_out0", 102000000, 0}, 324 {"hda2codec_2x", "pllP_out0", 48000000, 0}, 325 }; 326 327 static void 328 init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks) 329 { 330 int i, rv; 331 332 for (i = 0; i < nclks; i++) { 333 rv = clknode_div_register(sc->clkdom, clks + i); 334 if (rv != 0) 335 panic("clk_div_register failed"); 336 } 337 } 338 339 static void 340 init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks) 341 { 342 int i, rv; 343 344 for (i = 0; i < nclks; i++) { 345 rv = clknode_gate_register(sc->clkdom, clks + i); 346 if (rv != 0) 347 panic("clk_gate_register failed"); 348 } 349 } 350 351 static void 352 init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks) 353 { 354 int i, rv; 355 356 for (i = 0; i < nclks; i++) { 357 rv = clknode_mux_register(sc->clkdom, clks + i); 358 if (rv != 0) 359 panic("clk_mux_register failed"); 360 } 361 } 362 363 static void 364 init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks, 365 int nclks) 366 { 367 int i, rv; 368 uint32_t val; 369 int osc_idx; 370 371 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); 372 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; 373 fixed_clk_m.freq = osc_freqs[osc_idx]; 374 if (fixed_clk_m.freq == 0) 375 panic("Undefined input frequency"); 376 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m); 377 if (rv != 0) panic("clk_fixed_register failed"); 378 379 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 380 fixed_osc_div_clk.div = 1 << val; 381 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk); 382 if (rv != 0) panic("clk_fixed_register failed"); 383 384 for (i = 0; i < nclks; i++) { 385 rv = clknode_fixed_register(sc->clkdom, clks + i); 386 if (rv != 0) 387 panic("clk_fixed_register failed"); 388 } 389 } 390 391 static void 392 postinit_clock(struct tegra124_car_softc *sc) 393 { 394 int i; 395 struct tegra124_init_item *tbl; 396 struct clknode *clknode; 397 int rv; 398 399 for (i = 0; i < nitems(clk_init_table); i++) { 400 tbl = &clk_init_table[i]; 401 402 clknode = clknode_find_by_name(tbl->name); 403 if (clknode == NULL) { 404 device_printf(sc->dev, "Cannot find clock %s\n", 405 tbl->name); 406 continue; 407 } 408 if (tbl->parent != NULL) { 409 rv = clknode_set_parent_by_name(clknode, tbl->parent); 410 if (rv != 0) { 411 device_printf(sc->dev, 412 "Cannot set parent for %s (to %s): %d\n", 413 tbl->name, tbl->parent, rv); 414 continue; 415 } 416 } 417 if (tbl->frequency != 0) { 418 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999); 419 if (rv != 0) { 420 device_printf(sc->dev, 421 "Cannot set frequency for %s: %d\n", 422 tbl->name, rv); 423 continue; 424 } 425 } 426 if (tbl->enable!= 0) { 427 rv = clknode_enable(clknode); 428 if (rv != 0) { 429 device_printf(sc->dev, 430 "Cannot enable %s: %d\n", tbl->name, rv); 431 continue; 432 } 433 } 434 } 435 } 436 437 static void 438 register_clocks(device_t dev) 439 { 440 struct tegra124_car_softc *sc; 441 442 sc = device_get_softc(dev); 443 sc->clkdom = clkdom_create(dev); 444 if (sc->clkdom == NULL) 445 panic("clkdom == NULL"); 446 447 tegra124_init_plls(sc); 448 init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks)); 449 init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks)); 450 init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks)); 451 init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks)); 452 tegra124_periph_clock(sc); 453 tegra124_super_mux_clock(sc); 454 clkdom_finit(sc->clkdom); 455 clkdom_xlock(sc->clkdom); 456 postinit_clock(sc); 457 clkdom_unlock(sc->clkdom); 458 if (bootverbose) 459 clkdom_dump(sc->clkdom); 460 } 461 462 static int 463 tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 464 { 465 struct tegra124_car_softc *sc; 466 467 sc = device_get_softc(dev); 468 *val = bus_read_4(sc->mem_res, addr); 469 return (0); 470 } 471 472 static int 473 tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val) 474 { 475 struct tegra124_car_softc *sc; 476 477 sc = device_get_softc(dev); 478 bus_write_4(sc->mem_res, addr, val); 479 return (0); 480 } 481 482 static int 483 tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, 484 uint32_t set_mask) 485 { 486 struct tegra124_car_softc *sc; 487 uint32_t reg; 488 489 sc = device_get_softc(dev); 490 reg = bus_read_4(sc->mem_res, addr); 491 reg &= ~clear_mask; 492 reg |= set_mask; 493 bus_write_4(sc->mem_res, addr, reg); 494 return (0); 495 } 496 497 static void 498 tegra124_car_clkdev_device_lock(device_t dev) 499 { 500 struct tegra124_car_softc *sc; 501 502 sc = device_get_softc(dev); 503 mtx_lock(&sc->mtx); 504 } 505 506 static void 507 tegra124_car_clkdev_device_unlock(device_t dev) 508 { 509 struct tegra124_car_softc *sc; 510 511 sc = device_get_softc(dev); 512 mtx_unlock(&sc->mtx); 513 } 514 515 static int 516 tegra124_car_detach(device_t dev) 517 { 518 519 device_printf(dev, "Error: Clock driver cannot be detached\n"); 520 return (EBUSY); 521 } 522 523 static int 524 tegra124_car_probe(device_t dev) 525 { 526 527 if (!ofw_bus_status_okay(dev)) 528 return (ENXIO); 529 530 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 531 device_set_desc(dev, "Tegra Clock Driver"); 532 return (BUS_PROBE_DEFAULT); 533 } 534 535 return (ENXIO); 536 } 537 538 static int 539 tegra124_car_attach(device_t dev) 540 { 541 struct tegra124_car_softc *sc = device_get_softc(dev); 542 int rid, rv; 543 544 sc->dev = dev; 545 546 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 547 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 548 549 /* Resource setup. */ 550 rid = 0; 551 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 552 RF_ACTIVE); 553 if (!sc->mem_res) { 554 device_printf(dev, "cannot allocate memory resource\n"); 555 rv = ENXIO; 556 goto fail; 557 } 558 559 register_clocks(dev); 560 hwreset_register_ofw_provider(dev); 561 return (0); 562 563 fail: 564 if (sc->mem_res) 565 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 566 567 return (rv); 568 } 569 570 static int 571 tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value) 572 { 573 struct tegra124_car_softc *sc = device_get_softc(dev); 574 575 return (tegra124_hwreset_by_idx(sc, id, value)); 576 } 577 578 static device_method_t tegra124_car_methods[] = { 579 /* Device interface */ 580 DEVMETHOD(device_probe, tegra124_car_probe), 581 DEVMETHOD(device_attach, tegra124_car_attach), 582 DEVMETHOD(device_detach, tegra124_car_detach), 583 584 /* Clkdev interface*/ 585 DEVMETHOD(clkdev_read_4, tegra124_car_clkdev_read_4), 586 DEVMETHOD(clkdev_write_4, tegra124_car_clkdev_write_4), 587 DEVMETHOD(clkdev_modify_4, tegra124_car_clkdev_modify_4), 588 DEVMETHOD(clkdev_device_lock, tegra124_car_clkdev_device_lock), 589 DEVMETHOD(clkdev_device_unlock, tegra124_car_clkdev_device_unlock), 590 591 /* Reset interface */ 592 DEVMETHOD(hwreset_assert, tegra124_car_hwreset_assert), 593 594 DEVMETHOD_END 595 }; 596 597 static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods, 598 sizeof(struct tegra124_car_softc)); 599 EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver, NULL, NULL, 600 BUS_PASS_TIMER); 601