1 /*- 2 * Copyright 1992-2016 Michal Meloun 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 #ifndef _TEGRA_HDMI_REG_H_ 29 #define _TEGRA_HDMI_REG_H_ 30 31 /* 32 * !!! WARNING !!! 33 * Tegra manual uses registers index (and not register addreses). 34 * We follow the TRM notation and index is converted to offset in 35 * WR4 / RD4 macros 36 */ 37 #define HDMI_NV_PDISP_SOR_STATE0 0x001 38 #define SOR_STATE0_UPDATE (1 << 0) 39 40 #define HDMI_NV_PDISP_SOR_STATE1 0x002 41 #define SOR_STATE1_ATTACHED (1 << 3) 42 #define SOR_STATE1_ASY_ORMODE_NORMAL (1 << 2) 43 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0) 44 #define ASY_HEAD_OPMODE_SLEEP 0 45 #define ASY_HEAD_OPMODE_SNOOZE 1 46 #define ASY_HEAD_OPMODE_AWAKE 2 47 48 #define HDMI_NV_PDISP_SOR_STATE2 0x003 49 #define SOR_STATE2_ASY_DEPOL_NEG (1 << 14) 50 #define SOR_STATE2_ASY_VSYNCPOL_NEG (1 << 13) 51 #define SOR_STATE2_ASY_HSYNCPOL_NEG (1 << 12) 52 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8) 53 #define ASY_PROTOCOL_SINGLE_TMDS_A 1 54 #define ASY_PROTOCOL_CUSTOM 15 55 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6) 56 #define ASY_CRCMODE_ACTIVE 0 57 #define ASY_CRCMODE_COMPLETE 1 58 #define ASY_CRCMODE_NON_ACTIVE 2 59 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4) 60 #define ASY_SUBOWNER_NONE 0 61 #define ASY_SUBOWNER_SUBHEAD0 1 62 #define ASY_SUBOWNER_SUBHEAD1 2 63 #define SUBOWNER_BOTH 3 64 #define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0) 65 #define ASY_OWNER_NONE 0 66 #define ASY_OWNER_HEAD0 1 67 68 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x01e 69 #define AUDIO_INFOFRAME_CTRL_ENABLE (1 << 0) 70 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x01f 71 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x020 72 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x021 73 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x022 74 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) 75 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) 76 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) 77 78 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x023 79 #define AVI_INFOFRAME_CTRL_ENABLE (1 << 0) 80 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x024 81 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x025 82 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x026 83 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x027 84 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x028 85 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x029 86 87 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x02a 88 #define GENERIC_CTRL_AUDIO (1 << 16) 89 #define GENERIC_CTRL_HBLANK (1 << 12) 90 #define GENERIC_CTRL_SINGLE (1 << 8) 91 #define GENERIC_CTRL_OTHER (1 << 4) 92 #define GENERIC_CTRL_ENABLE (1 << 0) 93 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x02b 94 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x02c 95 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x02d 96 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x02e 97 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x02f 98 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x030 99 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x031 100 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x032 101 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x033 102 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x034 103 104 #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x035 105 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x036 106 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x037 107 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x038 108 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x039 109 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x03a 110 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x03b 111 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x03c 112 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x03d 113 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x03e 114 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x03f 115 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x040 116 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x041 117 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x042 118 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x043 119 #define ACR_ENABLE (1U << 31) 120 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8) 121 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0) 122 123 #define HDMI_NV_PDISP_HDMI_CTRL 0x044 124 #define HDMI_CTRL_ENABLE (1 << 30) 125 #define HDMI_CTRL_CA_SELECT (1 << 28) 126 #define HDMI_CTRL_SS_SELECT (1 << 27) 127 #define HDMI_CTRL_SF_SELECT (1 << 26) 128 #define HDMI_CTRL_CC_SELECT (1 << 25) 129 #define HDMI_CTRL_CT_SELECT (1 << 24) 130 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16) 131 #define HDMI_CTRL_SAMPLE_FLAT (1 << 12) 132 #define HDMI_CTRL_AUDIO_LAYOUT_SELECT (1 << 10) 133 #define HDMI_CTRL_AUDIO_LAYOUT (1 << 8) 134 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0) 135 136 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x046 137 #define VSYNC_WINDOW_ENABLE (1U << 31) 138 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16) 139 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0) 140 141 #define HDMI_NV_PDISP_HDMI_SPARE 0x04f 142 #define SPARE_ACR_PRIORITY (1U << 31) 143 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16) 144 #define SPARE_SUPRESS_SP_B (1 << 2) 145 #define SPARE_FORCE_SW_CTS (1 << 1) 146 #define SPARE_HW_CTS (1 << 0) 147 148 #define HDMI_NV_PDISP_SOR_PWR 0x055 149 #define SOR_PWR_SETTING_NEW (1U << 31) 150 #define SOR_PWR_SAFE_STATE_PU (1 << 16) 151 #define SOR_PWR_NORMAL_START_ALT (1 << 1) 152 #define SOR_PWR_NORMAL_STATE_PU (1 << 0) 153 154 #define HDMI_NV_PDISP_SOR_PLL0 0x057 155 #define SOR_PLL0_TX_REG_LOAD(x) (((x) & 0xf) << 28) 156 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) 157 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16) 158 #define SOR_PLL0_BG_V17_S(x) (((x) & 0xf) << 12) 159 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) 160 #define SOR_PLL0_PULLDOWN (1 << 5) 161 #define SOR_PLL0_RESISTORSEL (1 << 4) 162 #define SOR_PLL0_PDPORT (1 << 3) 163 #define SOR_PLL0_VCOPD (1 << 2) 164 #define SOR_PLL0_PDBG (1 << 1) 165 #define SOR_PLL0_PWR (1 << 0) 166 167 #define HDMI_NV_PDISP_SOR_PLL1 0x058 168 #define SOR_PLL1_S_D_PIN_PE (1 << 30) 169 #define SOR_PLL1_HALF_FULL_PE (1 << 29) 170 #define SOR_PLL1_PE_EN (1 << 28) 171 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20) 172 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9) 173 #define SOR_PLL1_TMDS_TERM (1 << 8) 174 175 #define HDMI_NV_PDISP_SOR_CSTM 0x05a 176 #define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28) 177 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) 178 #define SOR_CSTM_PLLDIV (1 << 21) 179 #define SOR_CSTM_BALANCED (1 << 19) 180 #define SOR_CSTM_NEW_MODE (1 << 18) 181 #define SOR_CSTM_DUP_SYNC (1 << 17) 182 #define SOR_CSTM_LVDS_ENABLE (1 << 16) 183 #define SOR_CSTM_LINKACTB (1 << 15) 184 #define SOR_CSTM_LINKACTA (1 << 14) 185 #define SOR_CSTM_MODE(x) (((x) & 0x3) << 12) 186 #define CSTM_MODE_LVDS 0 187 #define CSTM_MODE_TMDS 1 188 189 #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x05f 190 #define SOR_SEQ_SWITCH (1 << 30) 191 #define SOR_SEQ_STATUS (1 << 28) 192 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16) 193 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12) 194 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8) 195 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4) 196 #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0) 197 198 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x060 + (x)) 199 #define SOR_SEQ_INST_PLL_PULLDOWN (1U << 31) 200 #define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30) 201 #define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29) 202 #define SOR_SEQ_INST_BLANK_V (1 << 28) 203 #define SOR_SEQ_INST_BLANK_H (1 << 27) 204 #define SOR_SEQ_INST_BLANK_DE (1 << 26) 205 #define SOR_SEQ_INST_BLACK_DATA (1 << 25) 206 #define SOR_SEQ_INST_TRISTATE_IOS (1 << 24) 207 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23) 208 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22) 209 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21) 210 #define SOR_SEQ_INST_HALT (1 << 15) 211 #define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12) 212 #define WAIT_UNITS_US 0 213 #define WAIT_UNITS_MS 1 214 #define WAIT_UNITS_VSYNC 2 215 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0) 216 217 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x07e 218 219 #define HDMI_NV_PDISP_AUDIO_N 0x08c 220 #define AUDIO_N_LOOKUP (1 << 28) 221 #define AUDIO_N_GENERATE_ALTERNATE (1 << 24) 222 #define AUDIO_N_RESETF (1 << 20) 223 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0) 224 225 #define HDMI_NV_PDISP_SOR_REFCLK 0x095 226 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) 227 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6) 228 229 #define HDMI_NV_PDISP_INPUT_CONTROL 0x097 230 #define ARM_VIDEO_RANGE_LIMITED (1 << 1) 231 #define HDMI_SRC_DISPLAYB (1 << 0) 232 233 #define HDMI_NV_PDISP_PE_CURRENT 0x099 234 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0x0ac 235 #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29) 236 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT(x) (((x) & 0x03) << 20) 237 #define SOURCE_SELECT_AUTO 0 238 #define SOURCE_SELECT_SPDIF 1 239 #define SOURCE_SELECT_HDAL 2 240 #define SOR_AUDIO_CNTRL0_AFIFO_FLUSH (1 << 12) 241 242 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0x0ae 243 #define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27) 244 245 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320 0x0af 246 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441 0x0b0 247 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882 0x0b1 248 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764 0x0b2 249 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480 0x0b3 250 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960 0x0b4 251 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920 0x0b5 252 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0 0x0b6 253 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1 0x0b7 254 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2 0x0b8 255 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3 0x0b9 256 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0x0ba 257 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0x0bb 258 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0x0bc 259 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0x0bd 260 #define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1) 261 #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0) 262 263 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0x0bf 264 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0x0c0 265 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0x0c1 266 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0x0c2 267 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0x0c3 268 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0x0c4 269 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0x0c5 270 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0x0c6 271 272 #define HDMI_NV_PDISP_INT_STATUS 0x0cc 273 #define INT_SCRATCH (1 << 3) 274 #define INT_CP_REQUEST (1 << 2) 275 #define INT_CODEC_SCRATCH1 (1 << 1) 276 #define INT_CODEC_SCRATCH0 (1 << 0) 277 278 #define HDMI_NV_PDISP_INT_MASK 0x0cd 279 #define HDMI_NV_PDISP_INT_ENABLE 0x0ce 280 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0x0d1 281 #define HDMI_NV_PDISP_SOR_PAD_CTLS0 0x0d2 282 283 #endif /* _TEGRA_HDMI_REG_H_ */ 284