1 /*- 2 * Copyright 1992-2016 Michal Meloun 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 #ifndef _TEGRA_HDMI_REG_H_ 27 #define _TEGRA_HDMI_REG_H_ 28 29 /* 30 * !!! WARNING !!! 31 * Tegra manual uses registers index (and not register addreses). 32 * We follow the TRM notation and index is converted to offset in 33 * WR4 / RD4 macros 34 */ 35 #define HDMI_NV_PDISP_SOR_STATE0 0x001 36 #define SOR_STATE0_UPDATE (1 << 0) 37 38 #define HDMI_NV_PDISP_SOR_STATE1 0x002 39 #define SOR_STATE1_ATTACHED (1 << 3) 40 #define SOR_STATE1_ASY_ORMODE_NORMAL (1 << 2) 41 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0) 42 #define ASY_HEAD_OPMODE_SLEEP 0 43 #define ASY_HEAD_OPMODE_SNOOZE 1 44 #define ASY_HEAD_OPMODE_AWAKE 2 45 46 #define HDMI_NV_PDISP_SOR_STATE2 0x003 47 #define SOR_STATE2_ASY_DEPOL_NEG (1 << 14) 48 #define SOR_STATE2_ASY_VSYNCPOL_NEG (1 << 13) 49 #define SOR_STATE2_ASY_HSYNCPOL_NEG (1 << 12) 50 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8) 51 #define ASY_PROTOCOL_SINGLE_TMDS_A 1 52 #define ASY_PROTOCOL_CUSTOM 15 53 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6) 54 #define ASY_CRCMODE_ACTIVE 0 55 #define ASY_CRCMODE_COMPLETE 1 56 #define ASY_CRCMODE_NON_ACTIVE 2 57 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4) 58 #define ASY_SUBOWNER_NONE 0 59 #define ASY_SUBOWNER_SUBHEAD0 1 60 #define ASY_SUBOWNER_SUBHEAD1 2 61 #define SUBOWNER_BOTH 3 62 #define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0) 63 #define ASY_OWNER_NONE 0 64 #define ASY_OWNER_HEAD0 1 65 66 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x01e 67 #define AUDIO_INFOFRAME_CTRL_ENABLE (1 << 0) 68 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x01f 69 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x020 70 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x021 71 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x022 72 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) 73 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) 74 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) 75 76 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x023 77 #define AVI_INFOFRAME_CTRL_ENABLE (1 << 0) 78 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x024 79 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x025 80 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x026 81 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x027 82 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x028 83 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x029 84 85 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x02a 86 #define GENERIC_CTRL_AUDIO (1 << 16) 87 #define GENERIC_CTRL_HBLANK (1 << 12) 88 #define GENERIC_CTRL_SINGLE (1 << 8) 89 #define GENERIC_CTRL_OTHER (1 << 4) 90 #define GENERIC_CTRL_ENABLE (1 << 0) 91 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x02b 92 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x02c 93 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x02d 94 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x02e 95 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x02f 96 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x030 97 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x031 98 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x032 99 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x033 100 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x034 101 102 #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x035 103 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x036 104 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x037 105 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x038 106 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x039 107 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x03a 108 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x03b 109 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x03c 110 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x03d 111 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x03e 112 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x03f 113 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x040 114 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x041 115 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x042 116 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x043 117 #define ACR_ENABLE (1U << 31) 118 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8) 119 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0) 120 121 #define HDMI_NV_PDISP_HDMI_CTRL 0x044 122 #define HDMI_CTRL_ENABLE (1 << 30) 123 #define HDMI_CTRL_CA_SELECT (1 << 28) 124 #define HDMI_CTRL_SS_SELECT (1 << 27) 125 #define HDMI_CTRL_SF_SELECT (1 << 26) 126 #define HDMI_CTRL_CC_SELECT (1 << 25) 127 #define HDMI_CTRL_CT_SELECT (1 << 24) 128 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16) 129 #define HDMI_CTRL_SAMPLE_FLAT (1 << 12) 130 #define HDMI_CTRL_AUDIO_LAYOUT_SELECT (1 << 10) 131 #define HDMI_CTRL_AUDIO_LAYOUT (1 << 8) 132 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0) 133 134 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x046 135 #define VSYNC_WINDOW_ENABLE (1U << 31) 136 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16) 137 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0) 138 139 #define HDMI_NV_PDISP_HDMI_SPARE 0x04f 140 #define SPARE_ACR_PRIORITY (1U << 31) 141 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16) 142 #define SPARE_SUPRESS_SP_B (1 << 2) 143 #define SPARE_FORCE_SW_CTS (1 << 1) 144 #define SPARE_HW_CTS (1 << 0) 145 146 #define HDMI_NV_PDISP_SOR_PWR 0x055 147 #define SOR_PWR_SETTING_NEW (1U << 31) 148 #define SOR_PWR_SAFE_STATE_PU (1 << 16) 149 #define SOR_PWR_NORMAL_START_ALT (1 << 1) 150 #define SOR_PWR_NORMAL_STATE_PU (1 << 0) 151 152 #define HDMI_NV_PDISP_SOR_PLL0 0x057 153 #define SOR_PLL0_TX_REG_LOAD(x) (((x) & 0xf) << 28) 154 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) 155 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16) 156 #define SOR_PLL0_BG_V17_S(x) (((x) & 0xf) << 12) 157 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) 158 #define SOR_PLL0_PULLDOWN (1 << 5) 159 #define SOR_PLL0_RESISTORSEL (1 << 4) 160 #define SOR_PLL0_PDPORT (1 << 3) 161 #define SOR_PLL0_VCOPD (1 << 2) 162 #define SOR_PLL0_PDBG (1 << 1) 163 #define SOR_PLL0_PWR (1 << 0) 164 165 #define HDMI_NV_PDISP_SOR_PLL1 0x058 166 #define SOR_PLL1_S_D_PIN_PE (1 << 30) 167 #define SOR_PLL1_HALF_FULL_PE (1 << 29) 168 #define SOR_PLL1_PE_EN (1 << 28) 169 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20) 170 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9) 171 #define SOR_PLL1_TMDS_TERM (1 << 8) 172 173 #define HDMI_NV_PDISP_SOR_CSTM 0x05a 174 #define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28) 175 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) 176 #define SOR_CSTM_PLLDIV (1 << 21) 177 #define SOR_CSTM_BALANCED (1 << 19) 178 #define SOR_CSTM_NEW_MODE (1 << 18) 179 #define SOR_CSTM_DUP_SYNC (1 << 17) 180 #define SOR_CSTM_LVDS_ENABLE (1 << 16) 181 #define SOR_CSTM_LINKACTB (1 << 15) 182 #define SOR_CSTM_LINKACTA (1 << 14) 183 #define SOR_CSTM_MODE(x) (((x) & 0x3) << 12) 184 #define CSTM_MODE_LVDS 0 185 #define CSTM_MODE_TMDS 1 186 187 #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x05f 188 #define SOR_SEQ_SWITCH (1 << 30) 189 #define SOR_SEQ_STATUS (1 << 28) 190 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16) 191 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12) 192 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8) 193 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4) 194 #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0) 195 196 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x060 + (x)) 197 #define SOR_SEQ_INST_PLL_PULLDOWN (1U << 31) 198 #define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30) 199 #define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29) 200 #define SOR_SEQ_INST_BLANK_V (1 << 28) 201 #define SOR_SEQ_INST_BLANK_H (1 << 27) 202 #define SOR_SEQ_INST_BLANK_DE (1 << 26) 203 #define SOR_SEQ_INST_BLACK_DATA (1 << 25) 204 #define SOR_SEQ_INST_TRISTATE_IOS (1 << 24) 205 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23) 206 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22) 207 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21) 208 #define SOR_SEQ_INST_HALT (1 << 15) 209 #define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12) 210 #define WAIT_UNITS_US 0 211 #define WAIT_UNITS_MS 1 212 #define WAIT_UNITS_VSYNC 2 213 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0) 214 215 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x07e 216 217 #define HDMI_NV_PDISP_AUDIO_N 0x08c 218 #define AUDIO_N_LOOKUP (1 << 28) 219 #define AUDIO_N_GENERATE_ALTERNATE (1 << 24) 220 #define AUDIO_N_RESETF (1 << 20) 221 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0) 222 223 #define HDMI_NV_PDISP_SOR_REFCLK 0x095 224 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) 225 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6) 226 227 #define HDMI_NV_PDISP_INPUT_CONTROL 0x097 228 #define ARM_VIDEO_RANGE_LIMITED (1 << 1) 229 #define HDMI_SRC_DISPLAYB (1 << 0) 230 231 #define HDMI_NV_PDISP_PE_CURRENT 0x099 232 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0x0ac 233 #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29) 234 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT(x) (((x) & 0x03) << 20) 235 #define SOURCE_SELECT_AUTO 0 236 #define SOURCE_SELECT_SPDIF 1 237 #define SOURCE_SELECT_HDAL 2 238 #define SOR_AUDIO_CNTRL0_AFIFO_FLUSH (1 << 12) 239 240 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0x0ae 241 #define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27) 242 243 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320 0x0af 244 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441 0x0b0 245 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882 0x0b1 246 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764 0x0b2 247 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480 0x0b3 248 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960 0x0b4 249 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920 0x0b5 250 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0 0x0b6 251 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1 0x0b7 252 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2 0x0b8 253 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3 0x0b9 254 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0x0ba 255 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0x0bb 256 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0x0bc 257 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0x0bd 258 #define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1) 259 #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0) 260 261 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0x0bf 262 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0x0c0 263 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0x0c1 264 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0x0c2 265 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0x0c3 266 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0x0c4 267 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0x0c5 268 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0x0c6 269 270 #define HDMI_NV_PDISP_INT_STATUS 0x0cc 271 #define INT_SCRATCH (1 << 3) 272 #define INT_CP_REQUEST (1 << 2) 273 #define INT_CODEC_SCRATCH1 (1 << 1) 274 #define INT_CODEC_SCRATCH0 (1 << 0) 275 276 #define HDMI_NV_PDISP_INT_MASK 0x0cd 277 #define HDMI_NV_PDISP_INT_ENABLE 0x0ce 278 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0x0d1 279 #define HDMI_NV_PDISP_SOR_PAD_CTLS0 0x0d2 280 281 #endif /* _TEGRA_HDMI_REG_H_ */ 282