1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 #include <machine/frame.h> 47 #include <machine/intr.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 58 #if defined(SOC_MV_ARMADAXP) 59 #define MV_CLOCK_SRC get_l2clk() 60 #else 61 #define MV_CLOCK_SRC get_tclk() 62 #endif 63 64 struct mv_timer_softc { 65 struct resource * timer_res[2]; 66 bus_space_tag_t timer_bst; 67 bus_space_handle_t timer_bsh; 68 struct mtx timer_mtx; 69 struct eventtimer et; 70 }; 71 72 static struct resource_spec mv_timer_spec[] = { 73 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 74 { SYS_RES_IRQ, 0, RF_ACTIVE }, 75 { -1, 0 } 76 }; 77 78 static struct mv_timer_softc *timer_softc = NULL; 79 static int timers_initialized = 0; 80 81 static int mv_timer_probe(device_t); 82 static int mv_timer_attach(device_t); 83 84 static int mv_hardclock(void *); 85 static unsigned mv_timer_get_timecount(struct timecounter *); 86 87 static uint32_t mv_get_timer_control(void); 88 static void mv_set_timer_control(uint32_t); 89 static uint32_t mv_get_timer(uint32_t); 90 static void mv_set_timer(uint32_t, uint32_t); 91 static void mv_set_timer_rel(uint32_t, uint32_t); 92 static void mv_watchdog_enable(void); 93 static void mv_watchdog_disable(void); 94 static void mv_watchdog_event(void *, unsigned int, int *); 95 static int mv_timer_start(struct eventtimer *et, 96 sbintime_t first, sbintime_t period); 97 static int mv_timer_stop(struct eventtimer *et); 98 static void mv_setup_timers(void); 99 100 static struct timecounter mv_timer_timecounter = { 101 .tc_get_timecount = mv_timer_get_timecount, 102 .tc_name = "CPUTimer1", 103 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 104 .tc_counter_mask = ~0u, 105 .tc_quality = 1000, 106 }; 107 108 static int 109 mv_timer_probe(device_t dev) 110 { 111 112 if (!ofw_bus_is_compatible(dev, "mrvl,timer")) 113 return (ENXIO); 114 115 device_set_desc(dev, "Marvell CPU Timer"); 116 return (0); 117 } 118 119 static int 120 mv_timer_attach(device_t dev) 121 { 122 int error; 123 void *ihl; 124 struct mv_timer_softc *sc; 125 #if !defined(SOC_MV_ARMADAXP) 126 uint32_t irq_cause, irq_mask; 127 #endif 128 129 if (timer_softc != NULL) 130 return (ENXIO); 131 132 sc = (struct mv_timer_softc *)device_get_softc(dev); 133 timer_softc = sc; 134 135 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 136 if (error) { 137 device_printf(dev, "could not allocate resources\n"); 138 return (ENXIO); 139 } 140 141 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 142 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 143 144 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 145 mv_watchdog_disable(); 146 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 147 148 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 149 mv_hardclock, NULL, sc, &ihl) != 0) { 150 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 151 device_printf(dev, "Could not setup interrupt.\n"); 152 return (ENXIO); 153 } 154 155 mv_setup_timers(); 156 #if !defined(SOC_MV_ARMADAXP) 157 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 158 irq_cause &= IRQ_TIMER0_CLR; 159 160 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 161 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 162 irq_mask |= IRQ_TIMER0_MASK; 163 irq_mask &= ~IRQ_TIMER1_MASK; 164 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 165 #endif 166 sc->et.et_name = "CPUTimer0"; 167 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 168 sc->et.et_quality = 1000; 169 170 sc->et.et_frequency = MV_CLOCK_SRC; 171 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 172 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 173 sc->et.et_start = mv_timer_start; 174 sc->et.et_stop = mv_timer_stop; 175 sc->et.et_priv = sc; 176 et_register(&sc->et); 177 mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC; 178 tc_init(&mv_timer_timecounter); 179 180 return (0); 181 } 182 183 static int 184 mv_hardclock(void *arg) 185 { 186 struct mv_timer_softc *sc; 187 uint32_t irq_cause; 188 189 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 190 irq_cause &= IRQ_TIMER0_CLR; 191 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 192 193 sc = (struct mv_timer_softc *)arg; 194 if (sc->et.et_active) 195 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 196 197 return (FILTER_HANDLED); 198 } 199 200 static device_method_t mv_timer_methods[] = { 201 DEVMETHOD(device_probe, mv_timer_probe), 202 DEVMETHOD(device_attach, mv_timer_attach), 203 204 { 0, 0 } 205 }; 206 207 static driver_t mv_timer_driver = { 208 "timer", 209 mv_timer_methods, 210 sizeof(struct mv_timer_softc), 211 }; 212 213 static devclass_t mv_timer_devclass; 214 215 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0); 216 217 static unsigned 218 mv_timer_get_timecount(struct timecounter *tc) 219 { 220 221 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 222 } 223 224 void 225 cpu_initclocks(void) 226 { 227 228 cpu_initclocks_bsp(); 229 } 230 231 void 232 DELAY(int usec) 233 { 234 uint32_t val, val_temp; 235 int32_t nticks; 236 237 if (!timers_initialized) { 238 for (; usec > 0; usec--) 239 for (val = 100; val > 0; val--) 240 __asm __volatile("nop" ::: "memory"); 241 return; 242 } 243 244 val = mv_get_timer(1); 245 nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec); 246 247 while (nticks > 0) { 248 val_temp = mv_get_timer(1); 249 if (val > val_temp) 250 nticks -= (val - val_temp); 251 else 252 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 253 254 val = val_temp; 255 } 256 } 257 258 static uint32_t 259 mv_get_timer_control(void) 260 { 261 262 return (bus_space_read_4(timer_softc->timer_bst, 263 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 264 } 265 266 static void 267 mv_set_timer_control(uint32_t val) 268 { 269 270 bus_space_write_4(timer_softc->timer_bst, 271 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 272 } 273 274 static uint32_t 275 mv_get_timer(uint32_t timer) 276 { 277 278 return (bus_space_read_4(timer_softc->timer_bst, 279 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 280 } 281 282 static void 283 mv_set_timer(uint32_t timer, uint32_t val) 284 { 285 286 bus_space_write_4(timer_softc->timer_bst, 287 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 288 } 289 290 static void 291 mv_set_timer_rel(uint32_t timer, uint32_t val) 292 { 293 294 bus_space_write_4(timer_softc->timer_bst, 295 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 296 } 297 298 static void 299 mv_watchdog_enable(void) 300 { 301 uint32_t val, irq_cause; 302 #if !defined(SOC_MV_ARMADAXP) 303 uint32_t irq_mask; 304 #endif 305 306 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 307 irq_cause &= IRQ_TIMER_WD_CLR; 308 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 309 310 #if defined(SOC_MV_ARMADAXP) 311 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 312 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 313 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 314 #else 315 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 316 irq_mask |= IRQ_TIMER_WD_MASK; 317 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 318 319 val = read_cpu_ctrl(RSTOUTn_MASK); 320 val |= WD_RST_OUT_EN; 321 write_cpu_ctrl(RSTOUTn_MASK, val); 322 #endif 323 324 val = mv_get_timer_control(); 325 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; 326 mv_set_timer_control(val); 327 } 328 329 static void 330 mv_watchdog_disable(void) 331 { 332 uint32_t val, irq_cause; 333 #if !defined(SOC_MV_ARMADAXP) 334 uint32_t irq_mask; 335 #endif 336 337 val = mv_get_timer_control(); 338 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 339 mv_set_timer_control(val); 340 341 #if defined(SOC_MV_ARMADAXP) 342 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 343 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 344 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 345 #else 346 val = read_cpu_ctrl(RSTOUTn_MASK); 347 val &= ~WD_RST_OUT_EN; 348 write_cpu_ctrl(RSTOUTn_MASK, val); 349 350 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 351 irq_mask &= ~(IRQ_TIMER_WD_MASK); 352 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 353 #endif 354 355 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 356 irq_cause &= IRQ_TIMER_WD_CLR; 357 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 358 } 359 360 361 /* 362 * Watchdog event handler. 363 */ 364 static void 365 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 366 { 367 uint64_t ns; 368 uint64_t ticks; 369 370 mtx_lock(&timer_softc->timer_mtx); 371 if (cmd == 0) 372 mv_watchdog_disable(); 373 else { 374 /* 375 * Watchdog timeout is in nanosecs, calculation according to 376 * watchdog(9) 377 */ 378 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 379 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000; 380 if (ticks > MAX_WATCHDOG_TICKS) 381 mv_watchdog_disable(); 382 else { 383 /* Timer 2 is the watchdog */ 384 mv_set_timer(2, ticks); 385 mv_watchdog_enable(); 386 *error = 0; 387 } 388 } 389 mtx_unlock(&timer_softc->timer_mtx); 390 } 391 392 static int 393 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 394 { 395 struct mv_timer_softc *sc; 396 uint32_t val, val1; 397 398 /* Calculate dividers. */ 399 sc = (struct mv_timer_softc *)et->et_priv; 400 if (period != 0) 401 val = ((uint32_t)sc->et.et_frequency * period) >> 32; 402 else 403 val = 0; 404 if (first != 0) 405 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32; 406 else 407 val1 = val; 408 409 /* Apply configuration. */ 410 mv_set_timer_rel(0, val); 411 mv_set_timer(0, val1); 412 val = mv_get_timer_control(); 413 val |= CPU_TIMER0_EN; 414 if (period != 0) 415 val |= CPU_TIMER0_AUTO; 416 else 417 val &= ~CPU_TIMER0_AUTO; 418 mv_set_timer_control(val); 419 return (0); 420 } 421 422 static int 423 mv_timer_stop(struct eventtimer *et) 424 { 425 uint32_t val; 426 427 val = mv_get_timer_control(); 428 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 429 mv_set_timer_control(val); 430 return (0); 431 } 432 433 static void 434 mv_setup_timers(void) 435 { 436 uint32_t val; 437 438 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 439 mv_set_timer(1, INITIAL_TIMECOUNTER); 440 val = mv_get_timer_control(); 441 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 442 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 443 mv_set_timer_control(val); 444 timers_initialized = 1; 445 } 446