1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 6 * All rights reserved. 7 * 8 * Adapted to Marvell SoC by Semihalf. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/eventhandler.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 #include <machine/intr.h> 47 #include <machine/machdep.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 58 #define MV_TMR 0x1 59 #define MV_WDT 0x2 60 #define MV_NONE 0x0 61 62 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 63 64 #define WATCHDOG_TIMER_ARMV5 2 65 66 typedef void (*mv_watchdog_enable_t)(void); 67 typedef void (*mv_watchdog_disable_t)(void); 68 69 struct mv_timer_config { 70 enum soc_family soc_family; 71 mv_watchdog_enable_t watchdog_enable; 72 mv_watchdog_disable_t watchdog_disable; 73 unsigned int clock_src; 74 uint32_t bridge_irq_cause; 75 uint32_t irq_timer0_clr; 76 uint32_t irq_timer_wd_clr; 77 }; 78 79 struct mv_timer_softc { 80 struct resource * timer_res[2]; 81 bus_space_tag_t timer_bst; 82 bus_space_handle_t timer_bsh; 83 struct mtx timer_mtx; 84 struct eventtimer et; 85 boolean_t has_wdt; 86 struct mv_timer_config* config; 87 }; 88 89 static struct resource_spec mv_timer_spec[] = { 90 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 91 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 92 { -1, 0 } 93 }; 94 95 /* Interrupt is not required by MV_WDT devices */ 96 static struct ofw_compat_data mv_timer_compat[] = { 97 {"marvell,armada-380-timer", MV_NONE }, 98 {"marvell,armada-xp-timer", MV_TMR | MV_WDT }, 99 {"mrvl,timer", MV_TMR | MV_WDT }, 100 {NULL, MV_NONE } 101 }; 102 103 static struct mv_timer_softc *timer_softc = NULL; 104 static int timers_initialized = 0; 105 106 static int mv_timer_probe(device_t); 107 static int mv_timer_attach(device_t); 108 109 static int mv_hardclock(void *); 110 static unsigned mv_timer_get_timecount(struct timecounter *); 111 112 static uint32_t mv_get_timer_control(void); 113 static void mv_set_timer_control(uint32_t); 114 static uint32_t mv_get_timer(uint32_t); 115 static void mv_set_timer(uint32_t, uint32_t); 116 static void mv_set_timer_rel(uint32_t, uint32_t); 117 static void mv_watchdog_event(void *, unsigned int, int *); 118 static int mv_timer_start(struct eventtimer *et, 119 sbintime_t first, sbintime_t period); 120 static int mv_timer_stop(struct eventtimer *et); 121 static void mv_setup_timers(void); 122 123 static void mv_watchdog_enable_armadaxp(void); 124 static void mv_watchdog_disable_armadaxp(void); 125 126 static void mv_delay(int usec, void* arg); 127 128 static struct mv_timer_config timer_armadaxp_config = 129 { 130 MV_SOC_ARMADA_XP, 131 &mv_watchdog_enable_armadaxp, 132 &mv_watchdog_disable_armadaxp, 133 MV_CLOCK_SRC_ARMV7, 134 BRIDGE_IRQ_CAUSE_ARMADAXP, 135 IRQ_TIMER0_CLR_ARMADAXP, 136 IRQ_TIMER_WD_CLR_ARMADAXP, 137 }; 138 139 static struct ofw_compat_data mv_timer_soc_config[] = { 140 {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config }, 141 {NULL, (uintptr_t)NULL }, 142 }; 143 144 static struct timecounter mv_timer_timecounter = { 145 .tc_get_timecount = mv_timer_get_timecount, 146 .tc_name = "CPUTimer1", 147 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 148 .tc_counter_mask = ~0u, 149 .tc_quality = 1000, 150 }; 151 152 static int 153 mv_timer_probe(device_t dev) 154 { 155 156 if (!ofw_bus_status_okay(dev)) 157 return (ENXIO); 158 159 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE) 160 return (ENXIO); 161 162 device_set_desc(dev, "Marvell CPU Timer"); 163 return (0); 164 } 165 166 static int 167 mv_timer_attach(device_t dev) 168 { 169 int error; 170 void *ihl; 171 struct mv_timer_softc *sc; 172 uint32_t irq_cause, irq_mask; 173 174 if (timer_softc != NULL) 175 return (ENXIO); 176 177 sc = (struct mv_timer_softc *)device_get_softc(dev); 178 timer_softc = sc; 179 180 sc->config = (struct mv_timer_config*) 181 ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data; 182 183 if (sc->config->clock_src == 0) 184 sc->config->clock_src = get_tclk(); 185 186 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 187 if (error) { 188 device_printf(dev, "could not allocate resources\n"); 189 return (ENXIO); 190 } 191 192 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 193 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 194 195 sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt"); 196 197 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 198 199 if (sc->has_wdt) { 200 if (sc->config->watchdog_disable) 201 sc->config->watchdog_disable(); 202 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 203 } 204 205 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data 206 == MV_WDT) { 207 /* Don't set timers for wdt-only entry. */ 208 device_printf(dev, "only watchdog attached\n"); 209 return (0); 210 } else if (sc->timer_res[1] == NULL) { 211 device_printf(dev, "no interrupt resource\n"); 212 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 213 return (ENXIO); 214 } 215 216 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 217 mv_hardclock, NULL, sc, &ihl) != 0) { 218 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 219 device_printf(dev, "Could not setup interrupt.\n"); 220 return (ENXIO); 221 } 222 223 mv_setup_timers(); 224 if (sc->config->soc_family != MV_SOC_ARMADA_XP ) { 225 irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause); 226 irq_cause &= sc->config->irq_timer0_clr; 227 228 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause); 229 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 230 irq_mask |= IRQ_TIMER0_MASK; 231 irq_mask &= ~IRQ_TIMER1_MASK; 232 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 233 } 234 sc->et.et_name = "CPUTimer0"; 235 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 236 sc->et.et_quality = 1000; 237 238 sc->et.et_frequency = sc->config->clock_src; 239 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 240 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 241 sc->et.et_start = mv_timer_start; 242 sc->et.et_stop = mv_timer_stop; 243 sc->et.et_priv = sc; 244 et_register(&sc->et); 245 mv_timer_timecounter.tc_frequency = sc->config->clock_src; 246 tc_init(&mv_timer_timecounter); 247 248 #ifdef PLATFORM 249 arm_set_delay(mv_delay, NULL); 250 #endif 251 return (0); 252 } 253 254 static int 255 mv_hardclock(void *arg) 256 { 257 struct mv_timer_softc *sc; 258 uint32_t irq_cause; 259 260 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 261 irq_cause &= timer_softc->config->irq_timer0_clr; 262 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 263 264 sc = (struct mv_timer_softc *)arg; 265 if (sc->et.et_active) 266 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 267 268 return (FILTER_HANDLED); 269 } 270 271 static device_method_t mv_timer_methods[] = { 272 DEVMETHOD(device_probe, mv_timer_probe), 273 DEVMETHOD(device_attach, mv_timer_attach), 274 { 0, 0 } 275 }; 276 277 static driver_t mv_timer_driver = { 278 "timer", 279 mv_timer_methods, 280 sizeof(struct mv_timer_softc), 281 }; 282 283 DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, 0, 0); 284 285 static unsigned 286 mv_timer_get_timecount(struct timecounter *tc) 287 { 288 289 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 290 } 291 292 static void 293 mv_delay(int usec, void* arg) 294 { 295 uint32_t val, val_temp; 296 int32_t nticks; 297 298 val = mv_get_timer(1); 299 nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec); 300 301 while (nticks > 0) { 302 val_temp = mv_get_timer(1); 303 if (val > val_temp) 304 nticks -= (val - val_temp); 305 else 306 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 307 308 val = val_temp; 309 } 310 } 311 312 #ifndef PLATFORM 313 void 314 DELAY(int usec) 315 { 316 uint32_t val; 317 318 if (!timers_initialized) { 319 for (; usec > 0; usec--) 320 for (val = 100; val > 0; val--) 321 __asm __volatile("nop" ::: "memory"); 322 } else { 323 TSENTER(); 324 mv_delay(usec, NULL); 325 TSEXIT(); 326 } 327 } 328 #endif 329 330 static uint32_t 331 mv_get_timer_control(void) 332 { 333 334 return (bus_space_read_4(timer_softc->timer_bst, 335 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 336 } 337 338 static void 339 mv_set_timer_control(uint32_t val) 340 { 341 342 bus_space_write_4(timer_softc->timer_bst, 343 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 344 } 345 346 static uint32_t 347 mv_get_timer(uint32_t timer) 348 { 349 350 return (bus_space_read_4(timer_softc->timer_bst, 351 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 352 } 353 354 static void 355 mv_set_timer(uint32_t timer, uint32_t val) 356 { 357 358 bus_space_write_4(timer_softc->timer_bst, 359 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 360 } 361 362 static void 363 mv_set_timer_rel(uint32_t timer, uint32_t val) 364 { 365 366 bus_space_write_4(timer_softc->timer_bst, 367 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 368 } 369 370 static void 371 mv_watchdog_enable_armadaxp(void) 372 { 373 uint32_t irq_cause, val; 374 375 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 376 irq_cause &= timer_softc->config->irq_timer_wd_clr; 377 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 378 379 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 380 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 381 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 382 383 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 384 val &= ~RSTOUTn_MASK_WD; 385 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 386 387 val = mv_get_timer_control(); 388 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 389 mv_set_timer_control(val); 390 } 391 392 static void 393 mv_watchdog_disable_armadaxp(void) 394 { 395 uint32_t val, irq_cause; 396 397 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 398 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 399 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 400 401 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 402 val |= RSTOUTn_MASK_WD; 403 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 404 405 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 406 irq_cause &= timer_softc->config->irq_timer_wd_clr; 407 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 408 409 val = mv_get_timer_control(); 410 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 411 mv_set_timer_control(val); 412 } 413 414 /* 415 * Watchdog event handler. 416 */ 417 static void 418 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 419 { 420 uint64_t ns; 421 uint64_t ticks; 422 423 mtx_lock(&timer_softc->timer_mtx); 424 if (cmd == 0) { 425 if (timer_softc->config->watchdog_disable != NULL) 426 timer_softc->config->watchdog_disable(); 427 } else { 428 /* 429 * Watchdog timeout is in nanosecs, calculation according to 430 * watchdog(9) 431 */ 432 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 433 ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000; 434 if (ticks > MAX_WATCHDOG_TICKS) { 435 if (timer_softc->config->watchdog_disable != NULL) 436 timer_softc->config->watchdog_disable(); 437 } else { 438 mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks); 439 if (timer_softc->config->watchdog_enable != NULL) 440 timer_softc->config->watchdog_enable(); 441 *error = 0; 442 } 443 } 444 mtx_unlock(&timer_softc->timer_mtx); 445 } 446 447 static int 448 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 449 { 450 struct mv_timer_softc *sc; 451 uint32_t val, val1; 452 453 /* Calculate dividers. */ 454 sc = (struct mv_timer_softc *)et->et_priv; 455 if (period != 0) 456 val = ((uint32_t)sc->et.et_frequency * period) >> 32; 457 else 458 val = 0; 459 if (first != 0) 460 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32; 461 else 462 val1 = val; 463 464 /* Apply configuration. */ 465 mv_set_timer_rel(0, val); 466 mv_set_timer(0, val1); 467 val = mv_get_timer_control(); 468 val |= CPU_TIMER0_EN; 469 if (period != 0) 470 val |= CPU_TIMER0_AUTO; 471 else 472 val &= ~CPU_TIMER0_AUTO; 473 mv_set_timer_control(val); 474 return (0); 475 } 476 477 static int 478 mv_timer_stop(struct eventtimer *et) 479 { 480 uint32_t val; 481 482 val = mv_get_timer_control(); 483 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 484 mv_set_timer_control(val); 485 return (0); 486 } 487 488 static void 489 mv_setup_timers(void) 490 { 491 uint32_t val; 492 493 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 494 mv_set_timer(1, INITIAL_TIMECOUNTER); 495 val = mv_get_timer_control(); 496 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 497 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 498 499 if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) { 500 /* Enable 25MHz mode */ 501 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN; 502 } 503 504 mv_set_timer_control(val); 505 timers_initialized = 1; 506 } 507