1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 6 * All rights reserved. 7 * 8 * Adapted to Marvell SoC by Semihalf. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/eventhandler.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/timeet.h> 45 #include <sys/timetc.h> 46 #include <sys/watchdog.h> 47 #include <machine/bus.h> 48 #include <machine/cpu.h> 49 #include <machine/intr.h> 50 #include <machine/machdep.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #define INITIAL_TIMECOUNTER (0xffffffff) 59 #define MAX_WATCHDOG_TICKS (0xffffffff) 60 61 #define MV_TMR 0x1 62 #define MV_WDT 0x2 63 #define MV_NONE 0x0 64 65 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 66 67 #define WATCHDOG_TIMER_ARMV5 2 68 69 typedef void (*mv_watchdog_enable_t)(void); 70 typedef void (*mv_watchdog_disable_t)(void); 71 72 struct mv_timer_config { 73 enum soc_family soc_family; 74 mv_watchdog_enable_t watchdog_enable; 75 mv_watchdog_disable_t watchdog_disable; 76 unsigned int clock_src; 77 uint32_t bridge_irq_cause; 78 uint32_t irq_timer0_clr; 79 uint32_t irq_timer_wd_clr; 80 }; 81 82 struct mv_timer_softc { 83 struct resource * timer_res[2]; 84 bus_space_tag_t timer_bst; 85 bus_space_handle_t timer_bsh; 86 struct mtx timer_mtx; 87 struct eventtimer et; 88 boolean_t has_wdt; 89 struct mv_timer_config* config; 90 }; 91 92 static struct resource_spec mv_timer_spec[] = { 93 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 94 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 95 { -1, 0 } 96 }; 97 98 /* Interrupt is not required by MV_WDT devices */ 99 static struct ofw_compat_data mv_timer_compat[] = { 100 {"marvell,armada-380-timer", MV_NONE }, 101 {"marvell,armada-xp-timer", MV_TMR | MV_WDT }, 102 {"mrvl,timer", MV_TMR | MV_WDT }, 103 {NULL, MV_NONE } 104 }; 105 106 static struct mv_timer_softc *timer_softc = NULL; 107 static int timers_initialized = 0; 108 109 static int mv_timer_probe(device_t); 110 static int mv_timer_attach(device_t); 111 112 static int mv_hardclock(void *); 113 static unsigned mv_timer_get_timecount(struct timecounter *); 114 115 static uint32_t mv_get_timer_control(void); 116 static void mv_set_timer_control(uint32_t); 117 static uint32_t mv_get_timer(uint32_t); 118 static void mv_set_timer(uint32_t, uint32_t); 119 static void mv_set_timer_rel(uint32_t, uint32_t); 120 static void mv_watchdog_event(void *, unsigned int, int *); 121 static int mv_timer_start(struct eventtimer *et, 122 sbintime_t first, sbintime_t period); 123 static int mv_timer_stop(struct eventtimer *et); 124 static void mv_setup_timers(void); 125 126 static void mv_watchdog_enable_armv5(void); 127 static void mv_watchdog_enable_armadaxp(void); 128 static void mv_watchdog_disable_armv5(void); 129 static void mv_watchdog_disable_armadaxp(void); 130 131 static void mv_delay(int usec, void* arg); 132 133 static struct mv_timer_config timer_armadaxp_config = 134 { 135 MV_SOC_ARMADA_XP, 136 &mv_watchdog_enable_armadaxp, 137 &mv_watchdog_disable_armadaxp, 138 MV_CLOCK_SRC_ARMV7, 139 BRIDGE_IRQ_CAUSE_ARMADAXP, 140 IRQ_TIMER0_CLR_ARMADAXP, 141 IRQ_TIMER_WD_CLR_ARMADAXP, 142 }; 143 static struct mv_timer_config timer_armv5_config = 144 { 145 MV_SOC_ARMV5, 146 &mv_watchdog_enable_armv5, 147 &mv_watchdog_disable_armv5, 148 0, 149 BRIDGE_IRQ_CAUSE, 150 IRQ_TIMER0_CLR, 151 IRQ_TIMER_WD_CLR, 152 }; 153 154 static struct ofw_compat_data mv_timer_soc_config[] = { 155 {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config }, 156 {"mrvl,timer", (uintptr_t)&timer_armv5_config }, 157 {NULL, (uintptr_t)NULL }, 158 }; 159 160 static struct timecounter mv_timer_timecounter = { 161 .tc_get_timecount = mv_timer_get_timecount, 162 .tc_name = "CPUTimer1", 163 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 164 .tc_counter_mask = ~0u, 165 .tc_quality = 1000, 166 }; 167 168 static int 169 mv_timer_probe(device_t dev) 170 { 171 172 if (!ofw_bus_status_okay(dev)) 173 return (ENXIO); 174 175 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE) 176 return (ENXIO); 177 178 device_set_desc(dev, "Marvell CPU Timer"); 179 return (0); 180 } 181 182 static int 183 mv_timer_attach(device_t dev) 184 { 185 int error; 186 void *ihl; 187 struct mv_timer_softc *sc; 188 uint32_t irq_cause, irq_mask; 189 190 if (timer_softc != NULL) 191 return (ENXIO); 192 193 sc = (struct mv_timer_softc *)device_get_softc(dev); 194 timer_softc = sc; 195 196 sc->config = (struct mv_timer_config*) 197 ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data; 198 199 if (sc->config->clock_src == 0) 200 sc->config->clock_src = get_tclk(); 201 202 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 203 if (error) { 204 device_printf(dev, "could not allocate resources\n"); 205 return (ENXIO); 206 } 207 208 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 209 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 210 211 sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt"); 212 213 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 214 215 if (sc->has_wdt) { 216 if (sc->config->watchdog_disable) 217 sc->config->watchdog_disable(); 218 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 219 } 220 221 if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data 222 == MV_WDT) { 223 /* Don't set timers for wdt-only entry. */ 224 device_printf(dev, "only watchdog attached\n"); 225 return (0); 226 } else if (sc->timer_res[1] == NULL) { 227 device_printf(dev, "no interrupt resource\n"); 228 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 229 return (ENXIO); 230 } 231 232 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 233 mv_hardclock, NULL, sc, &ihl) != 0) { 234 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 235 device_printf(dev, "Could not setup interrupt.\n"); 236 return (ENXIO); 237 } 238 239 mv_setup_timers(); 240 if (sc->config->soc_family != MV_SOC_ARMADA_XP ) { 241 irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause); 242 irq_cause &= sc->config->irq_timer0_clr; 243 244 write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause); 245 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 246 irq_mask |= IRQ_TIMER0_MASK; 247 irq_mask &= ~IRQ_TIMER1_MASK; 248 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 249 } 250 sc->et.et_name = "CPUTimer0"; 251 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 252 sc->et.et_quality = 1000; 253 254 sc->et.et_frequency = sc->config->clock_src; 255 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; 256 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; 257 sc->et.et_start = mv_timer_start; 258 sc->et.et_stop = mv_timer_stop; 259 sc->et.et_priv = sc; 260 et_register(&sc->et); 261 mv_timer_timecounter.tc_frequency = sc->config->clock_src; 262 tc_init(&mv_timer_timecounter); 263 264 #ifdef PLATFORM 265 arm_set_delay(mv_delay, NULL); 266 #endif 267 return (0); 268 } 269 270 static int 271 mv_hardclock(void *arg) 272 { 273 struct mv_timer_softc *sc; 274 uint32_t irq_cause; 275 276 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 277 irq_cause &= timer_softc->config->irq_timer0_clr; 278 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 279 280 sc = (struct mv_timer_softc *)arg; 281 if (sc->et.et_active) 282 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 283 284 return (FILTER_HANDLED); 285 } 286 287 static device_method_t mv_timer_methods[] = { 288 DEVMETHOD(device_probe, mv_timer_probe), 289 DEVMETHOD(device_attach, mv_timer_attach), 290 { 0, 0 } 291 }; 292 293 static driver_t mv_timer_driver = { 294 "timer", 295 mv_timer_methods, 296 sizeof(struct mv_timer_softc), 297 }; 298 299 DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, 0, 0); 300 301 static unsigned 302 mv_timer_get_timecount(struct timecounter *tc) 303 { 304 305 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 306 } 307 308 static void 309 mv_delay(int usec, void* arg) 310 { 311 uint32_t val, val_temp; 312 int32_t nticks; 313 314 val = mv_get_timer(1); 315 nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec); 316 317 while (nticks > 0) { 318 val_temp = mv_get_timer(1); 319 if (val > val_temp) 320 nticks -= (val - val_temp); 321 else 322 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 323 324 val = val_temp; 325 } 326 } 327 328 #ifndef PLATFORM 329 void 330 DELAY(int usec) 331 { 332 uint32_t val; 333 334 if (!timers_initialized) { 335 for (; usec > 0; usec--) 336 for (val = 100; val > 0; val--) 337 __asm __volatile("nop" ::: "memory"); 338 } else { 339 TSENTER(); 340 mv_delay(usec, NULL); 341 TSEXIT(); 342 } 343 } 344 #endif 345 346 static uint32_t 347 mv_get_timer_control(void) 348 { 349 350 return (bus_space_read_4(timer_softc->timer_bst, 351 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 352 } 353 354 static void 355 mv_set_timer_control(uint32_t val) 356 { 357 358 bus_space_write_4(timer_softc->timer_bst, 359 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 360 } 361 362 static uint32_t 363 mv_get_timer(uint32_t timer) 364 { 365 366 return (bus_space_read_4(timer_softc->timer_bst, 367 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 368 } 369 370 static void 371 mv_set_timer(uint32_t timer, uint32_t val) 372 { 373 374 bus_space_write_4(timer_softc->timer_bst, 375 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 376 } 377 378 static void 379 mv_set_timer_rel(uint32_t timer, uint32_t val) 380 { 381 382 bus_space_write_4(timer_softc->timer_bst, 383 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 384 } 385 386 static void 387 mv_watchdog_enable_armv5(void) 388 { 389 uint32_t val, irq_cause, irq_mask; 390 391 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 392 irq_cause &= timer_softc->config->irq_timer_wd_clr; 393 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 394 395 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 396 irq_mask |= IRQ_TIMER_WD_MASK; 397 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 398 399 val = read_cpu_ctrl(RSTOUTn_MASK); 400 val |= WD_RST_OUT_EN; 401 write_cpu_ctrl(RSTOUTn_MASK, val); 402 403 val = mv_get_timer_control(); 404 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 405 mv_set_timer_control(val); 406 } 407 408 static void 409 mv_watchdog_enable_armadaxp(void) 410 { 411 uint32_t irq_cause, val; 412 413 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 414 irq_cause &= timer_softc->config->irq_timer_wd_clr; 415 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 416 417 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 418 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 419 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 420 421 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 422 val &= ~RSTOUTn_MASK_WD; 423 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 424 425 val = mv_get_timer_control(); 426 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 427 mv_set_timer_control(val); 428 } 429 430 static void 431 mv_watchdog_disable_armv5(void) 432 { 433 uint32_t val, irq_cause,irq_mask; 434 435 val = mv_get_timer_control(); 436 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 437 mv_set_timer_control(val); 438 439 val = read_cpu_ctrl(RSTOUTn_MASK); 440 val &= ~WD_RST_OUT_EN; 441 write_cpu_ctrl(RSTOUTn_MASK, val); 442 443 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 444 irq_mask &= ~(IRQ_TIMER_WD_MASK); 445 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 446 447 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 448 irq_cause &= timer_softc->config->irq_timer_wd_clr; 449 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 450 } 451 452 static void 453 mv_watchdog_disable_armadaxp(void) 454 { 455 uint32_t val, irq_cause; 456 457 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 458 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 459 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 460 461 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 462 val |= RSTOUTn_MASK_WD; 463 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 464 465 irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); 466 irq_cause &= timer_softc->config->irq_timer_wd_clr; 467 write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); 468 469 val = mv_get_timer_control(); 470 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 471 mv_set_timer_control(val); 472 } 473 474 /* 475 * Watchdog event handler. 476 */ 477 static void 478 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 479 { 480 uint64_t ns; 481 uint64_t ticks; 482 483 mtx_lock(&timer_softc->timer_mtx); 484 if (cmd == 0) { 485 if (timer_softc->config->watchdog_disable != NULL) 486 timer_softc->config->watchdog_disable(); 487 } else { 488 /* 489 * Watchdog timeout is in nanosecs, calculation according to 490 * watchdog(9) 491 */ 492 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 493 ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000; 494 if (ticks > MAX_WATCHDOG_TICKS) { 495 if (timer_softc->config->watchdog_disable != NULL) 496 timer_softc->config->watchdog_disable(); 497 } else { 498 mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks); 499 if (timer_softc->config->watchdog_enable != NULL) 500 timer_softc->config->watchdog_enable(); 501 *error = 0; 502 } 503 } 504 mtx_unlock(&timer_softc->timer_mtx); 505 } 506 507 static int 508 mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 509 { 510 struct mv_timer_softc *sc; 511 uint32_t val, val1; 512 513 /* Calculate dividers. */ 514 sc = (struct mv_timer_softc *)et->et_priv; 515 if (period != 0) 516 val = ((uint32_t)sc->et.et_frequency * period) >> 32; 517 else 518 val = 0; 519 if (first != 0) 520 val1 = ((uint32_t)sc->et.et_frequency * first) >> 32; 521 else 522 val1 = val; 523 524 /* Apply configuration. */ 525 mv_set_timer_rel(0, val); 526 mv_set_timer(0, val1); 527 val = mv_get_timer_control(); 528 val |= CPU_TIMER0_EN; 529 if (period != 0) 530 val |= CPU_TIMER0_AUTO; 531 else 532 val &= ~CPU_TIMER0_AUTO; 533 mv_set_timer_control(val); 534 return (0); 535 } 536 537 static int 538 mv_timer_stop(struct eventtimer *et) 539 { 540 uint32_t val; 541 542 val = mv_get_timer_control(); 543 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 544 mv_set_timer_control(val); 545 return (0); 546 } 547 548 static void 549 mv_setup_timers(void) 550 { 551 uint32_t val; 552 553 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 554 mv_set_timer(1, INITIAL_TIMECOUNTER); 555 val = mv_get_timer_control(); 556 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 557 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 558 559 if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) { 560 /* Enable 25MHz mode */ 561 val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN; 562 } 563 564 mv_set_timer_control(val); 565 timers_initialized = 1; 566 } 567