1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/frame.h> 46 #include <machine/intr.h> 47 48 #include <arm/mv/mvreg.h> 49 #include <arm/mv/mvvar.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #define MV_TIMER_TICK (get_tclk() / hz) 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 58 struct mv_timer_softc { 59 struct resource * timer_res[2]; 60 bus_space_tag_t timer_bst; 61 bus_space_handle_t timer_bsh; 62 struct mtx timer_mtx; 63 }; 64 65 static struct resource_spec mv_timer_spec[] = { 66 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 67 { SYS_RES_IRQ, 0, RF_ACTIVE }, 68 { -1, 0 } 69 }; 70 71 static struct mv_timer_softc *timer_softc = NULL; 72 static int timers_initialized = 0; 73 74 static int mv_timer_probe(device_t); 75 static int mv_timer_attach(device_t); 76 77 static int mv_hardclock(void *); 78 static unsigned mv_timer_get_timecount(struct timecounter *); 79 80 static uint32_t mv_get_timer_control(void); 81 static void mv_set_timer_control(uint32_t); 82 static uint32_t mv_get_timer(uint32_t); 83 static void mv_set_timer(uint32_t, uint32_t); 84 static void mv_set_timer_rel(uint32_t, uint32_t); 85 static void mv_watchdog_enable(void); 86 static void mv_watchdog_disable(void); 87 static void mv_watchdog_event(void *, unsigned int, int *); 88 static void mv_setup_timer(void); 89 static void mv_setup_timercount(void); 90 91 static struct timecounter mv_timer_timecounter = { 92 .tc_get_timecount = mv_timer_get_timecount, 93 .tc_name = "CPU Timer", 94 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 95 .tc_counter_mask = ~0u, 96 .tc_quality = 1000, 97 }; 98 99 static int 100 mv_timer_probe(device_t dev) 101 { 102 103 if (!ofw_bus_is_compatible(dev, "mrvl,timer")) 104 return (ENXIO); 105 106 device_set_desc(dev, "Marvell CPU Timer"); 107 return (0); 108 } 109 110 static int 111 mv_timer_attach(device_t dev) 112 { 113 int error; 114 void *ihl; 115 struct mv_timer_softc *sc; 116 117 if (timer_softc != NULL) 118 return (ENXIO); 119 120 sc = (struct mv_timer_softc *)device_get_softc(dev); 121 timer_softc = sc; 122 123 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 124 if (error) { 125 device_printf(dev, "could not allocate resources\n"); 126 return (ENXIO); 127 } 128 129 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 130 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 131 132 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 133 mv_watchdog_disable(); 134 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 135 136 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 137 mv_hardclock, NULL, NULL, &ihl) != 0) { 138 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 139 device_printf(dev, "could not setup hardclock interrupt\n"); 140 return (ENXIO); 141 } 142 143 mv_setup_timercount(); 144 timers_initialized = 1; 145 146 return (0); 147 } 148 149 static int 150 mv_hardclock(void *arg) 151 { 152 uint32_t irq_cause; 153 struct trapframe *frame; 154 155 frame = (struct trapframe *)arg; 156 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 157 158 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 159 irq_cause &= ~(IRQ_TIMER0); 160 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 161 162 return (FILTER_HANDLED); 163 } 164 165 static device_method_t mv_timer_methods[] = { 166 DEVMETHOD(device_probe, mv_timer_probe), 167 DEVMETHOD(device_attach, mv_timer_attach), 168 169 { 0, 0 } 170 }; 171 172 static driver_t mv_timer_driver = { 173 "timer", 174 mv_timer_methods, 175 sizeof(struct mv_timer_softc), 176 }; 177 178 static devclass_t mv_timer_devclass; 179 180 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0); 181 182 static unsigned 183 mv_timer_get_timecount(struct timecounter *tc) 184 { 185 186 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 187 } 188 189 void 190 cpu_initclocks(void) 191 { 192 uint32_t irq_cause, irq_mask; 193 194 mv_setup_timer(); 195 196 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 197 irq_cause &= ~(IRQ_TIMER0); 198 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 199 200 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 201 irq_mask |= IRQ_TIMER0_MASK; 202 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 203 204 mv_timer_timecounter.tc_frequency = get_tclk(); 205 tc_init(&mv_timer_timecounter); 206 } 207 208 void 209 cpu_startprofclock(void) 210 { 211 212 } 213 214 void 215 cpu_stopprofclock(void) 216 { 217 218 } 219 220 void 221 DELAY(int usec) 222 { 223 uint32_t val, val_temp; 224 int32_t nticks; 225 226 if (!timers_initialized) { 227 for (; usec > 0; usec--) 228 for (val = 100; val > 0; val--) 229 ; 230 return; 231 } 232 233 val = mv_get_timer(1); 234 nticks = ((get_tclk() / 1000000 + 1) * usec); 235 236 while (nticks > 0) { 237 val_temp = mv_get_timer(1); 238 if (val > val_temp) 239 nticks -= (val - val_temp); 240 else 241 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 242 243 val = val_temp; 244 } 245 } 246 247 static uint32_t 248 mv_get_timer_control(void) 249 { 250 251 return (bus_space_read_4(timer_softc->timer_bst, 252 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 253 } 254 255 static void 256 mv_set_timer_control(uint32_t val) 257 { 258 259 bus_space_write_4(timer_softc->timer_bst, 260 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 261 } 262 263 static uint32_t 264 mv_get_timer(uint32_t timer) 265 { 266 267 return (bus_space_read_4(timer_softc->timer_bst, 268 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 269 } 270 271 static void 272 mv_set_timer(uint32_t timer, uint32_t val) 273 { 274 275 bus_space_write_4(timer_softc->timer_bst, 276 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 277 } 278 279 static void 280 mv_set_timer_rel(uint32_t timer, uint32_t val) 281 { 282 283 bus_space_write_4(timer_softc->timer_bst, 284 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 285 } 286 287 static void 288 mv_watchdog_enable(void) 289 { 290 uint32_t val; 291 uint32_t irq_cause, irq_mask; 292 293 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 294 irq_cause &= ~(IRQ_TIMER_WD); 295 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 296 297 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 298 irq_mask |= IRQ_TIMER_WD_MASK; 299 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 300 301 val = read_cpu_ctrl(RSTOUTn_MASK); 302 val |= WD_RST_OUT_EN; 303 write_cpu_ctrl(RSTOUTn_MASK, val); 304 305 val = mv_get_timer_control(); 306 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; 307 mv_set_timer_control(val); 308 } 309 310 static void 311 mv_watchdog_disable(void) 312 { 313 uint32_t val; 314 uint32_t irq_cause, irq_mask; 315 316 val = mv_get_timer_control(); 317 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 318 mv_set_timer_control(val); 319 320 val = read_cpu_ctrl(RSTOUTn_MASK); 321 val &= ~WD_RST_OUT_EN; 322 write_cpu_ctrl(RSTOUTn_MASK, val); 323 324 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 325 irq_mask &= ~(IRQ_TIMER_WD_MASK); 326 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 327 328 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 329 irq_cause &= ~(IRQ_TIMER_WD); 330 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 331 } 332 333 334 /* 335 * Watchdog event handler. 336 */ 337 static void 338 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 339 { 340 uint64_t ns; 341 uint64_t ticks; 342 343 mtx_lock(&timer_softc->timer_mtx); 344 if (cmd == 0) 345 mv_watchdog_disable(); 346 else { 347 /* 348 * Watchdog timeout is in nanosecs, calculation according to 349 * watchdog(9) 350 */ 351 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 352 ticks = (uint64_t)(ns * get_tclk()) / 1000000000; 353 if (ticks > MAX_WATCHDOG_TICKS) 354 mv_watchdog_disable(); 355 else { 356 /* Timer 2 is the watchdog */ 357 mv_set_timer(2, ticks); 358 mv_watchdog_enable(); 359 *error = 0; 360 } 361 } 362 mtx_unlock(&timer_softc->timer_mtx); 363 } 364 365 static void 366 mv_setup_timer(void) 367 { 368 uint32_t val; 369 370 mv_set_timer_rel(0, MV_TIMER_TICK); 371 mv_set_timer(0, MV_TIMER_TICK); 372 val = mv_get_timer_control(); 373 val |= CPU_TIMER0_EN | CPU_TIMER0_AUTO; 374 mv_set_timer_control(val); 375 } 376 377 static void 378 mv_setup_timercount(void) 379 { 380 uint32_t val; 381 382 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 383 mv_set_timer(1, INITIAL_TIMECOUNTER); 384 val = mv_get_timer_control(); 385 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 386 mv_set_timer_control(val); 387 } 388