1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 #include <machine/frame.h> 46 #include <machine/intr.h> 47 48 #include <arm/mv/mvreg.h> 49 #include <arm/mv/mvvar.h> 50 51 #define MV_TIMER_TICK (get_tclk() / hz) 52 #define INITIAL_TIMECOUNTER (0xffffffff) 53 #define MAX_WATCHDOG_TICKS (0xffffffff) 54 55 struct mv_timer_softc { 56 struct resource * timer_res[2]; 57 bus_space_tag_t timer_bst; 58 bus_space_handle_t timer_bsh; 59 struct mtx timer_mtx; 60 }; 61 62 static struct resource_spec mv_timer_spec[] = { 63 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 64 { SYS_RES_IRQ, 0, RF_ACTIVE }, 65 { -1, 0 } 66 }; 67 68 static struct mv_timer_softc *timer_softc = NULL; 69 static int timers_initialized = 0; 70 71 static int mv_timer_probe(device_t); 72 static int mv_timer_attach(device_t); 73 74 static int mv_hardclock(void *); 75 static unsigned mv_timer_get_timecount(struct timecounter *); 76 77 static uint32_t mv_get_timer_control(void); 78 static void mv_set_timer_control(uint32_t); 79 static uint32_t mv_get_timer(uint32_t); 80 static void mv_set_timer(uint32_t, uint32_t); 81 static void mv_set_timer_rel(uint32_t, uint32_t); 82 static void mv_watchdog_enable(void); 83 static void mv_watchdog_disable(void); 84 static void mv_watchdog_event(void *, unsigned int, int *); 85 static void mv_setup_timer(void); 86 static void mv_setup_timercount(void); 87 88 static struct timecounter mv_timer_timecounter = { 89 .tc_get_timecount = mv_timer_get_timecount, 90 .tc_name = "CPU Timer", 91 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 92 .tc_counter_mask = ~0u, 93 .tc_quality = 1000, 94 }; 95 96 static int 97 mv_timer_probe(device_t dev) 98 { 99 100 device_set_desc(dev, "Marvell CPU Timer"); 101 return (0); 102 } 103 104 static int 105 mv_timer_attach(device_t dev) 106 { 107 int error; 108 void *ihl; 109 struct mv_timer_softc *sc; 110 111 if (timer_softc != NULL) 112 return (ENXIO); 113 114 sc = (struct mv_timer_softc *)device_get_softc(dev); 115 timer_softc = sc; 116 117 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 118 if (error) { 119 device_printf(dev, "could not allocate resources\n"); 120 return (ENXIO); 121 } 122 123 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 124 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 125 126 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 127 mv_watchdog_disable(); 128 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 129 130 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 131 mv_hardclock, NULL, NULL, &ihl) != 0) { 132 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 133 device_printf(dev, "could not setup hardclock interrupt\n"); 134 return (ENXIO); 135 } 136 137 mv_setup_timercount(); 138 timers_initialized = 1; 139 140 return (0); 141 } 142 143 static int 144 mv_hardclock(void *arg) 145 { 146 uint32_t irq_cause; 147 struct trapframe *frame; 148 149 frame = (struct trapframe *)arg; 150 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 151 152 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 153 irq_cause &= ~(IRQ_TIMER0); 154 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 155 156 return (FILTER_HANDLED); 157 } 158 159 static device_method_t mv_timer_methods[] = { 160 DEVMETHOD(device_probe, mv_timer_probe), 161 DEVMETHOD(device_attach, mv_timer_attach), 162 163 { 0, 0 } 164 }; 165 166 static driver_t mv_timer_driver = { 167 "timer", 168 mv_timer_methods, 169 sizeof(struct mv_timer_softc), 170 }; 171 172 static devclass_t mv_timer_devclass; 173 174 DRIVER_MODULE(timer, mbus, mv_timer_driver, mv_timer_devclass, 0, 0); 175 176 static unsigned 177 mv_timer_get_timecount(struct timecounter *tc) 178 { 179 180 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 181 } 182 183 void 184 cpu_initclocks(void) 185 { 186 uint32_t irq_cause, irq_mask; 187 188 mv_setup_timer(); 189 190 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 191 irq_cause &= ~(IRQ_TIMER0); 192 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 193 194 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 195 irq_mask |= IRQ_TIMER0_MASK; 196 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 197 198 mv_timer_timecounter.tc_frequency = get_tclk(); 199 tc_init(&mv_timer_timecounter); 200 } 201 202 void 203 cpu_startprofclock(void) 204 { 205 206 } 207 208 void 209 cpu_stopprofclock(void) 210 { 211 212 } 213 214 void 215 DELAY(int usec) 216 { 217 uint32_t val, val_temp; 218 int32_t nticks; 219 220 if (!timers_initialized) { 221 for (; usec > 0; usec--) 222 for (val = 100; val > 0; val--) 223 ; 224 return; 225 } 226 227 val = mv_get_timer(1); 228 nticks = ((get_tclk() / 1000000 + 1) * usec); 229 230 while (nticks > 0) { 231 val_temp = mv_get_timer(1); 232 if (val > val_temp) 233 nticks -= (val - val_temp); 234 else 235 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 236 237 val = val_temp; 238 } 239 } 240 241 static uint32_t 242 mv_get_timer_control(void) 243 { 244 245 return (bus_space_read_4(timer_softc->timer_bst, 246 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 247 } 248 249 static void 250 mv_set_timer_control(uint32_t val) 251 { 252 253 bus_space_write_4(timer_softc->timer_bst, 254 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 255 } 256 257 static uint32_t 258 mv_get_timer(uint32_t timer) 259 { 260 261 return (bus_space_read_4(timer_softc->timer_bst, 262 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 263 } 264 265 static void 266 mv_set_timer(uint32_t timer, uint32_t val) 267 { 268 269 bus_space_write_4(timer_softc->timer_bst, 270 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 271 } 272 273 static void 274 mv_set_timer_rel(uint32_t timer, uint32_t val) 275 { 276 277 bus_space_write_4(timer_softc->timer_bst, 278 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 279 } 280 281 static void 282 mv_watchdog_enable(void) 283 { 284 uint32_t val; 285 uint32_t irq_cause, irq_mask; 286 287 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 288 irq_cause &= ~(IRQ_TIMER_WD); 289 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 290 291 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 292 irq_mask |= IRQ_TIMER_WD_MASK; 293 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 294 295 val = read_cpu_ctrl(RSTOUTn_MASK); 296 val |= WD_RST_OUT_EN; 297 write_cpu_ctrl(RSTOUTn_MASK, val); 298 299 val = mv_get_timer_control(); 300 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; 301 mv_set_timer_control(val); 302 } 303 304 static void 305 mv_watchdog_disable(void) 306 { 307 uint32_t val; 308 uint32_t irq_cause, irq_mask; 309 310 val = mv_get_timer_control(); 311 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 312 mv_set_timer_control(val); 313 314 val = read_cpu_ctrl(RSTOUTn_MASK); 315 val &= ~WD_RST_OUT_EN; 316 write_cpu_ctrl(RSTOUTn_MASK, val); 317 318 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 319 irq_mask &= ~(IRQ_TIMER_WD_MASK); 320 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 321 322 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 323 irq_cause &= ~(IRQ_TIMER_WD); 324 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 325 } 326 327 328 /* 329 * Watchdog event handler. 330 */ 331 static void 332 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 333 { 334 uint64_t ns; 335 uint64_t ticks; 336 337 mtx_lock(&timer_softc->timer_mtx); 338 if (cmd == 0) 339 mv_watchdog_disable(); 340 else { 341 /* 342 * Watchdog timeout is in nanosecs, calculation according to 343 * watchdog(9) 344 */ 345 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 346 ticks = (uint64_t)(ns * get_tclk()) / 1000000000; 347 if (ticks > MAX_WATCHDOG_TICKS) 348 mv_watchdog_disable(); 349 else { 350 /* Timer 2 is the watchdog */ 351 mv_set_timer(2, ticks); 352 mv_watchdog_enable(); 353 *error = 0; 354 } 355 } 356 mtx_unlock(&timer_softc->timer_mtx); 357 } 358 359 static void 360 mv_setup_timer(void) 361 { 362 uint32_t val; 363 364 mv_set_timer_rel(0, MV_TIMER_TICK); 365 mv_set_timer(0, MV_TIMER_TICK); 366 val = mv_get_timer_control(); 367 val |= CPU_TIMER0_EN | CPU_TIMER0_AUTO; 368 mv_set_timer_control(val); 369 } 370 371 static void 372 mv_setup_timercount(void) 373 { 374 uint32_t val; 375 376 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 377 mv_set_timer(1, INITIAL_TIMECOUNTER); 378 val = mv_get_timer_control(); 379 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 380 mv_set_timer_control(val); 381 } 382