1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 #include <sys/watchdog.h> 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 #include <machine/frame.h> 47 #include <machine/intr.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 58 #if defined(SOC_MV_ARMADAXP) 59 #define MV_CLOCK_SRC get_l2clk() 60 #else 61 #define MV_CLOCK_SRC get_tclk() 62 #endif 63 64 struct mv_timer_softc { 65 struct resource * timer_res[2]; 66 bus_space_tag_t timer_bst; 67 bus_space_handle_t timer_bsh; 68 struct mtx timer_mtx; 69 struct eventtimer et; 70 }; 71 72 static struct resource_spec mv_timer_spec[] = { 73 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 74 { SYS_RES_IRQ, 0, RF_ACTIVE }, 75 { -1, 0 } 76 }; 77 78 static struct mv_timer_softc *timer_softc = NULL; 79 static int timers_initialized = 0; 80 81 static int mv_timer_probe(device_t); 82 static int mv_timer_attach(device_t); 83 84 static int mv_hardclock(void *); 85 static unsigned mv_timer_get_timecount(struct timecounter *); 86 87 static uint32_t mv_get_timer_control(void); 88 static void mv_set_timer_control(uint32_t); 89 static uint32_t mv_get_timer(uint32_t); 90 static void mv_set_timer(uint32_t, uint32_t); 91 static void mv_set_timer_rel(uint32_t, uint32_t); 92 static void mv_watchdog_enable(void); 93 static void mv_watchdog_disable(void); 94 static void mv_watchdog_event(void *, unsigned int, int *); 95 static int mv_timer_start(struct eventtimer *et, 96 struct bintime *first, struct bintime *period); 97 static int mv_timer_stop(struct eventtimer *et); 98 static void mv_setup_timers(void); 99 100 static struct timecounter mv_timer_timecounter = { 101 .tc_get_timecount = mv_timer_get_timecount, 102 .tc_name = "CPUTimer1", 103 .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ 104 .tc_counter_mask = ~0u, 105 .tc_quality = 1000, 106 }; 107 108 static int 109 mv_timer_probe(device_t dev) 110 { 111 112 if (!ofw_bus_is_compatible(dev, "mrvl,timer")) 113 return (ENXIO); 114 115 device_set_desc(dev, "Marvell CPU Timer"); 116 return (0); 117 } 118 119 static int 120 mv_timer_attach(device_t dev) 121 { 122 int error; 123 void *ihl; 124 struct mv_timer_softc *sc; 125 #if !defined(SOC_MV_ARMADAXP) 126 uint32_t irq_cause, irq_mask; 127 #endif 128 129 if (timer_softc != NULL) 130 return (ENXIO); 131 132 sc = (struct mv_timer_softc *)device_get_softc(dev); 133 timer_softc = sc; 134 135 error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); 136 if (error) { 137 device_printf(dev, "could not allocate resources\n"); 138 return (ENXIO); 139 } 140 141 sc->timer_bst = rman_get_bustag(sc->timer_res[0]); 142 sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); 143 144 mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); 145 mv_watchdog_disable(); 146 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 147 148 if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, 149 mv_hardclock, NULL, sc, &ihl) != 0) { 150 bus_release_resources(dev, mv_timer_spec, sc->timer_res); 151 device_printf(dev, "Could not setup interrupt.\n"); 152 return (ENXIO); 153 } 154 155 mv_setup_timers(); 156 #if !defined(SOC_MV_ARMADAXP) 157 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 158 irq_cause &= IRQ_TIMER0_CLR; 159 160 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 161 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 162 irq_mask |= IRQ_TIMER0_MASK; 163 irq_mask &= ~IRQ_TIMER1_MASK; 164 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 165 #endif 166 sc->et.et_name = "CPUTimer0"; 167 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 168 sc->et.et_quality = 1000; 169 170 sc->et.et_frequency = MV_CLOCK_SRC; 171 sc->et.et_min_period.sec = 0; 172 sc->et.et_min_period.frac = 173 ((0x00000002LLU << 32) / sc->et.et_frequency) << 32; 174 sc->et.et_max_period.sec = 0xfffffff0U / sc->et.et_frequency; 175 sc->et.et_max_period.frac = 176 ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32; 177 sc->et.et_start = mv_timer_start; 178 sc->et.et_stop = mv_timer_stop; 179 sc->et.et_priv = sc; 180 et_register(&sc->et); 181 mv_timer_timecounter.tc_frequency = MV_CLOCK_SRC; 182 tc_init(&mv_timer_timecounter); 183 184 return (0); 185 } 186 187 static int 188 mv_hardclock(void *arg) 189 { 190 struct mv_timer_softc *sc; 191 uint32_t irq_cause; 192 193 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 194 irq_cause &= IRQ_TIMER0_CLR; 195 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 196 197 sc = (struct mv_timer_softc *)arg; 198 if (sc->et.et_active) 199 sc->et.et_event_cb(&sc->et, sc->et.et_arg); 200 201 return (FILTER_HANDLED); 202 } 203 204 static device_method_t mv_timer_methods[] = { 205 DEVMETHOD(device_probe, mv_timer_probe), 206 DEVMETHOD(device_attach, mv_timer_attach), 207 208 { 0, 0 } 209 }; 210 211 static driver_t mv_timer_driver = { 212 "timer", 213 mv_timer_methods, 214 sizeof(struct mv_timer_softc), 215 }; 216 217 static devclass_t mv_timer_devclass; 218 219 DRIVER_MODULE(timer, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0); 220 221 static unsigned 222 mv_timer_get_timecount(struct timecounter *tc) 223 { 224 225 return (INITIAL_TIMECOUNTER - mv_get_timer(1)); 226 } 227 228 void 229 cpu_initclocks(void) 230 { 231 232 cpu_initclocks_bsp(); 233 } 234 235 void 236 DELAY(int usec) 237 { 238 uint32_t val, val_temp; 239 int32_t nticks; 240 241 if (!timers_initialized) { 242 for (; usec > 0; usec--) 243 for (val = 100; val > 0; val--) 244 __asm __volatile("nop" ::: "memory"); 245 return; 246 } 247 248 val = mv_get_timer(1); 249 nticks = ((MV_CLOCK_SRC / 1000000 + 1) * usec); 250 251 while (nticks > 0) { 252 val_temp = mv_get_timer(1); 253 if (val > val_temp) 254 nticks -= (val - val_temp); 255 else 256 nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); 257 258 val = val_temp; 259 } 260 } 261 262 static uint32_t 263 mv_get_timer_control(void) 264 { 265 266 return (bus_space_read_4(timer_softc->timer_bst, 267 timer_softc->timer_bsh, CPU_TIMER_CONTROL)); 268 } 269 270 static void 271 mv_set_timer_control(uint32_t val) 272 { 273 274 bus_space_write_4(timer_softc->timer_bst, 275 timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); 276 } 277 278 static uint32_t 279 mv_get_timer(uint32_t timer) 280 { 281 282 return (bus_space_read_4(timer_softc->timer_bst, 283 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); 284 } 285 286 static void 287 mv_set_timer(uint32_t timer, uint32_t val) 288 { 289 290 bus_space_write_4(timer_softc->timer_bst, 291 timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); 292 } 293 294 static void 295 mv_set_timer_rel(uint32_t timer, uint32_t val) 296 { 297 298 bus_space_write_4(timer_softc->timer_bst, 299 timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); 300 } 301 302 static void 303 mv_watchdog_enable(void) 304 { 305 uint32_t val, irq_cause; 306 #if !defined(SOC_MV_ARMADAXP) 307 uint32_t irq_mask; 308 #endif 309 310 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 311 irq_cause &= IRQ_TIMER_WD_CLR; 312 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 313 314 #if defined(SOC_MV_ARMADAXP) 315 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 316 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 317 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 318 #else 319 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 320 irq_mask |= IRQ_TIMER_WD_MASK; 321 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 322 323 val = read_cpu_ctrl(RSTOUTn_MASK); 324 val |= WD_RST_OUT_EN; 325 write_cpu_ctrl(RSTOUTn_MASK, val); 326 #endif 327 328 val = mv_get_timer_control(); 329 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO; 330 mv_set_timer_control(val); 331 } 332 333 static void 334 mv_watchdog_disable(void) 335 { 336 uint32_t val, irq_cause; 337 #if !defined(SOC_MV_ARMADAXP) 338 uint32_t irq_mask; 339 #endif 340 341 val = mv_get_timer_control(); 342 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 343 mv_set_timer_control(val); 344 345 #if defined(SOC_MV_ARMADAXP) 346 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 347 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 348 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 349 #else 350 val = read_cpu_ctrl(RSTOUTn_MASK); 351 val &= ~WD_RST_OUT_EN; 352 write_cpu_ctrl(RSTOUTn_MASK, val); 353 354 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 355 irq_mask &= ~(IRQ_TIMER_WD_MASK); 356 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 357 #endif 358 359 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 360 irq_cause &= IRQ_TIMER_WD_CLR; 361 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 362 } 363 364 365 /* 366 * Watchdog event handler. 367 */ 368 static void 369 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 370 { 371 uint64_t ns; 372 uint64_t ticks; 373 374 mtx_lock(&timer_softc->timer_mtx); 375 if (cmd == 0) 376 mv_watchdog_disable(); 377 else { 378 /* 379 * Watchdog timeout is in nanosecs, calculation according to 380 * watchdog(9) 381 */ 382 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 383 ticks = (uint64_t)(ns * MV_CLOCK_SRC) / 1000000000; 384 if (ticks > MAX_WATCHDOG_TICKS) 385 mv_watchdog_disable(); 386 else { 387 /* Timer 2 is the watchdog */ 388 mv_set_timer(2, ticks); 389 mv_watchdog_enable(); 390 *error = 0; 391 } 392 } 393 mtx_unlock(&timer_softc->timer_mtx); 394 } 395 396 static int 397 mv_timer_start(struct eventtimer *et, 398 struct bintime *first, struct bintime *period) 399 { 400 struct mv_timer_softc *sc; 401 uint32_t val, val1; 402 403 /* Calculate dividers. */ 404 sc = (struct mv_timer_softc *)et->et_priv; 405 if (period != NULL) { 406 val = (sc->et.et_frequency * (period->frac >> 32)) >> 32; 407 if (period->sec != 0) 408 val += sc->et.et_frequency * period->sec; 409 } else 410 val = 0; 411 if (first != NULL) { 412 val1 = (sc->et.et_frequency * (first->frac >> 32)) >> 32; 413 if (first->sec != 0) 414 val1 += sc->et.et_frequency * first->sec; 415 } else 416 val1 = val; 417 418 /* Apply configuration. */ 419 mv_set_timer_rel(0, val); 420 mv_set_timer(0, val1); 421 val = mv_get_timer_control(); 422 val |= CPU_TIMER0_EN; 423 if (period != NULL) 424 val |= CPU_TIMER0_AUTO; 425 else 426 val &= ~CPU_TIMER0_AUTO; 427 mv_set_timer_control(val); 428 return (0); 429 } 430 431 static int 432 mv_timer_stop(struct eventtimer *et) 433 { 434 uint32_t val; 435 436 val = mv_get_timer_control(); 437 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 438 mv_set_timer_control(val); 439 return (0); 440 } 441 442 static void 443 mv_setup_timers(void) 444 { 445 uint32_t val; 446 447 mv_set_timer_rel(1, INITIAL_TIMECOUNTER); 448 mv_set_timer(1, INITIAL_TIMECOUNTER); 449 val = mv_get_timer_control(); 450 val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); 451 val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; 452 mv_set_timer_control(val); 453 timers_initialized = 1; 454 } 455