1 /*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44 /* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48 /* SoC Regs */ 49 #define MV_PHYS_BASE 0xF1000000 50 #define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52 /* SRAM */ 53 #define MV_CESA_SRAM_BASE 0xF1100000 54 55 /* AXI Regs */ 56 #ifdef SOC_MV_DOVE 57 #define MV_AXI_PHYS_BASE 0xF1800000 58 #define MV_AXI_BASE MV_AXI_PHYS_BASE 59 #define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 60 #endif 61 62 /* 63 * External devices: 0x80000000, 1 GB (VA == PA) 64 * Includes Device Bus, PCI and PCIE. 65 */ 66 #if defined(SOC_MV_ORION) 67 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 68 #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 69 #define MV_PCI_PORTS 1 /* 1x PCIE */ 70 #elif defined(SOC_MV_DISCOVERY) 71 #define MV_PCI_PORTS 8 /* 8x PCIE */ 72 #elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 73 #define MV_PCI_PORTS 2 /* 2x PCIE */ 74 #elif defined(SOC_MV_ARMADAXP) 75 #define MV_PCI_PORTS 3 /* 3x PCIE */ 76 #else 77 #error "MV_PCI_PORTS not configured !" 78 #endif 79 80 /* PCI/PCIE Memory */ 81 #define MV_PCI_MEM_PHYS_BASE 0x80000000 82 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 83 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 84 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 85 #define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 86 MV_PCI_MEM_SLICE_SIZE)) 87 /* PCI/PCIE I/O */ 88 #define MV_PCI_IO_PHYS_BASE 0xBF000000 89 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 90 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 91 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 92 #define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 93 94 #if defined(SOC_MV_FREY) 95 #define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 96 #else 97 #define MV_PCI_VA_MEM_BASE 0 98 #endif 99 #define MV_PCI_VA_IO_BASE 0 100 101 /* 102 * Device Bus (VA == PA) 103 */ 104 #define MV_DEV_BOOT_BASE 0xF9300000 105 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 106 107 #define MV_DEV_CS0_BASE 0xF9400000 108 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 109 110 #define MV_DEV_CS1_BASE 0xF9500000 111 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 112 113 #define MV_DEV_CS2_BASE 0xFB500000 114 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 115 116 117 /* 118 * Integrated SoC peripherals addresses 119 */ 120 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 121 #if defined(SOC_MV_DOVE) 122 #define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 123 #elif defined(SOC_MV_LOKIPLUS) 124 #define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 125 #elif defined(SOC_MV_ARMADAXP) 126 #define MV_DDR_CADR_BASE (MV_BASE + 0x20180) 127 #else 128 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 129 #endif 130 #define MV_MPP_BASE (MV_BASE + 0x10000) 131 132 #if defined(SOC_MV_ARMADAXP) 133 #define MV_MISC_BASE (MV_BASE + 0x18200) 134 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 135 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 136 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 137 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 138 #elif !defined(SOC_MV_FREY) 139 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 140 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 141 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 142 #else 143 #define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 144 #endif 145 146 #define MV_PCI_BASE (MV_BASE + 0x30000) 147 #define MV_PCI_SIZE 0x2000 148 149 #if defined(SOC_MV_FREY) 150 #define MV_PCIE_BASE (MV_BASE + 0x8000) 151 #else 152 #define MV_PCIE_BASE (MV_BASE + 0x40000) 153 #endif 154 #define MV_PCIE_SIZE 0x2000 155 156 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 157 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 158 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 159 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 160 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 161 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 162 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 163 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 164 165 #define MV_SDIO_BASE (MV_BASE + 0x90000) 166 #define MV_SDIO_SIZE 0x10000 167 168 /* 169 * Decode windows definitions and macros 170 */ 171 #if defined(SOC_MV_ARMADAXP) 172 #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 173 #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 174 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 175 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 176 #else 177 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 178 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 179 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 180 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 181 #endif 182 183 #if defined(SOC_MV_DISCOVERY) 184 #define MV_WIN_CPU_MAX 14 185 #elif defined(SOC_MV_ARMADAXP) 186 #define MV_WIN_CPU_MAX 20 187 #else 188 #define MV_WIN_CPU_MAX 8 189 #endif 190 191 #define MV_WIN_CPU_ATTR_SHIFT 8 192 #if defined(SOC_MV_LOKIPLUS) 193 #define MV_WIN_CPU_TARGET_SHIFT 0 194 #define MV_WIN_CPU_ENABLE_BIT (1 << 5) 195 #else 196 #define MV_WIN_CPU_TARGET_SHIFT 4 197 #define MV_WIN_CPU_ENABLE_BIT 1 198 #endif 199 200 #if defined(SOC_MV_DOVE) 201 #define MV_WIN_DDR_MAX 2 202 #else /* SOC_MV_DOVE */ 203 #if defined(SOC_MV_LOKIPLUS) 204 #define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 205 #define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 206 #else /* SOC_MV_LOKIPLUS */ 207 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 208 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 209 #endif /* SOC_MV_LOKIPLUS */ 210 #define MV_WIN_DDR_MAX 4 211 #endif /* SOC_MV_DOVE */ 212 213 /* 214 * These values are valid only for peripherals decoding windows 215 * Bit in ATTR is zeroed according to CS bank number 216 */ 217 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 218 #define MV_WIN_DDR_TARGET 0x0 219 220 #if defined(SOC_MV_DISCOVERY) 221 #define MV_WIN_CESA_TARGET 9 222 #define MV_WIN_CESA_ATTR(eng_sel) 1 223 #elif defined(SOC_MV_ARMADAXP) 224 #define MV_WIN_CESA_TARGET 9 225 /* 226 * Bits [2:3] of cesa attribute select engine: 227 * eng_sel: 228 * 1: engine1 229 * 2: engine0 230 */ 231 #define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) 232 #else 233 #define MV_WIN_CESA_TARGET 3 234 #define MV_WIN_CESA_ATTR(eng_sel) 0 235 #endif 236 237 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 238 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 239 #define MV_WIN_USB_MAX 4 240 241 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 242 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 243 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 244 #define MV_WIN_ETH_MAX 6 245 246 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 247 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 248 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 249 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 250 #define MV_WIN_IDMA_MAX 8 251 #define MV_IDMA_CHAN_MAX 4 252 253 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 254 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 255 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 256 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 257 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 258 #define MV_WIN_XOR_MAX 8 259 #define MV_XOR_CHAN_MAX 2 260 #define MV_XOR_NON_REMAP 4 261 262 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 263 #define MV_WIN_PCIE_TARGET(n) 4 264 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 265 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0 266 #elif defined(SOC_MV_ARMADAXP) 267 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 268 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 269 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 270 #elif defined(SOC_MV_ORION) 271 #define MV_WIN_PCIE_TARGET(n) 4 272 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 273 #define MV_WIN_PCIE_IO_ATTR(n) 0x51 274 #elif defined(SOC_MV_LOKIPLUS) 275 #define MV_WIN_PCIE_TARGET(n) (3 + (n)) 276 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 277 #define MV_WIN_PCIE_IO_ATTR(n) 0x51 278 #endif 279 280 #define MV_WIN_PCI_TARGET 3 281 #define MV_WIN_PCI_MEM_ATTR 0x59 282 #define MV_WIN_PCI_IO_ATTR 0x51 283 284 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 285 (n) + 1) + 0x1820) 286 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 287 (n) + 1) + 0x1824) 288 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 289 (n) + 1) + 0x182C) 290 #define MV_WIN_PCIE_MAX 6 291 292 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 293 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 294 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 295 #define MV_PCIE_BAR_MAX 4 296 #define MV_PCIE_BAR_64BIT (0x4) 297 #define MV_PCIE_BAR_PREFETCH_EN (0x8) 298 299 #define MV_PCIE_CONTROL (0x1a00) 300 #define MV_PCIE_ROOT_CMPLX (1 << 1) 301 302 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 303 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 304 #define MV_WIN_SATA_MAX 4 305 306 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 307 static __inline uint32_t \ 308 pre ## _ ## reg ## _read(int i) \ 309 { \ 310 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 311 } 312 313 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 314 static __inline uint32_t \ 315 pre ## _ ## reg ## _read(int i, int j) \ 316 { \ 317 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 318 } \ 319 320 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 321 static __inline uint32_t \ 322 pre ## _ ## reg ## _read(uint32_t base, int i) \ 323 { \ 324 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 325 } 326 327 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 328 static __inline uint32_t \ 329 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 330 { \ 331 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 332 } 333 334 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 335 static __inline void \ 336 pre ## _ ## reg ## _write(int i, uint32_t val) \ 337 { \ 338 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 339 } 340 341 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 342 static __inline void \ 343 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 344 { \ 345 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 346 } 347 348 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 349 static __inline void \ 350 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 351 { \ 352 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 353 } 354 355 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 356 static __inline void \ 357 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 358 { \ 359 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 360 } 361 362 #define WIN_REG_RD(pre,reg,off,base) \ 363 static __inline uint32_t \ 364 pre ## _ ## reg ## _read(void) \ 365 { \ 366 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 367 } 368 369 #define WIN_REG_BASE_RD(pre,reg,off) \ 370 static __inline uint32_t \ 371 pre ## _ ## reg ## _read(uint32_t base) \ 372 { \ 373 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 374 } 375 376 #define WIN_REG_WR(pre,reg,off,base) \ 377 static __inline void \ 378 pre ## _ ## reg ## _write(uint32_t val) \ 379 { \ 380 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 381 } 382 383 #define WIN_REG_BASE_WR(pre,reg,off) \ 384 static __inline void \ 385 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 386 { \ 387 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 388 } 389 390 #endif /* _MVWIN_H_ */ 391