1 /*- 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Physical addresses of integrated SoC peripherals 39 */ 40 #define MV_PHYS_BASE 0xF1000000 41 #define MV_SIZE 0x100000 42 43 /* 44 * Decode windows addresses (physical) 45 */ 46 #define MV_PCIE_IO_PHYS_BASE (MV_PHYS_BASE + MV_SIZE) 47 #define MV_PCIE_IO_BASE MV_PCIE_IO_PHYS_BASE 48 #define MV_PCIE_IO_SIZE (1024 * 1024) 49 #define MV_PCI_IO_PHYS_BASE (MV_PCIE_IO_PHYS_BASE + MV_PCIE_IO_SIZE) 50 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 51 #define MV_PCI_IO_SIZE (1024 * 1024) 52 53 #define MV_PCIE_MEM_PHYS_BASE (MV_PCI_IO_PHYS_BASE + MV_PCI_IO_SIZE) 54 #define MV_PCIE_MEM_BASE MV_PCIE_MEM_PHYS_BASE 55 #define MV_PCIE_MEM_SIZE (64 * 1024 * 1024) 56 #define MV_PCI_MEM_PHYS_BASE (MV_PCIE_MEM_PHYS_BASE + MV_PCIE_MEM_SIZE) 57 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 58 #define MV_PCI_MEM_SIZE (64 * 1024 * 1024) 59 60 #define MV_DEV_BOOT_BASE 0xF9300000 61 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 62 63 #define MV_DEV_CS0_BASE 0xF9400000 64 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 65 66 #define MV_DEV_CS1_BASE 0xF9500000 67 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 68 69 #define MV_DEV_CS2_BASE 0xFB500000 70 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 71 72 #define MV_CESA_SRAM_PHYS_BASE 0xFD000000 73 #define MV_CESA_SRAM_BASE MV_CESA_SRAM_PHYS_BASE /* VA == PA mapping */ 74 #define MV_CESA_SRAM_SIZE (1024 * 1024) 75 76 /* XXX this is probably not robust against wraparounds... */ 77 #if ((MV_CESA_SRAM_PHYS_BASE + MV_CESA_SRAM_SIZE) > 0xFFFEFFFF) 78 #error Devices memory layout overlaps reset vectors range! 79 #endif 80 81 /* 82 * Integrated SoC peripherals addresses 83 */ 84 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 85 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 86 #define MV_MPP_BASE (MV_BASE + 0x10000) 87 88 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 89 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 90 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 91 92 #define MV_PCI_BASE (MV_BASE + 0x30000) 93 #define MV_PCI_SIZE 0x2000 94 95 #define MV_PCIE_BASE (MV_BASE + 0x40000) 96 #define MV_PCIE_SIZE 0x2000 97 98 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 99 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 100 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 101 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 102 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 103 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 104 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 105 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 106 107 /* 108 * Decode windows definitions and macros 109 */ 110 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 111 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 112 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 113 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 114 #if defined(SOC_MV_DISCOVERY) 115 #define MV_WIN_CPU_MAX 14 116 #else 117 #define MV_WIN_CPU_MAX 8 118 #endif 119 120 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 121 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 122 #define MV_WIN_DDR_MAX 4 123 124 #define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 125 #define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 126 #define MV_WIN_CESA_MAX 4 127 128 #if defined(SOC_MV_DISCOVERY) 129 #define MV_WIN_CESA_TARGET 9 130 #define MV_WIN_CESA_ATTR 1 131 #else 132 #define MV_WIN_CESA_TARGET 3 133 #define MV_WIN_CESA_ATTR 0 134 #endif 135 136 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x0) 137 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x4) 138 #define MV_WIN_USB_MAX 4 139 140 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 141 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 142 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 143 #define MV_WIN_ETH_MAX 6 144 145 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 146 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 147 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 148 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 149 #define MV_WIN_IDMA_MAX 8 150 #define MV_IDMA_CHAN_MAX 4 151 152 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 153 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 154 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 155 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 156 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 157 #define MV_WIN_XOR_MAX 8 158 #define MV_XOR_CHAN_MAX 2 159 #define MV_XOR_NON_REMAP 4 160 161 #if defined(SOC_MV_DISCOVERY) 162 #define MV_WIN_PCIE_MEM_TARGET 4 163 #define MV_WIN_PCIE_MEM_ATTR 0xE8 164 #define MV_WIN_PCIE_IO_TARGET 4 165 #define MV_WIN_PCIE_IO_ATTR 0xE0 166 #elif defined(SOC_MV_KIRKWOOD) 167 #define MV_WIN_PCIE_MEM_TARGET 4 168 #define MV_WIN_PCIE_MEM_ATTR 0xE8 169 #define MV_WIN_PCIE_IO_TARGET 4 170 #define MV_WIN_PCIE_IO_ATTR 0xE0 171 #elif defined(SOC_MV_ORION) 172 #define MV_WIN_PCIE_MEM_TARGET 4 173 #define MV_WIN_PCIE_MEM_ATTR 0x59 174 #define MV_WIN_PCIE_IO_TARGET 4 175 #define MV_WIN_PCIE_IO_ATTR 0x51 176 #define MV_WIN_PCI_MEM_TARGET 3 177 #define MV_WIN_PCI_MEM_ATTR 0x59 178 #define MV_WIN_PCI_IO_TARGET 3 179 #define MV_WIN_PCI_IO_ATTR 0x51 180 #endif 181 182 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 183 (n) + 1) + 0x1820) 184 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 185 (n) + 1) + 0x1824) 186 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 187 (n) + 1) + 0x182C) 188 #define MV_WIN_PCIE_MAX 6 189 190 #define MV_PCIE_BAR(n) (0x04 * (n) + 0x1804) 191 #define MV_PCIE_BAR_MAX 3 192 193 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 194 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 195 #define MV_WIN_SATA_MAX 4 196 197 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 198 static __inline uint32_t \ 199 pre ## _ ## reg ## _read(int i) \ 200 { \ 201 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 202 } 203 204 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 205 static __inline uint32_t \ 206 pre ## _ ## reg ## _read(int i, int j) \ 207 { \ 208 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 209 } \ 210 211 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 212 static __inline uint32_t \ 213 pre ## _ ## reg ## _read(uint32_t base, int i) \ 214 { \ 215 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 216 } 217 218 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 219 static __inline uint32_t \ 220 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 221 { \ 222 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 223 } 224 225 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 226 static __inline void \ 227 pre ## _ ## reg ## _write(int i, uint32_t val) \ 228 { \ 229 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 230 } 231 232 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 233 static __inline void \ 234 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 235 { \ 236 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 237 } 238 239 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 240 static __inline void \ 241 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 242 { \ 243 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 244 } 245 246 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 247 static __inline void \ 248 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 249 { \ 250 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 251 } 252 253 #define WIN_REG_RD(pre,reg,off,base) \ 254 static __inline uint32_t \ 255 pre ## _ ## reg ## _read(void) \ 256 { \ 257 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 258 } 259 260 #define WIN_REG_BASE_RD(pre,reg,off) \ 261 static __inline uint32_t \ 262 pre ## _ ## reg ## _read(uint32_t base) \ 263 { \ 264 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 265 } 266 267 #define WIN_REG_WR(pre,reg,off,base) \ 268 static __inline void \ 269 pre ## _ ## reg ## _write(uint32_t val) \ 270 { \ 271 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 272 } 273 274 #define WIN_REG_BASE_WR(pre,reg,off) \ 275 static __inline void \ 276 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 277 { \ 278 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 279 } 280 281 #endif /* _MVWIN_H_ */ 282