1 /*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MVWIN_H_ 35 #define _MVWIN_H_ 36 37 /* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44 /* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48 /* SoC Regs */ 49 #define MV_PHYS_BASE 0xF1000000 50 #define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52 /* SRAM */ 53 #define MV_CESA_SRAM_BASE 0xF1100000 54 55 /* AXI Regs */ 56 #ifdef SOC_MV_DOVE 57 #define MV_AXI_PHYS_BASE 0xF1800000 58 #define MV_AXI_BASE MV_AXI_PHYS_BASE 59 #define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 60 #endif 61 62 /* 63 * External devices: 0x80000000, 1 GB (VA == PA) 64 * Includes Device Bus, PCI and PCIE. 65 */ 66 #if defined(SOC_MV_ORION) 67 #define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 68 #elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 69 #define MV_PCI_PORTS 1 /* 1x PCIE */ 70 #elif defined(SOC_MV_DISCOVERY) 71 #define MV_PCI_PORTS 8 /* 8x PCIE */ 72 #elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 73 #define MV_PCI_PORTS 2 /* 2x PCIE */ 74 #elif defined(SOC_MV_ARMADAXP) 75 #define MV_PCI_PORTS 3 /* 3x PCIE */ 76 #elif defined(SOC_MV_ARMADA38X) 77 #define MV_PCI_PORTS 4 /* 4x PCIE */ 78 #else 79 #error "MV_PCI_PORTS not configured !" 80 #endif 81 82 /* PCI/PCIE Memory */ 83 #define MV_PCI_MEM_PHYS_BASE 0x80000000 84 #define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 85 #define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 86 #define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 87 #define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 88 MV_PCI_MEM_SLICE_SIZE)) 89 /* PCI/PCIE I/O */ 90 #define MV_PCI_IO_PHYS_BASE 0xBF000000 91 #define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 92 #define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 93 #define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 94 #define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 95 96 #if defined(SOC_MV_FREY) 97 #define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 98 #else 99 #define MV_PCI_VA_MEM_BASE 0 100 #endif 101 #define MV_PCI_VA_IO_BASE 0 102 103 /* 104 * Device Bus (VA == PA) 105 */ 106 #define MV_DEV_BOOT_BASE 0xF9300000 107 #define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 108 109 #define MV_DEV_CS0_BASE 0xF9400000 110 #define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 111 112 #define MV_DEV_CS1_BASE 0xF9500000 113 #define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 114 115 #define MV_DEV_CS2_BASE 0xFB500000 116 #define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 117 118 119 /* 120 * Integrated SoC peripherals addresses 121 */ 122 #define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 123 #if defined(SOC_MV_DOVE) 124 #define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 125 #elif defined(SOC_MV_LOKIPLUS) 126 #define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 127 #elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 128 #define MV_DDR_CADR_BASE (MV_BASE + 0x20180) 129 #else 130 #define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 131 #endif 132 #define MV_MPP_BASE (MV_BASE + 0x10000) 133 134 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 135 #define MV_MISC_BASE (MV_BASE + 0x18200) 136 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 137 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 138 #define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 139 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 140 #elif !defined(SOC_MV_FREY) 141 #define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 142 #define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 143 #define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 144 #else 145 #define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 146 #endif 147 148 #define MV_PCI_BASE (MV_BASE + 0x30000) 149 #define MV_PCI_SIZE 0x2000 150 151 #if defined(SOC_MV_FREY) 152 #define MV_PCIE_BASE (MV_BASE + 0x8000) 153 #elif defined(SOC_MV_ARMADA38X) 154 #define MV_PCIE_BASE (MV_BASE + 0x80000) 155 #else 156 #define MV_PCIE_BASE (MV_BASE + 0x40000) 157 #endif 158 #define MV_PCIE_SIZE 0x2000 159 160 #define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 161 #define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 162 #define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 163 #define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 164 #define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 165 #define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 166 #define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 167 #define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 168 169 #define MV_SDIO_BASE (MV_BASE + 0x90000) 170 #define MV_SDIO_SIZE 0x10000 171 172 /* 173 * Decode windows definitions and macros 174 */ 175 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 176 #define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 177 #define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 178 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 179 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 180 #else 181 #define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 182 #define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 183 #define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 184 #define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 185 #endif 186 187 #if defined(SOC_MV_DISCOVERY) 188 #define MV_WIN_CPU_MAX 14 189 #elif defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 190 #define MV_WIN_CPU_MAX 20 191 #else 192 #define MV_WIN_CPU_MAX 8 193 #endif 194 195 #define MV_WIN_CPU_ATTR_SHIFT 8 196 #if defined(SOC_MV_LOKIPLUS) 197 #define MV_WIN_CPU_TARGET_SHIFT 0 198 #define MV_WIN_CPU_ENABLE_BIT (1 << 5) 199 #else 200 #define MV_WIN_CPU_TARGET_SHIFT 4 201 #define MV_WIN_CPU_ENABLE_BIT 1 202 #endif 203 204 #if defined(SOC_MV_DOVE) 205 #define MV_WIN_DDR_MAX 2 206 #else /* SOC_MV_DOVE */ 207 #if defined(SOC_MV_LOKIPLUS) 208 #define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 209 #define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 210 #else /* SOC_MV_LOKIPLUS */ 211 #define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 212 #define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 213 #endif /* SOC_MV_LOKIPLUS */ 214 #define MV_WIN_DDR_MAX 4 215 #endif /* SOC_MV_DOVE */ 216 217 /* 218 * These values are valid only for peripherals decoding windows 219 * Bit in ATTR is zeroed according to CS bank number 220 */ 221 #define MV_WIN_DDR_ATTR(cs) (0x0F & ~(0x01 << (cs))) 222 #define MV_WIN_DDR_TARGET 0x0 223 224 #if defined(SOC_MV_DISCOVERY) 225 #define MV_WIN_CESA_TARGET 9 226 #define MV_WIN_CESA_ATTR(eng_sel) 1 227 #elif defined(SOC_MV_ARMADAXP) 228 #define MV_WIN_CESA_TARGET 9 229 /* 230 * Bits [2:3] of cesa attribute select engine: 231 * eng_sel: 232 * 1: engine1 233 * 2: engine0 234 */ 235 #define MV_WIN_CESA_ATTR(eng_sel) (1 | ((eng_sel) << 2)) 236 #else 237 #define MV_WIN_CESA_TARGET 3 238 #define MV_WIN_CESA_ATTR(eng_sel) 0 239 #endif 240 241 #define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 242 #define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 243 #define MV_WIN_USB_MAX 4 244 245 #define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 246 #define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 247 #define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 248 #define MV_WIN_ETH_MAX 6 249 250 #define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 251 #define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 252 #define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 253 #define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 254 #define MV_WIN_IDMA_MAX 8 255 #define MV_IDMA_CHAN_MAX 4 256 257 #define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 258 #define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 259 #define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 260 #define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 261 #define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 262 #define MV_WIN_XOR_MAX 8 263 #define MV_XOR_CHAN_MAX 2 264 #define MV_XOR_NON_REMAP 4 265 266 #if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 267 #define MV_WIN_PCIE_TARGET(n) 4 268 #define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 269 #define MV_WIN_PCIE_IO_ATTR(n) 0xE0 270 #elif defined(SOC_MV_ARMADAXP) 271 #define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 272 #define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 273 #define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 274 #elif defined(SOC_MV_ARMADA38X) 275 #define MV_WIN_PCIE_TARGET(n) ((n) == 0 ? 8 : 4) 276 #define MV_WIN_PCIE_MEM_ATTR(n) ((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20))) 277 #define MV_WIN_PCIE_IO_ATTR(n) ((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20))) 278 #elif defined(SOC_MV_ORION) 279 #define MV_WIN_PCIE_TARGET(n) 4 280 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 281 #define MV_WIN_PCIE_IO_ATTR(n) 0x51 282 #elif defined(SOC_MV_LOKIPLUS) 283 #define MV_WIN_PCIE_TARGET(n) (3 + (n)) 284 #define MV_WIN_PCIE_MEM_ATTR(n) 0x59 285 #define MV_WIN_PCIE_IO_ATTR(n) 0x51 286 #endif 287 288 #define MV_WIN_PCI_TARGET 3 289 #define MV_WIN_PCI_MEM_ATTR 0x59 290 #define MV_WIN_PCI_IO_ATTR 0x51 291 292 #define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 293 (n) + 1) + 0x1820) 294 #define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 295 (n) + 1) + 0x1824) 296 #define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 297 (n) + 1) + 0x182C) 298 #define MV_WIN_PCIE_MAX 6 299 300 #define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 301 #define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 302 #define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 303 #define MV_PCIE_BAR_MAX 4 304 #define MV_PCIE_BAR_64BIT (0x4) 305 #define MV_PCIE_BAR_PREFETCH_EN (0x8) 306 307 #define MV_PCIE_CONTROL (0x1a00) 308 #define MV_PCIE_ROOT_CMPLX (1 << 1) 309 310 #define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 311 #define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 312 #define MV_WIN_SATA_MAX 4 313 314 #if defined(SOC_MV_ARMADA38X) 315 #define MV_BOOTROM_MEM_ADDR 0xFFF00000 316 #define MV_BOOTROM_WIN_SIZE 0xF 317 #define MV_CPU_SUBSYS_REGS_LEN 0x100 318 319 /* IO Window Control Register fields */ 320 #define IO_WIN_SIZE_SHIFT 16 321 #define IO_WIN_SIZE_MASK 0xFFFF 322 #define IO_WIN_ATTR_SHIFT 8 323 #define IO_WIN_ATTR_MASK 0xFF 324 #define IO_WIN_TGT_SHIFT 4 325 #define IO_WIN_TGT_MASK 0xF 326 #define IO_WIN_SYNC_SHIFT 1 327 #define IO_WIN_SYNC_MASK 0x1 328 #define IO_WIN_ENA_SHIFT 0 329 #define IO_WIN_ENA_MASK 0x1 330 331 #define IO_WIN_9_CTRL_OFFSET 0x98 332 #define IO_WIN_9_BASE_OFFSET 0x9C 333 334 /* Mbus decoding unit IDs and attributes */ 335 #define MBUS_BOOTROM_TGT_ID 0x1 336 #define MBUS_BOOTROM_ATTR 0x1D 337 338 /* Internal Units Sync Barrier Control Register */ 339 #define MV_SYNC_BARRIER_CTRL 0x84 340 #define MV_SYNC_BARRIER_CTRL_ALL 0xFFFF 341 #endif 342 343 #define WIN_REG_IDX_RD(pre,reg,off,base) \ 344 static __inline uint32_t \ 345 pre ## _ ## reg ## _read(int i) \ 346 { \ 347 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 348 } 349 350 #define WIN_REG_IDX_RD2(pre,reg,off,base) \ 351 static __inline uint32_t \ 352 pre ## _ ## reg ## _read(int i, int j) \ 353 { \ 354 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 355 } \ 356 357 #define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 358 static __inline uint32_t \ 359 pre ## _ ## reg ## _read(uint32_t base, int i) \ 360 { \ 361 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 362 } 363 364 #define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 365 static __inline uint32_t \ 366 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 367 { \ 368 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 369 } 370 371 #define WIN_REG_IDX_WR(pre,reg,off,base) \ 372 static __inline void \ 373 pre ## _ ## reg ## _write(int i, uint32_t val) \ 374 { \ 375 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 376 } 377 378 #define WIN_REG_IDX_WR2(pre,reg,off,base) \ 379 static __inline void \ 380 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 381 { \ 382 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 383 } 384 385 #define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 386 static __inline void \ 387 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 388 { \ 389 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 390 } 391 392 #define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 393 static __inline void \ 394 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 395 { \ 396 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 397 } 398 399 #define WIN_REG_RD(pre,reg,off,base) \ 400 static __inline uint32_t \ 401 pre ## _ ## reg ## _read(void) \ 402 { \ 403 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 404 } 405 406 #define WIN_REG_BASE_RD(pre,reg,off) \ 407 static __inline uint32_t \ 408 pre ## _ ## reg ## _read(uint32_t base) \ 409 { \ 410 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 411 } 412 413 #define WIN_REG_WR(pre,reg,off,base) \ 414 static __inline void \ 415 pre ## _ ## reg ## _write(uint32_t val) \ 416 { \ 417 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 418 } 419 420 #define WIN_REG_BASE_WR(pre,reg,off) \ 421 static __inline void \ 422 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 423 { \ 424 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 425 } 426 427 #endif /* _MVWIN_H_ */ 428