1 /*- 2 * Copyright (c) 2002, 2003 Wasabi Systems, Inc. 3 * All rights reserved. 4 * 5 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed for the NetBSD Project by 18 * Wasabi Systems, Inc. 19 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 20 * or promote products derived from this software without specific prior 21 * written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1 36 * 37 * $FreeBSD$ 38 */ 39 40 #ifndef _MVVAR_H_ 41 #define _MVVAR_H_ 42 43 #include <sys/rman.h> 44 #include <vm/vm.h> 45 #include <vm/pmap.h> 46 #include <machine/pmap.h> 47 #include <machine/vm.h> 48 49 #define MV_TYPE_PCI 0 50 #define MV_TYPE_PCIE 1 51 #define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */ 52 53 struct obio_softc { 54 bus_space_tag_t obio_bst; /* bus space tag */ 55 struct rman obio_mem; 56 struct rman obio_irq; 57 struct rman obio_gpio; 58 }; 59 60 struct obio_device { 61 const char *od_name; 62 u_long od_base; 63 u_long od_size; 64 u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */ 65 u_int od_gpio[2 + 1]; /* as above for IRQ */ 66 u_int od_pwr_mask; 67 struct resource_list od_resources; 68 }; 69 70 struct obio_pci_irq_map { 71 int opim_slot; 72 int opim_pin; 73 int opim_irq; 74 }; 75 76 struct obio_pci { 77 int op_type; 78 79 bus_addr_t op_base; 80 u_long op_size; 81 82 /* Note IO/MEM regions are assumed VA == PA */ 83 bus_addr_t op_io_base; 84 u_long op_io_size; 85 int op_io_win_target; 86 int op_io_win_attr; 87 88 bus_addr_t op_mem_base; 89 u_long op_mem_size; 90 int op_mem_win_target; 91 int op_mem_win_attr; 92 93 const struct obio_pci_irq_map *op_pci_irq_map; 94 int op_irq; /* used if IRQ map table is NULL */ 95 }; 96 97 struct gpio_config { 98 int gc_gpio; /* GPIO number */ 99 uint32_t gc_flags; /* GPIO flags */ 100 int gc_output; /* GPIO output value */ 101 }; 102 103 struct decode_win { 104 int target; /* Mbus unit ID */ 105 int attr; /* Attributes of the target interface */ 106 vm_paddr_t base; /* Physical base addr */ 107 uint32_t size; 108 int remap; 109 }; 110 111 extern const struct pmap_devmap pmap_devmap[]; 112 extern const struct obio_pci mv_pci_info[]; 113 extern const struct gpio_config mv_gpio_config[]; 114 extern bus_space_tag_t obio_tag; 115 extern struct obio_device obio_devices[]; 116 extern const struct decode_win *cpu_wins; 117 extern const struct decode_win *idma_wins; 118 extern const struct decode_win *xor_wins; 119 extern int cpu_wins_no; 120 extern int idma_wins_no; 121 extern int xor_wins_no; 122 123 /* Function prototypes */ 124 int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt, 125 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep); 126 void mv_gpio_intr_mask(int pin); 127 void mv_gpio_intr_unmask(int pin); 128 int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask); 129 void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable); 130 uint8_t mv_gpio_in(uint32_t pin); 131 132 void platform_mpp_init(void); 133 int soc_decode_win(void); 134 void soc_id(uint32_t *dev, uint32_t *rev); 135 void soc_identify(void); 136 void soc_dump_decode_win(void); 137 uint32_t soc_power_ctrl_get(uint32_t mask); 138 void soc_power_ctrl_set(uint32_t mask); 139 140 int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 141 int remap); 142 int decode_win_overlap(int, int, const struct decode_win *); 143 int win_cpu_can_remap(int); 144 145 void decode_win_idma_dump(void); 146 void decode_win_idma_setup(void); 147 int decode_win_idma_valid(void); 148 149 void decode_win_xor_dump(void); 150 void decode_win_xor_setup(void); 151 int decode_win_xor_valid(void); 152 153 int ddr_is_active(int i); 154 uint32_t ddr_base(int i); 155 uint32_t ddr_size(int i); 156 uint32_t ddr_attr(int i); 157 uint32_t ddr_target(int i); 158 159 uint32_t cpu_extra_feat(void); 160 uint32_t get_tclk(void); 161 uint32_t read_cpu_ctrl(uint32_t); 162 void write_cpu_ctrl(uint32_t, uint32_t); 163 164 enum mbus_device_ivars { 165 MBUS_IVAR_BASE, 166 }; 167 168 #define MBUS_ACCESSOR(var, ivar, type) \ 169 __BUS_ACCESSOR(mbus, var, MBUS, ivar, type) 170 171 MBUS_ACCESSOR(base, BASE, u_long) 172 173 #undef MBUS_ACCESSOR 174 175 #endif /* _MVVAR_H_ */ 176