1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 5 * Copyright (c) 2010 The FreeBSD Foundation 6 * Copyright (c) 2010-2015 Semihalf 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Portions of this software were developed by Semihalf 12 * under sponsorship from the FreeBSD Foundation. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of MARVELL nor the names of contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Marvell integrated PCI/PCI-Express controller driver. 41 */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/lock.h> 47 #include <sys/malloc.h> 48 #include <sys/module.h> 49 #include <sys/mutex.h> 50 #include <sys/queue.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/endian.h> 54 #include <sys/devmap.h> 55 56 #include <machine/fdt.h> 57 #include <machine/intr.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_bus_subr.h> 65 #include <dev/ofw/ofw_pci.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 #include <machine/resource.h> 74 #include <machine/bus.h> 75 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvvar.h> 78 #include <arm/mv/mvwin.h> 79 80 #ifdef DEBUG 81 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 82 #else 83 #define debugf(fmt, args...) 84 #endif 85 86 /* 87 * Code and data related to fdt-based PCI configuration. 88 * 89 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 90 * always Marvell-specific so that was deleted and the code now lives here. 91 */ 92 93 struct mv_pci_range { 94 u_long base_pci; 95 u_long base_parent; 96 u_long len; 97 }; 98 99 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 100 #define PCI_SPACE_LEN 0x00400000 101 102 static void 103 mv_pci_range_dump(struct mv_pci_range *range) 104 { 105 #ifdef DEBUG 106 printf("\n"); 107 printf(" base_pci = 0x%08lx\n", range->base_pci); 108 printf(" base_par = 0x%08lx\n", range->base_parent); 109 printf(" len = 0x%08lx\n", range->len); 110 #endif 111 } 112 113 static int 114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115 struct mv_pci_range *mem_space) 116 { 117 pcell_t ranges[FDT_RANGES_CELLS]; 118 struct mv_pci_range *pci_space; 119 pcell_t addr_cells, size_cells, par_addr_cells; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell2; 122 int tuple_size, tuples, i, rv, offset_cells, len; 123 int portid, is_io_space; 124 125 /* 126 * Retrieve 'ranges' property. 127 */ 128 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 129 return (EINVAL); 130 if (addr_cells != 3 || size_cells != 2) 131 return (ERANGE); 132 133 par_addr_cells = fdt_parent_addr_cells(node); 134 if (par_addr_cells > 3) 135 return (ERANGE); 136 137 len = OF_getproplen(node, "ranges"); 138 if (len > sizeof(ranges)) 139 return (ENOMEM); 140 141 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 142 return (EINVAL); 143 144 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 145 size_cells); 146 tuples = len / tuple_size; 147 148 /* 149 * Initialize the ranges so that we don't have to worry about 150 * having them all defined in the FDT. In particular, it is 151 * perfectly fine not to want I/O space on PCI buses. 152 */ 153 bzero(io_space, sizeof(*io_space)); 154 bzero(mem_space, sizeof(*mem_space)); 155 156 rangesptr = &ranges[0]; 157 offset_cells = 0; 158 for (i = 0; i < tuples; i++) { 159 cell0 = fdt_data_get((void *)rangesptr, 1); 160 rangesptr++; 161 /* cell1 */ 162 rangesptr++; 163 cell2 = fdt_data_get((void *)rangesptr, 1); 164 rangesptr++; 165 portid = fdt_data_get((void *)(rangesptr+1), 1); 166 167 if (cell0 & 0x02000000) { 168 pci_space = mem_space; 169 is_io_space = 0; 170 } else if (cell0 & 0x01000000) { 171 pci_space = io_space; 172 is_io_space = 1; 173 } else { 174 rv = ERANGE; 175 goto out; 176 } 177 178 if (par_addr_cells == 3) { 179 /* 180 * This is a PCI subnode 'ranges'. Skip cell0 and 181 * cell1 of this entry and only use cell2. 182 */ 183 offset_cells = 2; 184 rangesptr += offset_cells; 185 } 186 187 if ((par_addr_cells - offset_cells) > 2) { 188 rv = ERANGE; 189 goto out; 190 } 191 pci_space->base_parent = fdt_data_get((void *)rangesptr, 192 par_addr_cells - offset_cells); 193 rangesptr += par_addr_cells - offset_cells; 194 195 if (size_cells > 2) { 196 rv = ERANGE; 197 goto out; 198 } 199 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 200 rangesptr += size_cells; 201 202 pci_space->base_pci = cell2; 203 204 if (pci_space->len == 0) { 205 pci_space->len = PCI_SPACE_LEN; 206 pci_space->base_parent = fdt_immr_va + 207 PCI_SPACE_LEN * ( 2 * portid + is_io_space); 208 } 209 } 210 rv = 0; 211 out: 212 return (rv); 213 } 214 215 static int 216 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 217 struct mv_pci_range *mem_space) 218 { 219 int err; 220 221 debugf("Processing PCI node: %x\n", node); 222 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 223 debugf("could not decode parent PCI node 'ranges'\n"); 224 return (err); 225 } 226 227 debugf("Post fixup dump:\n"); 228 mv_pci_range_dump(io_space); 229 mv_pci_range_dump(mem_space); 230 return (0); 231 } 232 233 int 234 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 235 vm_offset_t mem_va) 236 { 237 struct mv_pci_range io_space, mem_space; 238 int error; 239 240 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 241 return (error); 242 243 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 244 devmap->pd_pa = io_space.base_parent; 245 devmap->pd_size = io_space.len; 246 devmap++; 247 248 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 249 devmap->pd_pa = mem_space.base_parent; 250 devmap->pd_size = mem_space.len; 251 return (0); 252 } 253 254 /* 255 * Code and data related to the Marvell pcib driver. 256 */ 257 258 #define PCI_CFG_ENA (1U << 31) 259 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 260 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 261 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 262 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 263 264 #define PCI_REG_CFG_ADDR 0x0C78 265 #define PCI_REG_CFG_DATA 0x0C7C 266 267 #define PCIE_REG_CFG_ADDR 0x18F8 268 #define PCIE_REG_CFG_DATA 0x18FC 269 #define PCIE_REG_CONTROL 0x1A00 270 #define PCIE_CTRL_LINK1X 0x00000001 271 #define PCIE_REG_STATUS 0x1A04 272 #define PCIE_REG_IRQ_MASK 0x1910 273 274 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 275 #define PCIE_CONTROL_HOT_RESET (1 << 24) 276 277 #define PCIE_LINK_TIMEOUT 1000000 278 279 #define PCIE_STATUS_LINK_DOWN 1 280 #define PCIE_STATUS_DEV_OFFS 16 281 282 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 283 #define PCI_MIN_IO_ALLOC 4 284 #define PCI_MIN_MEM_ALLOC 16 285 286 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 287 288 struct mv_pcib_softc { 289 device_t sc_dev; 290 291 struct rman sc_mem_rman; 292 bus_addr_t sc_mem_base; 293 bus_addr_t sc_mem_size; 294 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 295 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 296 int sc_win_target; 297 int sc_mem_win_attr; 298 299 struct rman sc_io_rman; 300 bus_addr_t sc_io_base; 301 bus_addr_t sc_io_size; 302 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 303 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 304 int sc_io_win_attr; 305 306 struct resource *sc_res; 307 bus_space_handle_t sc_bsh; 308 bus_space_tag_t sc_bst; 309 int sc_rid; 310 311 struct mtx sc_msi_mtx; 312 uint32_t sc_msi_bitmap; 313 314 int sc_busnr; /* Host bridge bus number */ 315 int sc_devnr; /* Host bridge device number */ 316 int sc_type; 317 int sc_mode; /* Endpoint / Root Complex */ 318 319 int sc_msi_supported; 320 int sc_skip_enable_procedure; 321 int sc_enable_find_root_slot; 322 struct ofw_bus_iinfo sc_pci_iinfo; 323 324 int ap_segment; /* PCI domain */ 325 }; 326 327 /* Local forward prototypes */ 328 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 329 static void mv_pcib_hw_cfginit(void); 330 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 331 u_int, u_int, int); 332 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 333 u_int, u_int, uint32_t, int); 334 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 335 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 336 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 337 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 338 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 339 static int mv_pcib_mem_init(struct mv_pcib_softc *); 340 341 /* Forward prototypes */ 342 static int mv_pcib_probe(device_t); 343 static int mv_pcib_attach(device_t); 344 345 static struct rman *mv_pcib_get_rman(device_t, int, u_int); 346 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 347 rman_res_t, rman_res_t, rman_res_t, u_int); 348 static int mv_pcib_adjust_resource(device_t, device_t, struct resource *, 349 rman_res_t, rman_res_t); 350 static int mv_pcib_release_resource(device_t, device_t, struct resource *); 351 static int mv_pcib_activate_resource(device_t, device_t, struct resource *); 352 static int mv_pcib_deactivate_resource(device_t, device_t, struct resource *); 353 static int mv_pcib_map_resource(device_t, device_t, struct resource *, 354 struct resource_map_request *, struct resource_map *); 355 static int mv_pcib_unmap_resource(device_t, device_t, struct resource *, 356 struct resource_map *); 357 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 358 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 359 360 static int mv_pcib_maxslots(device_t); 361 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 362 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 363 uint32_t, int); 364 static int mv_pcib_route_interrupt(device_t, device_t, int); 365 366 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 367 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 368 static int mv_pcib_release_msi(device_t, device_t, int, int *); 369 370 /* 371 * Bus interface definitions. 372 */ 373 static device_method_t mv_pcib_methods[] = { 374 /* Device interface */ 375 DEVMETHOD(device_probe, mv_pcib_probe), 376 DEVMETHOD(device_attach, mv_pcib_attach), 377 378 /* Bus interface */ 379 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 380 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 381 DEVMETHOD(bus_get_rman, mv_pcib_get_rman), 382 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 383 DEVMETHOD(bus_adjust_resource, mv_pcib_adjust_resource), 384 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 385 DEVMETHOD(bus_activate_resource, mv_pcib_activate_resource), 386 DEVMETHOD(bus_deactivate_resource, mv_pcib_deactivate_resource), 387 DEVMETHOD(bus_map_resource, mv_pcib_map_resource), 388 DEVMETHOD(bus_unmap_resource, mv_pcib_unmap_resource), 389 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 390 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 391 392 /* pcib interface */ 393 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 394 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 395 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 396 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 397 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 398 399 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 400 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 401 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 402 403 /* OFW bus interface */ 404 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 405 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 406 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 407 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 408 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 409 410 DEVMETHOD_END 411 }; 412 413 static driver_t mv_pcib_driver = { 414 "pcib", 415 mv_pcib_methods, 416 sizeof(struct mv_pcib_softc), 417 }; 418 419 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0); 420 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0); 421 422 static struct mtx pcicfg_mtx; 423 424 static int 425 mv_pcib_probe(device_t self) 426 { 427 phandle_t node; 428 429 node = ofw_bus_get_node(self); 430 if (!mv_fdt_is_type(node, "pci")) 431 return (ENXIO); 432 433 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 434 ofw_bus_is_compatible(self, "mrvl,pci") || 435 ofw_bus_node_is_compatible( 436 OF_parent(node), "marvell,armada-370-pcie"))) 437 return (ENXIO); 438 439 if (!ofw_bus_status_okay(self)) 440 return (ENXIO); 441 442 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 443 return (BUS_PROBE_DEFAULT); 444 } 445 446 static int 447 mv_pcib_attach(device_t self) 448 { 449 struct mv_pcib_softc *sc; 450 phandle_t node, parnode; 451 uint32_t val, reg0; 452 int err, bus, devfn, port_id; 453 454 sc = device_get_softc(self); 455 sc->sc_dev = self; 456 457 node = ofw_bus_get_node(self); 458 parnode = OF_parent(node); 459 460 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), 461 sizeof(port_id)) <= 0) { 462 /* If port ID does not exist in the FDT set value to 0 */ 463 if (!OF_hasprop(node, "marvell,pcie-port")) 464 port_id = 0; 465 else 466 return(ENXIO); 467 } 468 469 sc->ap_segment = port_id; 470 471 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) { 472 sc->sc_type = MV_TYPE_PCIE; 473 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); 474 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); 475 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); 476 sc->sc_skip_enable_procedure = 1; 477 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { 478 sc->sc_type = MV_TYPE_PCIE; 479 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); 480 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); 481 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); 482 sc->sc_enable_find_root_slot = 1; 483 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) { 484 sc->sc_type = MV_TYPE_PCI; 485 sc->sc_win_target = MV_WIN_PCI_TARGET; 486 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 487 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 488 } else 489 return (ENXIO); 490 491 /* 492 * Retrieve our mem-mapped registers range. 493 */ 494 sc->sc_rid = 0; 495 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 496 RF_ACTIVE); 497 if (sc->sc_res == NULL) { 498 device_printf(self, "could not map memory\n"); 499 return (ENXIO); 500 } 501 sc->sc_bst = rman_get_bustag(sc->sc_res); 502 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 503 504 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 505 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 506 MV_MODE_ENDPOINT); 507 508 /* 509 * Get PCI interrupt info. 510 */ 511 if (sc->sc_mode == MV_MODE_ROOT) 512 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 513 514 /* 515 * Configure decode windows for PCI(E) access. 516 */ 517 if (mv_pcib_decode_win(node, sc) != 0) 518 return (ENXIO); 519 520 mv_pcib_hw_cfginit(); 521 522 /* 523 * Enable PCIE device. 524 */ 525 mv_pcib_enable(sc, port_id); 526 527 /* 528 * Memory management. 529 */ 530 err = mv_pcib_mem_init(sc); 531 if (err) 532 return (err); 533 534 /* 535 * Preliminary bus enumeration to find first linked devices and set 536 * appropriate bus number from which should start the actual enumeration 537 */ 538 for (bus = 0; bus < PCI_BUSMAX; bus++) { 539 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) { 540 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); 541 if (reg0 == (~0U)) 542 continue; /* no device */ 543 else { 544 sc->sc_busnr = bus; /* update bus number */ 545 break; 546 } 547 } 548 } 549 550 if (sc->sc_mode == MV_MODE_ROOT) { 551 err = mv_pcib_init(sc, sc->sc_busnr, 552 mv_pcib_maxslots(sc->sc_dev)); 553 if (err) 554 goto error; 555 556 device_add_child(self, "pci", -1); 557 } else { 558 sc->sc_devnr = 1; 559 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 560 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 561 device_add_child(self, "pci_ep", -1); 562 } 563 564 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 565 return (bus_generic_attach(self)); 566 567 error: 568 /* XXX SYS_RES_ should be released here */ 569 rman_fini(&sc->sc_mem_rman); 570 rman_fini(&sc->sc_io_rman); 571 572 return (err); 573 } 574 575 static void 576 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 577 { 578 uint32_t val; 579 int timeout; 580 581 if (sc->sc_skip_enable_procedure) 582 goto pcib_enable_root_mode; 583 584 /* 585 * Check if PCIE device is enabled. 586 */ 587 if ((sc->sc_skip_enable_procedure == 0) && 588 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) { 589 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 590 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 591 592 timeout = PCIE_LINK_TIMEOUT; 593 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 594 PCIE_REG_STATUS); 595 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 596 DELAY(1000); 597 timeout -= 1000; 598 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 599 PCIE_REG_STATUS); 600 } 601 } 602 603 pcib_enable_root_mode: 604 if (sc->sc_mode == MV_MODE_ROOT) { 605 /* 606 * Enable PCI bridge. 607 */ 608 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 609 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 610 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 611 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 612 } 613 } 614 615 static int 616 mv_pcib_mem_init(struct mv_pcib_softc *sc) 617 { 618 int err; 619 620 /* 621 * Memory management. 622 */ 623 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 624 err = rman_init(&sc->sc_mem_rman); 625 if (err) 626 return (err); 627 628 sc->sc_io_rman.rm_type = RMAN_ARRAY; 629 err = rman_init(&sc->sc_io_rman); 630 if (err) { 631 rman_fini(&sc->sc_mem_rman); 632 return (err); 633 } 634 635 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 636 sc->sc_mem_base + sc->sc_mem_size - 1); 637 if (err) 638 goto error; 639 640 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 641 sc->sc_io_base + sc->sc_io_size - 1); 642 if (err) 643 goto error; 644 645 return (0); 646 647 error: 648 rman_fini(&sc->sc_mem_rman); 649 rman_fini(&sc->sc_io_rman); 650 651 return (err); 652 } 653 654 static inline uint32_t 655 pcib_bit_get(uint32_t *map, uint32_t bit) 656 { 657 uint32_t n = bit / BITS_PER_UINT32; 658 659 bit = bit % BITS_PER_UINT32; 660 return (map[n] & (1 << bit)); 661 } 662 663 static inline void 664 pcib_bit_set(uint32_t *map, uint32_t bit) 665 { 666 uint32_t n = bit / BITS_PER_UINT32; 667 668 bit = bit % BITS_PER_UINT32; 669 map[n] |= (1 << bit); 670 } 671 672 static inline uint32_t 673 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 674 { 675 uint32_t i; 676 677 for (i = start; i < start + bits; i++) 678 if (pcib_bit_get(map, i)) 679 return (0); 680 681 return (1); 682 } 683 684 static inline void 685 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 686 { 687 uint32_t i; 688 689 for (i = start; i < start + bits; i++) 690 pcib_bit_set(map, i); 691 } 692 693 /* 694 * The idea of this allocator is taken from ARM No-Cache memory 695 * management code (sys/arm/arm/vm_machdep.c). 696 */ 697 static bus_addr_t 698 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 699 { 700 uint32_t bits, bits_limit, i, *map, min_alloc, size; 701 bus_addr_t addr = 0; 702 bus_addr_t base; 703 704 if (smask & 1) { 705 base = sc->sc_io_base; 706 min_alloc = PCI_MIN_IO_ALLOC; 707 bits_limit = sc->sc_io_size / min_alloc; 708 map = sc->sc_io_map; 709 smask &= ~0x3; 710 } else { 711 base = sc->sc_mem_base; 712 min_alloc = PCI_MIN_MEM_ALLOC; 713 bits_limit = sc->sc_mem_size / min_alloc; 714 map = sc->sc_mem_map; 715 smask &= ~0xF; 716 } 717 718 size = ~smask + 1; 719 bits = size / min_alloc; 720 721 for (i = 0; i + bits <= bits_limit; i += bits) 722 if (pcib_map_check(map, i, bits)) { 723 pcib_map_set(map, i, bits); 724 addr = base + (i * min_alloc); 725 return (addr); 726 } 727 728 return (addr); 729 } 730 731 static int 732 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 733 int barno) 734 { 735 uint32_t addr, bar; 736 int reg, width; 737 738 reg = PCIR_BAR(barno); 739 740 /* 741 * Need to init the BAR register with 0xffffffff before correct 742 * value can be read. 743 */ 744 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 745 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 746 if (bar == 0) 747 return (1); 748 749 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 750 width = ((bar & 7) == 4) ? 2 : 1; 751 752 addr = pcib_alloc(sc, bar); 753 if (!addr) 754 return (-1); 755 756 if (bootverbose) 757 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 758 bus, slot, func, reg, bar, addr); 759 760 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 761 if (width == 2) 762 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 763 0, 4); 764 765 return (width); 766 } 767 768 static void 769 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 770 { 771 bus_addr_t io_base, mem_base; 772 uint32_t io_limit, mem_limit; 773 int secbus; 774 775 io_base = sc->sc_io_base; 776 io_limit = io_base + sc->sc_io_size - 1; 777 mem_base = sc->sc_mem_base; 778 mem_limit = mem_base + sc->sc_mem_size - 1; 779 780 /* Configure I/O decode registers */ 781 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 782 io_base >> 8, 1); 783 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 784 io_base >> 16, 2); 785 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 786 io_limit >> 8, 1); 787 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 788 io_limit >> 16, 2); 789 790 /* Configure memory decode registers */ 791 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 792 mem_base >> 16, 2); 793 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 794 mem_limit >> 16, 2); 795 796 /* Disable memory prefetch decode */ 797 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 798 0x10, 2); 799 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 800 0x0, 4); 801 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 802 0xF, 2); 803 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 804 0x0, 4); 805 806 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 807 PCIR_SECBUS_1, 1); 808 809 /* Configure buses behind the bridge */ 810 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 811 } 812 813 static int 814 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 815 { 816 int slot, func, maxfunc, error; 817 uint8_t hdrtype, command, class, subclass; 818 819 for (slot = 0; slot <= maxslot; slot++) { 820 maxfunc = 0; 821 for (func = 0; func <= maxfunc; func++) { 822 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 823 func, PCIR_HDRTYPE, 1); 824 825 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 826 continue; 827 828 if (func == 0 && (hdrtype & PCIM_MFDEV)) 829 maxfunc = PCI_FUNCMAX; 830 831 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 832 func, PCIR_COMMAND, 1); 833 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 834 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 835 PCIR_COMMAND, command, 1); 836 837 error = mv_pcib_init_all_bars(sc, bus, slot, func, 838 hdrtype); 839 840 if (error) 841 return (error); 842 843 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 844 PCIM_CMD_PORTEN; 845 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 846 PCIR_COMMAND, command, 1); 847 848 /* Handle PCI-PCI bridges */ 849 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 850 func, PCIR_CLASS, 1); 851 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 852 func, PCIR_SUBCLASS, 1); 853 854 if (class != PCIC_BRIDGE || 855 subclass != PCIS_BRIDGE_PCI) 856 continue; 857 858 mv_pcib_init_bridge(sc, bus, slot, func); 859 } 860 } 861 862 /* Enable all ABCD interrupts */ 863 pcib_write_irq_mask(sc, (0xF << 24)); 864 865 return (0); 866 } 867 868 static int 869 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 870 int func, int hdrtype) 871 { 872 int maxbar, bar, i; 873 874 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 875 bar = 0; 876 877 /* Program the base address registers */ 878 while (bar < maxbar) { 879 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 880 bar += i; 881 if (i < 0) { 882 device_printf(sc->sc_dev, 883 "PCI IO/Memory space exhausted\n"); 884 return (ENOMEM); 885 } 886 } 887 888 return (0); 889 } 890 891 static struct rman * 892 mv_pcib_get_rman(device_t dev, int type, u_int flags) 893 { 894 struct mv_pcib_softc *sc = device_get_softc(dev); 895 896 switch (type) { 897 case SYS_RES_IOPORT: 898 return (&sc->sc_io_rman); 899 case SYS_RES_MEMORY: 900 return (&sc->sc_mem_rman); 901 default: 902 return (NULL); 903 } 904 } 905 906 static struct resource * 907 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 908 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 909 { 910 struct mv_pcib_softc *sc = device_get_softc(dev); 911 912 switch (type) { 913 case SYS_RES_IOPORT: 914 case SYS_RES_MEMORY: 915 break; 916 #ifdef PCI_RES_BUS 917 case PCI_RES_BUS: 918 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, 919 end, count, flags)); 920 #endif 921 default: 922 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 923 type, rid, start, end, count, flags)); 924 } 925 926 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 927 start = sc->sc_mem_base; 928 end = sc->sc_mem_base + sc->sc_mem_size - 1; 929 count = sc->sc_mem_size; 930 } 931 932 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 933 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 934 return (NULL); 935 936 return (bus_generic_rman_alloc_resource(dev, child, type, rid, 937 start, end, count, flags)); 938 } 939 940 static int 941 mv_pcib_adjust_resource(device_t dev, device_t child, 942 struct resource *r, rman_res_t start, rman_res_t end) 943 { 944 #ifdef PCI_RES_BUS 945 struct mv_pcib_softc *sc = device_get_softc(dev); 946 #endif 947 948 switch (rman_get_type(r)) { 949 case SYS_RES_IOPORT: 950 case SYS_RES_MEMORY: 951 return (bus_generic_rman_adjust_resource(dev, child, r, start, 952 end)); 953 #ifdef PCI_RES_BUS 954 case PCI_RES_BUS: 955 return (pci_domain_adjust_bus(sc->ap_segment, child, r, start, 956 end)); 957 #endif 958 default: 959 return (bus_generic_adjust_resource(dev, child, r, start, end)); 960 } 961 } 962 963 static int 964 mv_pcib_release_resource(device_t dev, device_t child, struct resource *res) 965 { 966 #ifdef PCI_RES_BUS 967 struct mv_pcib_softc *sc = device_get_softc(dev); 968 #endif 969 970 switch (rman_get_type(res)) { 971 case SYS_RES_IOPORT: 972 case SYS_RES_MEMORY: 973 return (bus_generic_rman_release_resource(dev, child, res)); 974 #ifdef PCI_RES_BUS 975 case PCI_RES_BUS: 976 return (pci_domain_release_bus(sc->ap_segment, child, res)); 977 #endif 978 default: 979 return (bus_generic_release_resource(dev, child, res)); 980 } 981 } 982 983 static int 984 mv_pcib_activate_resource(device_t dev, device_t child, struct resource *r) 985 { 986 #ifdef PCI_RES_BUS 987 struct mv_pcib_softc *sc = device_get_softc(dev); 988 #endif 989 990 switch (rman_get_type(r)) { 991 case SYS_RES_IOPORT: 992 case SYS_RES_MEMORY: 993 return (bus_generic_rman_activate_resource(dev, child, r)); 994 #ifdef PCI_RES_BUS 995 case PCI_RES_BUS: 996 return (pci_domain_activate_bus(sc->ap_segment, child, r)); 997 #endif 998 default: 999 return (bus_generic_activate_resource(dev, child, r)); 1000 } 1001 } 1002 1003 static int 1004 mv_pcib_deactivate_resource(device_t dev, device_t child, struct resource *r) 1005 { 1006 #ifdef PCI_RES_BUS 1007 struct mv_pcib_softc *sc = device_get_softc(dev); 1008 #endif 1009 1010 switch (rman_get_type(r)) { 1011 case SYS_RES_IOPORT: 1012 case SYS_RES_MEMORY: 1013 return (bus_generic_rman_deactivate_resource(dev, child, r)); 1014 #ifdef PCI_RES_BUS 1015 case PCI_RES_BUS: 1016 return (pci_domain_deactivate_bus(sc->ap_segment, child, r)); 1017 #endif 1018 default: 1019 return (bus_generic_deactivate_resource(dev, child, r)); 1020 } 1021 } 1022 1023 static int 1024 mv_pcib_map_resource(device_t dev, device_t child, struct resource *r, 1025 struct resource_map_request *argsp, struct resource_map *map) 1026 { 1027 struct resource_map_request args; 1028 rman_res_t length, start; 1029 int error; 1030 1031 /* Resources must be active to be mapped. */ 1032 if (!(rman_get_flags(r) & RF_ACTIVE)) 1033 return (ENXIO); 1034 1035 /* Mappings are only supported on I/O and memory resources. */ 1036 switch (rman_get_type(r)) { 1037 case SYS_RES_IOPORT: 1038 case SYS_RES_MEMORY: 1039 break; 1040 default: 1041 return (EINVAL); 1042 } 1043 1044 resource_init_map_request(&args); 1045 error = resource_validate_map_request(r, argsp, &args, &start, &length); 1046 if (error) 1047 return (error); 1048 1049 map->r_bustag = fdtbus_bs_tag; 1050 map->r_bushandle = start; 1051 map->r_size = length; 1052 return (0); 1053 } 1054 1055 static int 1056 mv_pcib_unmap_resource(device_t dev, device_t child, struct resource *r, 1057 struct resource_map *map) 1058 { 1059 switch (rman_get_type(r)) { 1060 case SYS_RES_IOPORT: 1061 case SYS_RES_MEMORY: 1062 return (0); 1063 default: 1064 return (EINVAL); 1065 } 1066 } 1067 1068 static int 1069 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1070 { 1071 struct mv_pcib_softc *sc = device_get_softc(dev); 1072 1073 switch (which) { 1074 case PCIB_IVAR_BUS: 1075 *result = sc->sc_busnr; 1076 return (0); 1077 case PCIB_IVAR_DOMAIN: 1078 *result = device_get_unit(dev); 1079 return (0); 1080 } 1081 1082 return (ENOENT); 1083 } 1084 1085 static int 1086 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 1087 { 1088 struct mv_pcib_softc *sc = device_get_softc(dev); 1089 1090 switch (which) { 1091 case PCIB_IVAR_BUS: 1092 sc->sc_busnr = value; 1093 return (0); 1094 } 1095 1096 return (ENOENT); 1097 } 1098 1099 static inline void 1100 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 1101 { 1102 1103 if (sc->sc_type != MV_TYPE_PCIE) 1104 return; 1105 1106 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 1107 } 1108 1109 static void 1110 mv_pcib_hw_cfginit(void) 1111 { 1112 static int opened = 0; 1113 1114 if (opened) 1115 return; 1116 1117 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 1118 opened = 1; 1119 } 1120 1121 static uint32_t 1122 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1123 u_int func, u_int reg, int bytes) 1124 { 1125 uint32_t addr, data, ca, cd; 1126 1127 ca = (sc->sc_type != MV_TYPE_PCI) ? 1128 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1129 cd = (sc->sc_type != MV_TYPE_PCI) ? 1130 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1131 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1132 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1133 1134 mtx_lock_spin(&pcicfg_mtx); 1135 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1136 1137 data = ~0; 1138 switch (bytes) { 1139 case 1: 1140 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1141 cd + (reg & 3)); 1142 break; 1143 case 2: 1144 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 1145 cd + (reg & 2))); 1146 break; 1147 case 4: 1148 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 1149 cd)); 1150 break; 1151 } 1152 mtx_unlock_spin(&pcicfg_mtx); 1153 return (data); 1154 } 1155 1156 static void 1157 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1158 u_int func, u_int reg, uint32_t data, int bytes) 1159 { 1160 uint32_t addr, ca, cd; 1161 1162 ca = (sc->sc_type != MV_TYPE_PCI) ? 1163 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1164 cd = (sc->sc_type != MV_TYPE_PCI) ? 1165 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1166 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1167 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1168 1169 mtx_lock_spin(&pcicfg_mtx); 1170 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1171 1172 switch (bytes) { 1173 case 1: 1174 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1175 cd + (reg & 3), data); 1176 break; 1177 case 2: 1178 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1179 cd + (reg & 2), htole16(data)); 1180 break; 1181 case 4: 1182 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1183 cd, htole32(data)); 1184 break; 1185 } 1186 mtx_unlock_spin(&pcicfg_mtx); 1187 } 1188 1189 static int 1190 mv_pcib_maxslots(device_t dev) 1191 { 1192 struct mv_pcib_softc *sc = device_get_softc(dev); 1193 1194 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1195 } 1196 1197 static int 1198 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1199 { 1200 struct mv_pcib_softc *sc = device_get_softc(dev); 1201 uint32_t vendor, device; 1202 1203 /* On platforms other than Armada38x, root link is always at slot 0 */ 1204 if (!sc->sc_enable_find_root_slot) 1205 return (slot == 0); 1206 1207 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1208 PCIR_VENDOR_LENGTH); 1209 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1210 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1211 1212 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1213 } 1214 1215 static uint32_t 1216 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1217 u_int reg, int bytes) 1218 { 1219 struct mv_pcib_softc *sc = device_get_softc(dev); 1220 1221 /* Return ~0 if link is inactive or trying to read from Root */ 1222 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1223 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1224 return (~0U); 1225 1226 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1227 } 1228 1229 static void 1230 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1231 u_int reg, uint32_t val, int bytes) 1232 { 1233 struct mv_pcib_softc *sc = device_get_softc(dev); 1234 1235 /* Return if link is inactive or trying to write to Root */ 1236 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1237 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1238 return; 1239 1240 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1241 } 1242 1243 static int 1244 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1245 { 1246 struct mv_pcib_softc *sc; 1247 struct ofw_pci_register reg; 1248 uint32_t pintr, mintr[4]; 1249 int icells; 1250 phandle_t iparent; 1251 1252 sc = device_get_softc(bus); 1253 pintr = pin; 1254 1255 /* Fabricate imap information in case this isn't an OFW device */ 1256 bzero(®, sizeof(reg)); 1257 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1258 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1259 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1260 1261 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1262 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1263 &iparent); 1264 if (icells > 0) 1265 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1266 1267 /* Maybe it's a real interrupt, not an intpin */ 1268 if (pin > 4) 1269 return (pin); 1270 1271 device_printf(bus, "could not route pin %d for device %d.%d\n", 1272 pin, pci_get_slot(dev), pci_get_function(dev)); 1273 return (PCI_INVALID_IRQ); 1274 } 1275 1276 static int 1277 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1278 { 1279 struct mv_pci_range io_space, mem_space; 1280 device_t dev; 1281 int error; 1282 1283 dev = sc->sc_dev; 1284 1285 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1286 device_printf(dev, "could not retrieve 'ranges' data\n"); 1287 return (error); 1288 } 1289 1290 /* Configure CPU decoding windows */ 1291 error = decode_win_cpu_set(sc->sc_win_target, 1292 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1293 if (error < 0) { 1294 device_printf(dev, "could not set up CPU decode " 1295 "window for PCI IO\n"); 1296 return (ENXIO); 1297 } 1298 error = decode_win_cpu_set(sc->sc_win_target, 1299 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1300 mem_space.base_parent); 1301 if (error < 0) { 1302 device_printf(dev, "could not set up CPU decode " 1303 "windows for PCI MEM\n"); 1304 return (ENXIO); 1305 } 1306 1307 sc->sc_io_base = io_space.base_parent; 1308 sc->sc_io_size = io_space.len; 1309 1310 sc->sc_mem_base = mem_space.base_parent; 1311 sc->sc_mem_size = mem_space.len; 1312 1313 return (0); 1314 } 1315 1316 static int 1317 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1318 uint32_t *data) 1319 { 1320 struct mv_pcib_softc *sc; 1321 1322 sc = device_get_softc(dev); 1323 if (!sc->sc_msi_supported) 1324 return (ENOTSUP); 1325 1326 irq = irq - MSI_IRQ; 1327 1328 /* validate parameters */ 1329 if (isclr(&sc->sc_msi_bitmap, irq)) { 1330 device_printf(dev, "invalid MSI 0x%x\n", irq); 1331 return (EINVAL); 1332 } 1333 1334 mv_msi_data(irq, addr, data); 1335 1336 debugf("%s: irq: %d addr: %jx data: %x\n", 1337 __func__, irq, *addr, *data); 1338 1339 return (0); 1340 } 1341 1342 static int 1343 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1344 int maxcount __unused, int *irqs) 1345 { 1346 struct mv_pcib_softc *sc; 1347 u_int start = 0, i; 1348 1349 sc = device_get_softc(dev); 1350 if (!sc->sc_msi_supported) 1351 return (ENOTSUP); 1352 1353 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1354 return (EINVAL); 1355 1356 mtx_lock(&sc->sc_msi_mtx); 1357 1358 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1359 for (i = start; i < start + count; i++) { 1360 if (isset(&sc->sc_msi_bitmap, i)) 1361 break; 1362 } 1363 if (i == start + count) 1364 break; 1365 } 1366 1367 if ((start + count) == MSI_IRQ_NUM) { 1368 mtx_unlock(&sc->sc_msi_mtx); 1369 return (ENXIO); 1370 } 1371 1372 for (i = start; i < start + count; i++) { 1373 setbit(&sc->sc_msi_bitmap, i); 1374 *irqs++ = MSI_IRQ + i; 1375 } 1376 debugf("%s: start: %x count: %x\n", __func__, start, count); 1377 1378 mtx_unlock(&sc->sc_msi_mtx); 1379 return (0); 1380 } 1381 1382 static int 1383 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1384 { 1385 struct mv_pcib_softc *sc; 1386 u_int i; 1387 1388 sc = device_get_softc(dev); 1389 if(!sc->sc_msi_supported) 1390 return (ENOTSUP); 1391 1392 mtx_lock(&sc->sc_msi_mtx); 1393 1394 for (i = 0; i < count; i++) 1395 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1396 1397 mtx_unlock(&sc->sc_msi_mtx); 1398 return (0); 1399 } 1400