1 /*- 2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3 * Copyright (c) 2010 The FreeBSD Foundation 4 * Copyright (c) 2010-2012 Semihalf 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of MARVELL nor the names of contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 /* 38 * Marvell integrated PCI/PCI-Express controller driver. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/queue.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/endian.h> 55 56 #include <machine/fdt.h> 57 #include <machine/intr.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_pci.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 #include <machine/devmap.h> 74 #include <machine/resource.h> 75 #include <machine/bus.h> 76 77 #include <arm/mv/mvreg.h> 78 #include <arm/mv/mvvar.h> 79 #include <arm/mv/mvwin.h> 80 81 #ifdef DEBUG 82 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83 #else 84 #define debugf(fmt, args...) 85 #endif 86 87 /* 88 * Code and data related to fdt-based PCI configuration. 89 * 90 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91 * always Marvell-specific so that was deleted and the code now lives here. 92 */ 93 94 struct mv_pci_range { 95 u_long base_pci; 96 u_long base_parent; 97 u_long len; 98 }; 99 100 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101 102 static void 103 mv_pci_range_dump(struct mv_pci_range *range) 104 { 105 #ifdef DEBUG 106 printf("\n"); 107 printf(" base_pci = 0x%08lx\n", range->base_pci); 108 printf(" base_par = 0x%08lx\n", range->base_parent); 109 printf(" len = 0x%08lx\n", range->len); 110 #endif 111 } 112 113 static int 114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115 struct mv_pci_range *mem_space) 116 { 117 pcell_t ranges[FDT_RANGES_CELLS]; 118 struct mv_pci_range *pci_space; 119 pcell_t addr_cells, size_cells, par_addr_cells; 120 pcell_t *rangesptr; 121 pcell_t cell0, cell1, cell2; 122 int tuple_size, tuples, i, rv, offset_cells, len; 123 124 /* 125 * Retrieve 'ranges' property. 126 */ 127 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 128 return (EINVAL); 129 if (addr_cells != 3 || size_cells != 2) 130 return (ERANGE); 131 132 par_addr_cells = fdt_parent_addr_cells(node); 133 if (par_addr_cells > 3) 134 return (ERANGE); 135 136 len = OF_getproplen(node, "ranges"); 137 if (len > sizeof(ranges)) 138 return (ENOMEM); 139 140 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 141 return (EINVAL); 142 143 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 144 size_cells); 145 tuples = len / tuple_size; 146 147 /* 148 * Initialize the ranges so that we don't have to worry about 149 * having them all defined in the FDT. In particular, it is 150 * perfectly fine not to want I/O space on PCI busses. 151 */ 152 bzero(io_space, sizeof(*io_space)); 153 bzero(mem_space, sizeof(*mem_space)); 154 155 rangesptr = &ranges[0]; 156 offset_cells = 0; 157 for (i = 0; i < tuples; i++) { 158 cell0 = fdt_data_get((void *)rangesptr, 1); 159 rangesptr++; 160 cell1 = fdt_data_get((void *)rangesptr, 1); 161 rangesptr++; 162 cell2 = fdt_data_get((void *)rangesptr, 1); 163 rangesptr++; 164 165 if (cell0 & 0x02000000) { 166 pci_space = mem_space; 167 } else if (cell0 & 0x01000000) { 168 pci_space = io_space; 169 } else { 170 rv = ERANGE; 171 goto out; 172 } 173 174 if (par_addr_cells == 3) { 175 /* 176 * This is a PCI subnode 'ranges'. Skip cell0 and 177 * cell1 of this entry and only use cell2. 178 */ 179 offset_cells = 2; 180 rangesptr += offset_cells; 181 } 182 183 if (fdt_data_verify((void *)rangesptr, par_addr_cells - 184 offset_cells)) { 185 rv = ERANGE; 186 goto out; 187 } 188 pci_space->base_parent = fdt_data_get((void *)rangesptr, 189 par_addr_cells - offset_cells); 190 rangesptr += par_addr_cells - offset_cells; 191 192 if (fdt_data_verify((void *)rangesptr, size_cells)) { 193 rv = ERANGE; 194 goto out; 195 } 196 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 197 rangesptr += size_cells; 198 199 pci_space->base_pci = cell2; 200 } 201 rv = 0; 202 out: 203 return (rv); 204 } 205 206 static int 207 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 208 struct mv_pci_range *mem_space) 209 { 210 int err; 211 212 debugf("Processing PCI node: %x\n", node); 213 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 214 debugf("could not decode parent PCI node 'ranges'\n"); 215 return (err); 216 } 217 218 debugf("Post fixup dump:\n"); 219 mv_pci_range_dump(io_space); 220 mv_pci_range_dump(mem_space); 221 return (0); 222 } 223 224 int 225 mv_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, vm_offset_t io_va, 226 vm_offset_t mem_va) 227 { 228 struct mv_pci_range io_space, mem_space; 229 int error; 230 231 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 232 return (error); 233 234 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 235 devmap->pd_pa = io_space.base_parent; 236 devmap->pd_size = io_space.len; 237 devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 238 devmap->pd_cache = PTE_NOCACHE; 239 devmap++; 240 241 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 242 devmap->pd_pa = mem_space.base_parent; 243 devmap->pd_size = mem_space.len; 244 devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 245 devmap->pd_cache = PTE_NOCACHE; 246 return (0); 247 } 248 249 /* 250 * Code and data related to the Marvell pcib driver. 251 */ 252 253 #define PCI_CFG_ENA (1U << 31) 254 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 255 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 256 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 257 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 258 259 #define PCI_REG_CFG_ADDR 0x0C78 260 #define PCI_REG_CFG_DATA 0x0C7C 261 262 #define PCIE_REG_CFG_ADDR 0x18F8 263 #define PCIE_REG_CFG_DATA 0x18FC 264 #define PCIE_REG_CONTROL 0x1A00 265 #define PCIE_CTRL_LINK1X 0x00000001 266 #define PCIE_REG_STATUS 0x1A04 267 #define PCIE_REG_IRQ_MASK 0x1910 268 269 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 270 #define PCIE_CONTROL_HOT_RESET (1 << 24) 271 272 #define PCIE_LINK_TIMEOUT 1000000 273 274 #define PCIE_STATUS_LINK_DOWN 1 275 #define PCIE_STATUS_DEV_OFFS 16 276 277 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 278 #define PCI_MIN_IO_ALLOC 4 279 #define PCI_MIN_MEM_ALLOC 16 280 281 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 282 283 struct mv_pcib_softc { 284 device_t sc_dev; 285 286 struct rman sc_mem_rman; 287 bus_addr_t sc_mem_base; 288 bus_addr_t sc_mem_size; 289 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 290 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 291 int sc_win_target; 292 int sc_mem_win_attr; 293 294 struct rman sc_io_rman; 295 bus_addr_t sc_io_base; 296 bus_addr_t sc_io_size; 297 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 298 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 299 int sc_io_win_attr; 300 301 struct resource *sc_res; 302 bus_space_handle_t sc_bsh; 303 bus_space_tag_t sc_bst; 304 int sc_rid; 305 306 struct mtx sc_msi_mtx; 307 uint32_t sc_msi_bitmap; 308 309 int sc_busnr; /* Host bridge bus number */ 310 int sc_devnr; /* Host bridge device number */ 311 int sc_type; 312 int sc_mode; /* Endpoint / Root Complex */ 313 314 struct ofw_bus_iinfo sc_pci_iinfo; 315 }; 316 317 /* Local forward prototypes */ 318 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 319 static void mv_pcib_hw_cfginit(void); 320 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 321 u_int, u_int, int); 322 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 323 u_int, u_int, uint32_t, int); 324 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 325 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 326 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 327 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 328 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 329 static int mv_pcib_mem_init(struct mv_pcib_softc *); 330 331 /* Forward prototypes */ 332 static int mv_pcib_probe(device_t); 333 static int mv_pcib_attach(device_t); 334 335 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 336 u_long, u_long, u_long, u_int); 337 static int mv_pcib_release_resource(device_t, device_t, int, int, 338 struct resource *); 339 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 340 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 341 342 static int mv_pcib_maxslots(device_t); 343 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 344 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 345 uint32_t, int); 346 static int mv_pcib_route_interrupt(device_t, device_t, int); 347 #if defined(SOC_MV_ARMADAXP) 348 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 349 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 350 static int mv_pcib_release_msi(device_t, device_t, int, int *); 351 #endif 352 353 /* 354 * Bus interface definitions. 355 */ 356 static device_method_t mv_pcib_methods[] = { 357 /* Device interface */ 358 DEVMETHOD(device_probe, mv_pcib_probe), 359 DEVMETHOD(device_attach, mv_pcib_attach), 360 361 /* Bus interface */ 362 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 363 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 364 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 365 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 366 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 367 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 368 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 369 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 370 371 /* pcib interface */ 372 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 373 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 374 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 375 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 376 377 #if defined(SOC_MV_ARMADAXP) 378 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 379 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 380 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 381 #endif 382 383 /* OFW bus interface */ 384 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 385 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 386 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 387 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 388 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 389 390 DEVMETHOD_END 391 }; 392 393 static driver_t mv_pcib_driver = { 394 "pcib", 395 mv_pcib_methods, 396 sizeof(struct mv_pcib_softc), 397 }; 398 399 devclass_t pcib_devclass; 400 401 DRIVER_MODULE(pcib, nexus, mv_pcib_driver, pcib_devclass, 0, 0); 402 403 static struct mtx pcicfg_mtx; 404 405 static int 406 mv_pcib_probe(device_t self) 407 { 408 phandle_t node; 409 410 node = ofw_bus_get_node(self); 411 if (!fdt_is_type(node, "pci")) 412 return (ENXIO); 413 414 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 415 ofw_bus_is_compatible(self, "mrvl,pci"))) 416 return (ENXIO); 417 418 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 419 return (BUS_PROBE_DEFAULT); 420 } 421 422 static int 423 mv_pcib_attach(device_t self) 424 { 425 struct mv_pcib_softc *sc; 426 phandle_t node, parnode; 427 uint32_t val, unit; 428 int err; 429 430 sc = device_get_softc(self); 431 sc->sc_dev = self; 432 unit = fdt_get_unit(self); 433 434 435 node = ofw_bus_get_node(self); 436 parnode = OF_parent(node); 437 if (fdt_is_compatible(node, "mrvl,pcie")) { 438 sc->sc_type = MV_TYPE_PCIE; 439 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 440 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 441 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 442 } else if (fdt_is_compatible(node, "mrvl,pci")) { 443 sc->sc_type = MV_TYPE_PCI; 444 sc->sc_win_target = MV_WIN_PCI_TARGET; 445 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 446 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 447 } else 448 return (ENXIO); 449 450 /* 451 * Retrieve our mem-mapped registers range. 452 */ 453 sc->sc_rid = 0; 454 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 455 RF_ACTIVE); 456 if (sc->sc_res == NULL) { 457 device_printf(self, "could not map memory\n"); 458 return (ENXIO); 459 } 460 sc->sc_bst = rman_get_bustag(sc->sc_res); 461 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 462 463 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 464 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 465 MV_MODE_ENDPOINT); 466 467 /* 468 * Get PCI interrupt info. 469 */ 470 if (sc->sc_mode == MV_MODE_ROOT) 471 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 472 473 /* 474 * Configure decode windows for PCI(E) access. 475 */ 476 if (mv_pcib_decode_win(node, sc) != 0) 477 return (ENXIO); 478 479 mv_pcib_hw_cfginit(); 480 481 /* 482 * Enable PCIE device. 483 */ 484 mv_pcib_enable(sc, unit); 485 486 /* 487 * Memory management. 488 */ 489 err = mv_pcib_mem_init(sc); 490 if (err) 491 return (err); 492 493 if (sc->sc_mode == MV_MODE_ROOT) { 494 err = mv_pcib_init(sc, sc->sc_busnr, 495 mv_pcib_maxslots(sc->sc_dev)); 496 if (err) 497 goto error; 498 499 device_add_child(self, "pci", -1); 500 } else { 501 sc->sc_devnr = 1; 502 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 503 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 504 device_add_child(self, "pci_ep", -1); 505 } 506 507 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 508 return (bus_generic_attach(self)); 509 510 error: 511 /* XXX SYS_RES_ should be released here */ 512 rman_fini(&sc->sc_mem_rman); 513 rman_fini(&sc->sc_io_rman); 514 515 return (err); 516 } 517 518 static void 519 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 520 { 521 uint32_t val; 522 #if !defined(SOC_MV_ARMADAXP) 523 int timeout; 524 525 /* 526 * Check if PCIE device is enabled. 527 */ 528 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 529 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 530 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 531 532 timeout = PCIE_LINK_TIMEOUT; 533 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 534 PCIE_REG_STATUS); 535 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 536 DELAY(1000); 537 timeout -= 1000; 538 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 539 PCIE_REG_STATUS); 540 } 541 } 542 #endif 543 544 545 if (sc->sc_mode == MV_MODE_ROOT) { 546 /* 547 * Enable PCI bridge. 548 */ 549 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 550 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 551 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 552 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 553 } 554 } 555 556 static int 557 mv_pcib_mem_init(struct mv_pcib_softc *sc) 558 { 559 int err; 560 561 /* 562 * Memory management. 563 */ 564 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 565 err = rman_init(&sc->sc_mem_rman); 566 if (err) 567 return (err); 568 569 sc->sc_io_rman.rm_type = RMAN_ARRAY; 570 err = rman_init(&sc->sc_io_rman); 571 if (err) { 572 rman_fini(&sc->sc_mem_rman); 573 return (err); 574 } 575 576 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 577 sc->sc_mem_base + sc->sc_mem_size - 1); 578 if (err) 579 goto error; 580 581 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 582 sc->sc_io_base + sc->sc_io_size - 1); 583 if (err) 584 goto error; 585 586 return (0); 587 588 error: 589 rman_fini(&sc->sc_mem_rman); 590 rman_fini(&sc->sc_io_rman); 591 592 return (err); 593 } 594 595 static inline uint32_t 596 pcib_bit_get(uint32_t *map, uint32_t bit) 597 { 598 uint32_t n = bit / BITS_PER_UINT32; 599 600 bit = bit % BITS_PER_UINT32; 601 return (map[n] & (1 << bit)); 602 } 603 604 static inline void 605 pcib_bit_set(uint32_t *map, uint32_t bit) 606 { 607 uint32_t n = bit / BITS_PER_UINT32; 608 609 bit = bit % BITS_PER_UINT32; 610 map[n] |= (1 << bit); 611 } 612 613 static inline uint32_t 614 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 615 { 616 uint32_t i; 617 618 for (i = start; i < start + bits; i++) 619 if (pcib_bit_get(map, i)) 620 return (0); 621 622 return (1); 623 } 624 625 static inline void 626 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 627 { 628 uint32_t i; 629 630 for (i = start; i < start + bits; i++) 631 pcib_bit_set(map, i); 632 } 633 634 /* 635 * The idea of this allocator is taken from ARM No-Cache memory 636 * management code (sys/arm/arm/vm_machdep.c). 637 */ 638 static bus_addr_t 639 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 640 { 641 uint32_t bits, bits_limit, i, *map, min_alloc, size; 642 bus_addr_t addr = 0; 643 bus_addr_t base; 644 645 if (smask & 1) { 646 base = sc->sc_io_base; 647 min_alloc = PCI_MIN_IO_ALLOC; 648 bits_limit = sc->sc_io_size / min_alloc; 649 map = sc->sc_io_map; 650 smask &= ~0x3; 651 } else { 652 base = sc->sc_mem_base; 653 min_alloc = PCI_MIN_MEM_ALLOC; 654 bits_limit = sc->sc_mem_size / min_alloc; 655 map = sc->sc_mem_map; 656 smask &= ~0xF; 657 } 658 659 size = ~smask + 1; 660 bits = size / min_alloc; 661 662 for (i = 0; i + bits <= bits_limit; i += bits) 663 if (pcib_map_check(map, i, bits)) { 664 pcib_map_set(map, i, bits); 665 addr = base + (i * min_alloc); 666 return (addr); 667 } 668 669 return (addr); 670 } 671 672 static int 673 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 674 int barno) 675 { 676 uint32_t addr, bar; 677 int reg, width; 678 679 reg = PCIR_BAR(barno); 680 681 /* 682 * Need to init the BAR register with 0xffffffff before correct 683 * value can be read. 684 */ 685 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 686 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 687 if (bar == 0) 688 return (1); 689 690 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 691 width = ((bar & 7) == 4) ? 2 : 1; 692 693 addr = pcib_alloc(sc, bar); 694 if (!addr) 695 return (-1); 696 697 if (bootverbose) 698 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 699 bus, slot, func, reg, bar, addr); 700 701 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 702 if (width == 2) 703 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 704 0, 4); 705 706 return (width); 707 } 708 709 static void 710 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 711 { 712 bus_addr_t io_base, mem_base; 713 uint32_t io_limit, mem_limit; 714 int secbus; 715 716 io_base = sc->sc_io_base; 717 io_limit = io_base + sc->sc_io_size - 1; 718 mem_base = sc->sc_mem_base; 719 mem_limit = mem_base + sc->sc_mem_size - 1; 720 721 /* Configure I/O decode registers */ 722 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 723 io_base >> 8, 1); 724 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 725 io_base >> 16, 2); 726 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 727 io_limit >> 8, 1); 728 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 729 io_limit >> 16, 2); 730 731 /* Configure memory decode registers */ 732 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 733 mem_base >> 16, 2); 734 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 735 mem_limit >> 16, 2); 736 737 /* Disable memory prefetch decode */ 738 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 739 0x10, 2); 740 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 741 0x0, 4); 742 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 743 0xF, 2); 744 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 745 0x0, 4); 746 747 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 748 PCIR_SECBUS_1, 1); 749 750 /* Configure buses behind the bridge */ 751 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 752 } 753 754 static int 755 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 756 { 757 int slot, func, maxfunc, error; 758 uint8_t hdrtype, command, class, subclass; 759 760 for (slot = 0; slot <= maxslot; slot++) { 761 maxfunc = 0; 762 for (func = 0; func <= maxfunc; func++) { 763 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 764 func, PCIR_HDRTYPE, 1); 765 766 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 767 continue; 768 769 if (func == 0 && (hdrtype & PCIM_MFDEV)) 770 maxfunc = PCI_FUNCMAX; 771 772 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 773 func, PCIR_COMMAND, 1); 774 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 775 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 776 PCIR_COMMAND, command, 1); 777 778 error = mv_pcib_init_all_bars(sc, bus, slot, func, 779 hdrtype); 780 781 if (error) 782 return (error); 783 784 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 785 PCIM_CMD_PORTEN; 786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 787 PCIR_COMMAND, command, 1); 788 789 /* Handle PCI-PCI bridges */ 790 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 791 func, PCIR_CLASS, 1); 792 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 793 func, PCIR_SUBCLASS, 1); 794 795 if (class != PCIC_BRIDGE || 796 subclass != PCIS_BRIDGE_PCI) 797 continue; 798 799 mv_pcib_init_bridge(sc, bus, slot, func); 800 } 801 } 802 803 /* Enable all ABCD interrupts */ 804 pcib_write_irq_mask(sc, (0xF << 24)); 805 806 return (0); 807 } 808 809 static int 810 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 811 int func, int hdrtype) 812 { 813 int maxbar, bar, i; 814 815 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 816 bar = 0; 817 818 /* Program the base address registers */ 819 while (bar < maxbar) { 820 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 821 bar += i; 822 if (i < 0) { 823 device_printf(sc->sc_dev, 824 "PCI IO/Memory space exhausted\n"); 825 return (ENOMEM); 826 } 827 } 828 829 return (0); 830 } 831 832 static struct resource * 833 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 834 u_long start, u_long end, u_long count, u_int flags) 835 { 836 struct mv_pcib_softc *sc = device_get_softc(dev); 837 struct rman *rm = NULL; 838 struct resource *res; 839 840 switch (type) { 841 case SYS_RES_IOPORT: 842 rm = &sc->sc_io_rman; 843 break; 844 case SYS_RES_MEMORY: 845 rm = &sc->sc_mem_rman; 846 break; 847 default: 848 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 849 type, rid, start, end, count, flags)); 850 }; 851 852 if ((start == 0UL) && (end == ~0UL)) { 853 start = sc->sc_mem_base; 854 end = sc->sc_mem_base + sc->sc_mem_size - 1; 855 count = sc->sc_mem_size; 856 } 857 858 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 859 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 860 return (NULL); 861 862 res = rman_reserve_resource(rm, start, end, count, flags, child); 863 if (res == NULL) 864 return (NULL); 865 866 rman_set_rid(res, *rid); 867 rman_set_bustag(res, fdtbus_bs_tag); 868 rman_set_bushandle(res, start); 869 870 if (flags & RF_ACTIVE) 871 if (bus_activate_resource(child, type, *rid, res)) { 872 rman_release_resource(res); 873 return (NULL); 874 } 875 876 return (res); 877 } 878 879 static int 880 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 881 struct resource *res) 882 { 883 884 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 885 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 886 type, rid, res)); 887 888 return (rman_release_resource(res)); 889 } 890 891 static int 892 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 893 { 894 struct mv_pcib_softc *sc = device_get_softc(dev); 895 896 switch (which) { 897 case PCIB_IVAR_BUS: 898 *result = sc->sc_busnr; 899 return (0); 900 case PCIB_IVAR_DOMAIN: 901 *result = device_get_unit(dev); 902 return (0); 903 } 904 905 return (ENOENT); 906 } 907 908 static int 909 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 910 { 911 struct mv_pcib_softc *sc = device_get_softc(dev); 912 913 switch (which) { 914 case PCIB_IVAR_BUS: 915 sc->sc_busnr = value; 916 return (0); 917 } 918 919 return (ENOENT); 920 } 921 922 static inline void 923 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 924 { 925 926 if (!sc->sc_type != MV_TYPE_PCI) 927 return; 928 929 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 930 } 931 932 static void 933 mv_pcib_hw_cfginit(void) 934 { 935 static int opened = 0; 936 937 if (opened) 938 return; 939 940 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 941 opened = 1; 942 } 943 944 static uint32_t 945 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 946 u_int func, u_int reg, int bytes) 947 { 948 uint32_t addr, data, ca, cd; 949 950 ca = (sc->sc_type != MV_TYPE_PCI) ? 951 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 952 cd = (sc->sc_type != MV_TYPE_PCI) ? 953 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 954 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 955 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 956 957 mtx_lock_spin(&pcicfg_mtx); 958 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 959 960 data = ~0; 961 switch (bytes) { 962 case 1: 963 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 964 cd + (reg & 3)); 965 break; 966 case 2: 967 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 968 cd + (reg & 2))); 969 break; 970 case 4: 971 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 972 cd)); 973 break; 974 } 975 mtx_unlock_spin(&pcicfg_mtx); 976 return (data); 977 } 978 979 static void 980 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 981 u_int func, u_int reg, uint32_t data, int bytes) 982 { 983 uint32_t addr, ca, cd; 984 985 ca = (sc->sc_type != MV_TYPE_PCI) ? 986 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 987 cd = (sc->sc_type != MV_TYPE_PCI) ? 988 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 989 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 990 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 991 992 mtx_lock_spin(&pcicfg_mtx); 993 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 994 995 switch (bytes) { 996 case 1: 997 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 998 cd + (reg & 3), data); 999 break; 1000 case 2: 1001 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1002 cd + (reg & 2), htole16(data)); 1003 break; 1004 case 4: 1005 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1006 cd, htole32(data)); 1007 break; 1008 } 1009 mtx_unlock_spin(&pcicfg_mtx); 1010 } 1011 1012 static int 1013 mv_pcib_maxslots(device_t dev) 1014 { 1015 struct mv_pcib_softc *sc = device_get_softc(dev); 1016 1017 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1018 } 1019 1020 static uint32_t 1021 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1022 u_int reg, int bytes) 1023 { 1024 struct mv_pcib_softc *sc = device_get_softc(dev); 1025 1026 /* Return ~0 if link is inactive or trying to read from Root */ 1027 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1028 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 1029 return (~0U); 1030 1031 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1032 } 1033 1034 static void 1035 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1036 u_int reg, uint32_t val, int bytes) 1037 { 1038 struct mv_pcib_softc *sc = device_get_softc(dev); 1039 1040 /* Return if link is inactive or trying to write to Root */ 1041 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1042 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 1043 return; 1044 1045 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1046 } 1047 1048 static int 1049 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1050 { 1051 struct mv_pcib_softc *sc; 1052 struct ofw_pci_register reg; 1053 uint32_t pintr, mintr; 1054 phandle_t iparent; 1055 1056 sc = device_get_softc(bus); 1057 pintr = pin; 1058 1059 /* Fabricate imap information in case this isn't an OFW device */ 1060 bzero(®, sizeof(reg)); 1061 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1062 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1063 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1064 1065 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1066 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 1067 &iparent)) 1068 return (ofw_bus_map_intr(dev, iparent, mintr)); 1069 1070 /* Maybe it's a real interrupt, not an intpin */ 1071 if (pin > 4) 1072 return (pin); 1073 1074 device_printf(bus, "could not route pin %d for device %d.%d\n", 1075 pin, pci_get_slot(dev), pci_get_function(dev)); 1076 return (PCI_INVALID_IRQ); 1077 } 1078 1079 static int 1080 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1081 { 1082 struct mv_pci_range io_space, mem_space; 1083 device_t dev; 1084 int error; 1085 1086 dev = sc->sc_dev; 1087 1088 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1089 device_printf(dev, "could not retrieve 'ranges' data\n"); 1090 return (error); 1091 } 1092 1093 /* Configure CPU decoding windows */ 1094 error = decode_win_cpu_set(sc->sc_win_target, 1095 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1096 if (error < 0) { 1097 device_printf(dev, "could not set up CPU decode " 1098 "window for PCI IO\n"); 1099 return (ENXIO); 1100 } 1101 error = decode_win_cpu_set(sc->sc_win_target, 1102 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1103 mem_space.base_parent); 1104 if (error < 0) { 1105 device_printf(dev, "could not set up CPU decode " 1106 "windows for PCI MEM\n"); 1107 return (ENXIO); 1108 } 1109 1110 sc->sc_io_base = io_space.base_parent; 1111 sc->sc_io_size = io_space.len; 1112 1113 sc->sc_mem_base = mem_space.base_parent; 1114 sc->sc_mem_size = mem_space.len; 1115 1116 return (0); 1117 } 1118 1119 #if defined(SOC_MV_ARMADAXP) 1120 static int 1121 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1122 uint32_t *data) 1123 { 1124 struct mv_pcib_softc *sc; 1125 1126 sc = device_get_softc(dev); 1127 irq = irq - MSI_IRQ; 1128 1129 /* validate parameters */ 1130 if (isclr(&sc->sc_msi_bitmap, irq)) { 1131 device_printf(dev, "invalid MSI 0x%x\n", irq); 1132 return (EINVAL); 1133 } 1134 1135 mv_msi_data(irq, addr, data); 1136 1137 debugf("%s: irq: %d addr: %jx data: %x\n", 1138 __func__, irq, *addr, *data); 1139 1140 return (0); 1141 } 1142 1143 static int 1144 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1145 int maxcount __unused, int *irqs) 1146 { 1147 struct mv_pcib_softc *sc; 1148 u_int start = 0, i; 1149 1150 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1151 return (EINVAL); 1152 1153 sc = device_get_softc(dev); 1154 mtx_lock(&sc->sc_msi_mtx); 1155 1156 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1157 for (i = start; i < start + count; i++) { 1158 if (isset(&sc->sc_msi_bitmap, i)) 1159 break; 1160 } 1161 if (i == start + count) 1162 break; 1163 } 1164 1165 if ((start + count) == MSI_IRQ_NUM) { 1166 mtx_unlock(&sc->sc_msi_mtx); 1167 return (ENXIO); 1168 } 1169 1170 for (i = start; i < start + count; i++) { 1171 setbit(&sc->sc_msi_bitmap, i); 1172 irqs[i] = MSI_IRQ + i; 1173 } 1174 debugf("%s: start: %x count: %x\n", __func__, start, count); 1175 1176 mtx_unlock(&sc->sc_msi_mtx); 1177 return (0); 1178 } 1179 1180 static int 1181 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1182 { 1183 struct mv_pcib_softc *sc; 1184 u_int i; 1185 1186 sc = device_get_softc(dev); 1187 mtx_lock(&sc->sc_msi_mtx); 1188 1189 for (i = 0; i < count; i++) 1190 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1191 1192 mtx_unlock(&sc->sc_msi_mtx); 1193 return (0); 1194 } 1195 #endif 1196 1197