1 /*- 2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3 * Copyright (c) 2010 The FreeBSD Foundation 4 * Copyright (c) 2010-2012 Semihalf 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Portions of this software were developed by Semihalf 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of MARVELL nor the names of contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 /* 38 * Marvell integrated PCI/PCI-Express controller driver. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/queue.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/endian.h> 55 56 #include <machine/fdt.h> 57 #include <machine/intr.h> 58 59 #include <vm/vm.h> 60 #include <vm/pmap.h> 61 62 #include <dev/fdt/fdt_common.h> 63 #include <dev/ofw/ofw_bus.h> 64 #include <dev/ofw/ofw_pci.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcib_private.h> 69 70 #include "ofw_bus_if.h" 71 #include "pcib_if.h" 72 73 #include <machine/resource.h> 74 #include <machine/bus.h> 75 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvvar.h> 78 #include <arm/mv/mvwin.h> 79 80 #ifdef DEBUG 81 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 82 #else 83 #define debugf(fmt, args...) 84 #endif 85 86 #define PCI_CFG_ENA (1U << 31) 87 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 88 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 89 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 90 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 91 92 #define PCI_REG_CFG_ADDR 0x0C78 93 #define PCI_REG_CFG_DATA 0x0C7C 94 95 #define PCIE_REG_CFG_ADDR 0x18F8 96 #define PCIE_REG_CFG_DATA 0x18FC 97 #define PCIE_REG_CONTROL 0x1A00 98 #define PCIE_CTRL_LINK1X 0x00000001 99 #define PCIE_REG_STATUS 0x1A04 100 #define PCIE_REG_IRQ_MASK 0x1910 101 102 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 103 #define PCIE_CONTROL_HOT_RESET (1 << 24) 104 105 #define PCIE_LINK_TIMEOUT 1000000 106 107 #define PCIE_STATUS_LINK_DOWN 1 108 #define PCIE_STATUS_DEV_OFFS 16 109 110 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 111 #define PCI_MIN_IO_ALLOC 4 112 #define PCI_MIN_MEM_ALLOC 16 113 114 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 115 116 struct mv_pcib_softc { 117 device_t sc_dev; 118 119 struct rman sc_mem_rman; 120 bus_addr_t sc_mem_base; 121 bus_addr_t sc_mem_size; 122 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 123 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 124 int sc_win_target; 125 int sc_mem_win_attr; 126 127 struct rman sc_io_rman; 128 bus_addr_t sc_io_base; 129 bus_addr_t sc_io_size; 130 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 131 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 132 int sc_io_win_attr; 133 134 struct resource *sc_res; 135 bus_space_handle_t sc_bsh; 136 bus_space_tag_t sc_bst; 137 int sc_rid; 138 139 struct mtx sc_msi_mtx; 140 uint32_t sc_msi_bitmap; 141 142 int sc_busnr; /* Host bridge bus number */ 143 int sc_devnr; /* Host bridge device number */ 144 int sc_type; 145 int sc_mode; /* Endpoint / Root Complex */ 146 147 struct ofw_bus_iinfo sc_pci_iinfo; 148 }; 149 150 /* Local forward prototypes */ 151 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 152 static void mv_pcib_hw_cfginit(void); 153 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 154 u_int, u_int, int); 155 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 156 u_int, u_int, uint32_t, int); 157 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 158 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 159 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 160 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 161 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 162 static int mv_pcib_mem_init(struct mv_pcib_softc *); 163 164 /* Forward prototypes */ 165 static int mv_pcib_probe(device_t); 166 static int mv_pcib_attach(device_t); 167 168 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 169 u_long, u_long, u_long, u_int); 170 static int mv_pcib_release_resource(device_t, device_t, int, int, 171 struct resource *); 172 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 173 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 174 175 static int mv_pcib_maxslots(device_t); 176 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 177 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 178 uint32_t, int); 179 static int mv_pcib_route_interrupt(device_t, device_t, int); 180 #if defined(SOC_MV_ARMADAXP) 181 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 182 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 183 static int mv_pcib_release_msi(device_t, device_t, int, int *); 184 #endif 185 186 /* 187 * Bus interface definitions. 188 */ 189 static device_method_t mv_pcib_methods[] = { 190 /* Device interface */ 191 DEVMETHOD(device_probe, mv_pcib_probe), 192 DEVMETHOD(device_attach, mv_pcib_attach), 193 194 /* Bus interface */ 195 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 196 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 197 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 198 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 199 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 200 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 201 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 202 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 203 204 /* pcib interface */ 205 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 206 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 207 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 208 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 209 210 #if defined(SOC_MV_ARMADAXP) 211 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 212 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 213 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 214 #endif 215 216 /* OFW bus interface */ 217 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 218 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 219 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 220 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 221 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 222 223 DEVMETHOD_END 224 }; 225 226 static driver_t mv_pcib_driver = { 227 "pcib", 228 mv_pcib_methods, 229 sizeof(struct mv_pcib_softc), 230 }; 231 232 devclass_t pcib_devclass; 233 234 DRIVER_MODULE(pcib, nexus, mv_pcib_driver, pcib_devclass, 0, 0); 235 236 static struct mtx pcicfg_mtx; 237 238 static int 239 mv_pcib_probe(device_t self) 240 { 241 phandle_t node; 242 243 node = ofw_bus_get_node(self); 244 if (!fdt_is_type(node, "pci")) 245 return (ENXIO); 246 247 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 248 ofw_bus_is_compatible(self, "mrvl,pci"))) 249 return (ENXIO); 250 251 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 252 return (BUS_PROBE_DEFAULT); 253 } 254 255 static int 256 mv_pcib_attach(device_t self) 257 { 258 struct mv_pcib_softc *sc; 259 phandle_t node, parnode; 260 uint32_t val, unit; 261 int err; 262 263 sc = device_get_softc(self); 264 sc->sc_dev = self; 265 unit = fdt_get_unit(self); 266 267 268 node = ofw_bus_get_node(self); 269 parnode = OF_parent(node); 270 if (fdt_is_compatible(node, "mrvl,pcie")) { 271 sc->sc_type = MV_TYPE_PCIE; 272 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 273 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 274 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 275 } else if (fdt_is_compatible(node, "mrvl,pci")) { 276 sc->sc_type = MV_TYPE_PCI; 277 sc->sc_win_target = MV_WIN_PCI_TARGET; 278 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 279 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 280 } else 281 return (ENXIO); 282 283 /* 284 * Retrieve our mem-mapped registers range. 285 */ 286 sc->sc_rid = 0; 287 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 288 RF_ACTIVE); 289 if (sc->sc_res == NULL) { 290 device_printf(self, "could not map memory\n"); 291 return (ENXIO); 292 } 293 sc->sc_bst = rman_get_bustag(sc->sc_res); 294 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 295 296 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 297 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 298 MV_MODE_ENDPOINT); 299 300 /* 301 * Get PCI interrupt info. 302 */ 303 if (sc->sc_mode == MV_MODE_ROOT) 304 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 305 306 /* 307 * Configure decode windows for PCI(E) access. 308 */ 309 if (mv_pcib_decode_win(node, sc) != 0) 310 return (ENXIO); 311 312 mv_pcib_hw_cfginit(); 313 314 /* 315 * Enable PCIE device. 316 */ 317 mv_pcib_enable(sc, unit); 318 319 /* 320 * Memory management. 321 */ 322 err = mv_pcib_mem_init(sc); 323 if (err) 324 return (err); 325 326 if (sc->sc_mode == MV_MODE_ROOT) { 327 err = mv_pcib_init(sc, sc->sc_busnr, 328 mv_pcib_maxslots(sc->sc_dev)); 329 if (err) 330 goto error; 331 332 device_add_child(self, "pci", -1); 333 } else { 334 sc->sc_devnr = 1; 335 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 336 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 337 device_add_child(self, "pci_ep", -1); 338 } 339 340 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 341 return (bus_generic_attach(self)); 342 343 error: 344 /* XXX SYS_RES_ should be released here */ 345 rman_fini(&sc->sc_mem_rman); 346 rman_fini(&sc->sc_io_rman); 347 348 return (err); 349 } 350 351 static void 352 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 353 { 354 uint32_t val; 355 #if !defined(SOC_MV_ARMADAXP) 356 int timeout; 357 358 /* 359 * Check if PCIE device is enabled. 360 */ 361 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 362 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 363 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 364 365 timeout = PCIE_LINK_TIMEOUT; 366 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 367 PCIE_REG_STATUS); 368 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 369 DELAY(1000); 370 timeout -= 1000; 371 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 372 PCIE_REG_STATUS); 373 } 374 } 375 #endif 376 377 378 if (sc->sc_mode == MV_MODE_ROOT) { 379 /* 380 * Enable PCI bridge. 381 */ 382 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 383 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 384 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 385 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 386 } 387 } 388 389 static int 390 mv_pcib_mem_init(struct mv_pcib_softc *sc) 391 { 392 int err; 393 394 /* 395 * Memory management. 396 */ 397 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 398 err = rman_init(&sc->sc_mem_rman); 399 if (err) 400 return (err); 401 402 sc->sc_io_rman.rm_type = RMAN_ARRAY; 403 err = rman_init(&sc->sc_io_rman); 404 if (err) { 405 rman_fini(&sc->sc_mem_rman); 406 return (err); 407 } 408 409 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 410 sc->sc_mem_base + sc->sc_mem_size - 1); 411 if (err) 412 goto error; 413 414 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 415 sc->sc_io_base + sc->sc_io_size - 1); 416 if (err) 417 goto error; 418 419 return (0); 420 421 error: 422 rman_fini(&sc->sc_mem_rman); 423 rman_fini(&sc->sc_io_rman); 424 425 return (err); 426 } 427 428 static inline uint32_t 429 pcib_bit_get(uint32_t *map, uint32_t bit) 430 { 431 uint32_t n = bit / BITS_PER_UINT32; 432 433 bit = bit % BITS_PER_UINT32; 434 return (map[n] & (1 << bit)); 435 } 436 437 static inline void 438 pcib_bit_set(uint32_t *map, uint32_t bit) 439 { 440 uint32_t n = bit / BITS_PER_UINT32; 441 442 bit = bit % BITS_PER_UINT32; 443 map[n] |= (1 << bit); 444 } 445 446 static inline uint32_t 447 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 448 { 449 uint32_t i; 450 451 for (i = start; i < start + bits; i++) 452 if (pcib_bit_get(map, i)) 453 return (0); 454 455 return (1); 456 } 457 458 static inline void 459 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 460 { 461 uint32_t i; 462 463 for (i = start; i < start + bits; i++) 464 pcib_bit_set(map, i); 465 } 466 467 /* 468 * The idea of this allocator is taken from ARM No-Cache memory 469 * management code (sys/arm/arm/vm_machdep.c). 470 */ 471 static bus_addr_t 472 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 473 { 474 uint32_t bits, bits_limit, i, *map, min_alloc, size; 475 bus_addr_t addr = 0; 476 bus_addr_t base; 477 478 if (smask & 1) { 479 base = sc->sc_io_base; 480 min_alloc = PCI_MIN_IO_ALLOC; 481 bits_limit = sc->sc_io_size / min_alloc; 482 map = sc->sc_io_map; 483 smask &= ~0x3; 484 } else { 485 base = sc->sc_mem_base; 486 min_alloc = PCI_MIN_MEM_ALLOC; 487 bits_limit = sc->sc_mem_size / min_alloc; 488 map = sc->sc_mem_map; 489 smask &= ~0xF; 490 } 491 492 size = ~smask + 1; 493 bits = size / min_alloc; 494 495 for (i = 0; i + bits <= bits_limit; i += bits) 496 if (pcib_map_check(map, i, bits)) { 497 pcib_map_set(map, i, bits); 498 addr = base + (i * min_alloc); 499 return (addr); 500 } 501 502 return (addr); 503 } 504 505 static int 506 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 507 int barno) 508 { 509 uint32_t addr, bar; 510 int reg, width; 511 512 reg = PCIR_BAR(barno); 513 514 /* 515 * Need to init the BAR register with 0xffffffff before correct 516 * value can be read. 517 */ 518 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 519 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 520 if (bar == 0) 521 return (1); 522 523 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 524 width = ((bar & 7) == 4) ? 2 : 1; 525 526 addr = pcib_alloc(sc, bar); 527 if (!addr) 528 return (-1); 529 530 if (bootverbose) 531 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 532 bus, slot, func, reg, bar, addr); 533 534 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 535 if (width == 2) 536 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 537 0, 4); 538 539 return (width); 540 } 541 542 static void 543 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 544 { 545 bus_addr_t io_base, mem_base; 546 uint32_t io_limit, mem_limit; 547 int secbus; 548 549 io_base = sc->sc_io_base; 550 io_limit = io_base + sc->sc_io_size - 1; 551 mem_base = sc->sc_mem_base; 552 mem_limit = mem_base + sc->sc_mem_size - 1; 553 554 /* Configure I/O decode registers */ 555 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 556 io_base >> 8, 1); 557 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 558 io_base >> 16, 2); 559 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 560 io_limit >> 8, 1); 561 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 562 io_limit >> 16, 2); 563 564 /* Configure memory decode registers */ 565 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 566 mem_base >> 16, 2); 567 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 568 mem_limit >> 16, 2); 569 570 /* Disable memory prefetch decode */ 571 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 572 0x10, 2); 573 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 574 0x0, 4); 575 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 576 0xF, 2); 577 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 578 0x0, 4); 579 580 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 581 PCIR_SECBUS_1, 1); 582 583 /* Configure buses behind the bridge */ 584 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 585 } 586 587 static int 588 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 589 { 590 int slot, func, maxfunc, error; 591 uint8_t hdrtype, command, class, subclass; 592 593 for (slot = 0; slot <= maxslot; slot++) { 594 maxfunc = 0; 595 for (func = 0; func <= maxfunc; func++) { 596 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 597 func, PCIR_HDRTYPE, 1); 598 599 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 600 continue; 601 602 if (func == 0 && (hdrtype & PCIM_MFDEV)) 603 maxfunc = PCI_FUNCMAX; 604 605 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 606 func, PCIR_COMMAND, 1); 607 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 608 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 609 PCIR_COMMAND, command, 1); 610 611 error = mv_pcib_init_all_bars(sc, bus, slot, func, 612 hdrtype); 613 614 if (error) 615 return (error); 616 617 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 618 PCIM_CMD_PORTEN; 619 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 620 PCIR_COMMAND, command, 1); 621 622 /* Handle PCI-PCI bridges */ 623 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 624 func, PCIR_CLASS, 1); 625 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 626 func, PCIR_SUBCLASS, 1); 627 628 if (class != PCIC_BRIDGE || 629 subclass != PCIS_BRIDGE_PCI) 630 continue; 631 632 mv_pcib_init_bridge(sc, bus, slot, func); 633 } 634 } 635 636 /* Enable all ABCD interrupts */ 637 pcib_write_irq_mask(sc, (0xF << 24)); 638 639 return (0); 640 } 641 642 static int 643 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 644 int func, int hdrtype) 645 { 646 int maxbar, bar, i; 647 648 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 649 bar = 0; 650 651 /* Program the base address registers */ 652 while (bar < maxbar) { 653 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 654 bar += i; 655 if (i < 0) { 656 device_printf(sc->sc_dev, 657 "PCI IO/Memory space exhausted\n"); 658 return (ENOMEM); 659 } 660 } 661 662 return (0); 663 } 664 665 static struct resource * 666 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 667 u_long start, u_long end, u_long count, u_int flags) 668 { 669 struct mv_pcib_softc *sc = device_get_softc(dev); 670 struct rman *rm = NULL; 671 struct resource *res; 672 673 switch (type) { 674 case SYS_RES_IOPORT: 675 rm = &sc->sc_io_rman; 676 break; 677 case SYS_RES_MEMORY: 678 rm = &sc->sc_mem_rman; 679 break; 680 default: 681 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 682 type, rid, start, end, count, flags)); 683 }; 684 685 if ((start == 0UL) && (end == ~0UL)) { 686 start = sc->sc_mem_base; 687 end = sc->sc_mem_base + sc->sc_mem_size - 1; 688 count = sc->sc_mem_size; 689 } 690 691 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 692 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 693 return (NULL); 694 695 res = rman_reserve_resource(rm, start, end, count, flags, child); 696 if (res == NULL) 697 return (NULL); 698 699 rman_set_rid(res, *rid); 700 rman_set_bustag(res, fdtbus_bs_tag); 701 rman_set_bushandle(res, start); 702 703 if (flags & RF_ACTIVE) 704 if (bus_activate_resource(child, type, *rid, res)) { 705 rman_release_resource(res); 706 return (NULL); 707 } 708 709 return (res); 710 } 711 712 static int 713 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 714 struct resource *res) 715 { 716 717 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 718 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 719 type, rid, res)); 720 721 return (rman_release_resource(res)); 722 } 723 724 static int 725 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 726 { 727 struct mv_pcib_softc *sc = device_get_softc(dev); 728 729 switch (which) { 730 case PCIB_IVAR_BUS: 731 *result = sc->sc_busnr; 732 return (0); 733 case PCIB_IVAR_DOMAIN: 734 *result = device_get_unit(dev); 735 return (0); 736 } 737 738 return (ENOENT); 739 } 740 741 static int 742 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 743 { 744 struct mv_pcib_softc *sc = device_get_softc(dev); 745 746 switch (which) { 747 case PCIB_IVAR_BUS: 748 sc->sc_busnr = value; 749 return (0); 750 } 751 752 return (ENOENT); 753 } 754 755 static inline void 756 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 757 { 758 759 if (!sc->sc_type != MV_TYPE_PCI) 760 return; 761 762 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 763 } 764 765 static void 766 mv_pcib_hw_cfginit(void) 767 { 768 static int opened = 0; 769 770 if (opened) 771 return; 772 773 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 774 opened = 1; 775 } 776 777 static uint32_t 778 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 779 u_int func, u_int reg, int bytes) 780 { 781 uint32_t addr, data, ca, cd; 782 783 ca = (sc->sc_type != MV_TYPE_PCI) ? 784 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 785 cd = (sc->sc_type != MV_TYPE_PCI) ? 786 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 787 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 788 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 789 790 mtx_lock_spin(&pcicfg_mtx); 791 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 792 793 data = ~0; 794 switch (bytes) { 795 case 1: 796 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 797 cd + (reg & 3)); 798 break; 799 case 2: 800 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 801 cd + (reg & 2))); 802 break; 803 case 4: 804 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 805 cd)); 806 break; 807 } 808 mtx_unlock_spin(&pcicfg_mtx); 809 return (data); 810 } 811 812 static void 813 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 814 u_int func, u_int reg, uint32_t data, int bytes) 815 { 816 uint32_t addr, ca, cd; 817 818 ca = (sc->sc_type != MV_TYPE_PCI) ? 819 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 820 cd = (sc->sc_type != MV_TYPE_PCI) ? 821 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 822 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 823 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 824 825 mtx_lock_spin(&pcicfg_mtx); 826 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 827 828 switch (bytes) { 829 case 1: 830 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 831 cd + (reg & 3), data); 832 break; 833 case 2: 834 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 835 cd + (reg & 2), htole16(data)); 836 break; 837 case 4: 838 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 839 cd, htole32(data)); 840 break; 841 } 842 mtx_unlock_spin(&pcicfg_mtx); 843 } 844 845 static int 846 mv_pcib_maxslots(device_t dev) 847 { 848 struct mv_pcib_softc *sc = device_get_softc(dev); 849 850 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 851 } 852 853 static uint32_t 854 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 855 u_int reg, int bytes) 856 { 857 struct mv_pcib_softc *sc = device_get_softc(dev); 858 859 /* Return ~0 if link is inactive or trying to read from Root */ 860 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 861 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 862 return (~0U); 863 864 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 865 } 866 867 static void 868 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 869 u_int reg, uint32_t val, int bytes) 870 { 871 struct mv_pcib_softc *sc = device_get_softc(dev); 872 873 /* Return if link is inactive or trying to write to Root */ 874 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 875 PCIE_STATUS_LINK_DOWN) || (slot == 0)) 876 return; 877 878 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 879 } 880 881 static int 882 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 883 { 884 struct mv_pcib_softc *sc; 885 struct ofw_pci_register reg; 886 uint32_t pintr, mintr; 887 phandle_t iparent; 888 889 sc = device_get_softc(bus); 890 pintr = pin; 891 892 /* Fabricate imap information in case this isn't an OFW device */ 893 bzero(®, sizeof(reg)); 894 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 895 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 896 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 897 898 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 899 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), 900 &iparent)) 901 return (ofw_bus_map_intr(dev, iparent, mintr)); 902 903 /* Maybe it's a real interrupt, not an intpin */ 904 if (pin > 4) 905 return (pin); 906 907 device_printf(bus, "could not route pin %d for device %d.%d\n", 908 pin, pci_get_slot(dev), pci_get_function(dev)); 909 return (PCI_INVALID_IRQ); 910 } 911 912 static int 913 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 914 { 915 struct fdt_pci_range io_space, mem_space; 916 device_t dev; 917 int error; 918 919 dev = sc->sc_dev; 920 921 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 922 device_printf(dev, "could not retrieve 'ranges' data\n"); 923 return (error); 924 } 925 926 /* Configure CPU decoding windows */ 927 error = decode_win_cpu_set(sc->sc_win_target, 928 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 929 if (error < 0) { 930 device_printf(dev, "could not set up CPU decode " 931 "window for PCI IO\n"); 932 return (ENXIO); 933 } 934 error = decode_win_cpu_set(sc->sc_win_target, 935 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 936 mem_space.base_parent); 937 if (error < 0) { 938 device_printf(dev, "could not set up CPU decode " 939 "windows for PCI MEM\n"); 940 return (ENXIO); 941 } 942 943 sc->sc_io_base = io_space.base_parent; 944 sc->sc_io_size = io_space.len; 945 946 sc->sc_mem_base = mem_space.base_parent; 947 sc->sc_mem_size = mem_space.len; 948 949 return (0); 950 } 951 952 #if defined(SOC_MV_ARMADAXP) 953 static int 954 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 955 uint32_t *data) 956 { 957 struct mv_pcib_softc *sc; 958 959 sc = device_get_softc(dev); 960 irq = irq - MSI_IRQ; 961 962 /* validate parameters */ 963 if (isclr(&sc->sc_msi_bitmap, irq)) { 964 device_printf(dev, "invalid MSI 0x%x\n", irq); 965 return (EINVAL); 966 } 967 968 mv_msi_data(irq, addr, data); 969 970 debugf("%s: irq: %d addr: %jx data: %x\n", 971 __func__, irq, *addr, *data); 972 973 return (0); 974 } 975 976 static int 977 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 978 int maxcount __unused, int *irqs) 979 { 980 struct mv_pcib_softc *sc; 981 u_int start = 0, i; 982 983 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 984 return (EINVAL); 985 986 sc = device_get_softc(dev); 987 mtx_lock(&sc->sc_msi_mtx); 988 989 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 990 for (i = start; i < start + count; i++) { 991 if (isset(&sc->sc_msi_bitmap, i)) 992 break; 993 } 994 if (i == start + count) 995 break; 996 } 997 998 if ((start + count) == MSI_IRQ_NUM) { 999 mtx_unlock(&sc->sc_msi_mtx); 1000 return (ENXIO); 1001 } 1002 1003 for (i = start; i < start + count; i++) { 1004 setbit(&sc->sc_msi_bitmap, i); 1005 irqs[i] = MSI_IRQ + i; 1006 } 1007 debugf("%s: start: %x count: %x\n", __func__, start, count); 1008 1009 mtx_unlock(&sc->sc_msi_mtx); 1010 return (0); 1011 } 1012 1013 static int 1014 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1015 { 1016 struct mv_pcib_softc *sc; 1017 u_int i; 1018 1019 sc = device_get_softc(dev); 1020 mtx_lock(&sc->sc_msi_mtx); 1021 1022 for (i = 0; i < count; i++) 1023 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1024 1025 mtx_unlock(&sc->sc_msi_mtx); 1026 return (0); 1027 } 1028 #endif 1029