1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 5 * Copyright (c) 2010 The FreeBSD Foundation 6 * Copyright (c) 2010-2015 Semihalf 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Portions of this software were developed by Semihalf 12 * under sponsorship from the FreeBSD Foundation. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of MARVELL nor the names of contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Marvell integrated PCI/PCI-Express controller driver. 41 */ 42 43 #include <sys/cdefs.h> 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/lock.h> 48 #include <sys/malloc.h> 49 #include <sys/module.h> 50 #include <sys/mutex.h> 51 #include <sys/queue.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/endian.h> 55 #include <sys/devmap.h> 56 57 #include <machine/fdt.h> 58 #include <machine/intr.h> 59 60 #include <vm/vm.h> 61 #include <vm/pmap.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 #include <dev/ofw/ofw_pci.h> 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcib_private.h> 70 71 #include "ofw_bus_if.h" 72 #include "pcib_if.h" 73 74 #include <machine/resource.h> 75 #include <machine/bus.h> 76 77 #include <arm/mv/mvreg.h> 78 #include <arm/mv/mvvar.h> 79 #include <arm/mv/mvwin.h> 80 81 #ifdef DEBUG 82 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83 #else 84 #define debugf(fmt, args...) 85 #endif 86 87 /* 88 * Code and data related to fdt-based PCI configuration. 89 * 90 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91 * always Marvell-specific so that was deleted and the code now lives here. 92 */ 93 94 struct mv_pci_range { 95 u_long base_pci; 96 u_long base_parent; 97 u_long len; 98 }; 99 100 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101 #define PCI_SPACE_LEN 0x00400000 102 103 static void 104 mv_pci_range_dump(struct mv_pci_range *range) 105 { 106 #ifdef DEBUG 107 printf("\n"); 108 printf(" base_pci = 0x%08lx\n", range->base_pci); 109 printf(" base_par = 0x%08lx\n", range->base_parent); 110 printf(" len = 0x%08lx\n", range->len); 111 #endif 112 } 113 114 static int 115 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 116 struct mv_pci_range *mem_space) 117 { 118 pcell_t ranges[FDT_RANGES_CELLS]; 119 struct mv_pci_range *pci_space; 120 pcell_t addr_cells, size_cells, par_addr_cells; 121 pcell_t *rangesptr; 122 pcell_t cell0, cell2; 123 int tuple_size, tuples, i, rv, offset_cells, len; 124 int portid, is_io_space; 125 126 /* 127 * Retrieve 'ranges' property. 128 */ 129 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 130 return (EINVAL); 131 if (addr_cells != 3 || size_cells != 2) 132 return (ERANGE); 133 134 par_addr_cells = fdt_parent_addr_cells(node); 135 if (par_addr_cells > 3) 136 return (ERANGE); 137 138 len = OF_getproplen(node, "ranges"); 139 if (len > sizeof(ranges)) 140 return (ENOMEM); 141 142 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 143 return (EINVAL); 144 145 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 146 size_cells); 147 tuples = len / tuple_size; 148 149 /* 150 * Initialize the ranges so that we don't have to worry about 151 * having them all defined in the FDT. In particular, it is 152 * perfectly fine not to want I/O space on PCI buses. 153 */ 154 bzero(io_space, sizeof(*io_space)); 155 bzero(mem_space, sizeof(*mem_space)); 156 157 rangesptr = &ranges[0]; 158 offset_cells = 0; 159 for (i = 0; i < tuples; i++) { 160 cell0 = fdt_data_get((void *)rangesptr, 1); 161 rangesptr++; 162 /* cell1 */ 163 rangesptr++; 164 cell2 = fdt_data_get((void *)rangesptr, 1); 165 rangesptr++; 166 portid = fdt_data_get((void *)(rangesptr+1), 1); 167 168 if (cell0 & 0x02000000) { 169 pci_space = mem_space; 170 is_io_space = 0; 171 } else if (cell0 & 0x01000000) { 172 pci_space = io_space; 173 is_io_space = 1; 174 } else { 175 rv = ERANGE; 176 goto out; 177 } 178 179 if (par_addr_cells == 3) { 180 /* 181 * This is a PCI subnode 'ranges'. Skip cell0 and 182 * cell1 of this entry and only use cell2. 183 */ 184 offset_cells = 2; 185 rangesptr += offset_cells; 186 } 187 188 if ((par_addr_cells - offset_cells) > 2) { 189 rv = ERANGE; 190 goto out; 191 } 192 pci_space->base_parent = fdt_data_get((void *)rangesptr, 193 par_addr_cells - offset_cells); 194 rangesptr += par_addr_cells - offset_cells; 195 196 if (size_cells > 2) { 197 rv = ERANGE; 198 goto out; 199 } 200 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 201 rangesptr += size_cells; 202 203 pci_space->base_pci = cell2; 204 205 if (pci_space->len == 0) { 206 pci_space->len = PCI_SPACE_LEN; 207 pci_space->base_parent = fdt_immr_va + 208 PCI_SPACE_LEN * ( 2 * portid + is_io_space); 209 } 210 } 211 rv = 0; 212 out: 213 return (rv); 214 } 215 216 static int 217 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 218 struct mv_pci_range *mem_space) 219 { 220 int err; 221 222 debugf("Processing PCI node: %x\n", node); 223 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 224 debugf("could not decode parent PCI node 'ranges'\n"); 225 return (err); 226 } 227 228 debugf("Post fixup dump:\n"); 229 mv_pci_range_dump(io_space); 230 mv_pci_range_dump(mem_space); 231 return (0); 232 } 233 234 int 235 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 236 vm_offset_t mem_va) 237 { 238 struct mv_pci_range io_space, mem_space; 239 int error; 240 241 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 242 return (error); 243 244 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 245 devmap->pd_pa = io_space.base_parent; 246 devmap->pd_size = io_space.len; 247 devmap++; 248 249 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 250 devmap->pd_pa = mem_space.base_parent; 251 devmap->pd_size = mem_space.len; 252 return (0); 253 } 254 255 /* 256 * Code and data related to the Marvell pcib driver. 257 */ 258 259 #define PCI_CFG_ENA (1U << 31) 260 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 261 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 262 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 263 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 264 265 #define PCI_REG_CFG_ADDR 0x0C78 266 #define PCI_REG_CFG_DATA 0x0C7C 267 268 #define PCIE_REG_CFG_ADDR 0x18F8 269 #define PCIE_REG_CFG_DATA 0x18FC 270 #define PCIE_REG_CONTROL 0x1A00 271 #define PCIE_CTRL_LINK1X 0x00000001 272 #define PCIE_REG_STATUS 0x1A04 273 #define PCIE_REG_IRQ_MASK 0x1910 274 275 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 276 #define PCIE_CONTROL_HOT_RESET (1 << 24) 277 278 #define PCIE_LINK_TIMEOUT 1000000 279 280 #define PCIE_STATUS_LINK_DOWN 1 281 #define PCIE_STATUS_DEV_OFFS 16 282 283 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 284 #define PCI_MIN_IO_ALLOC 4 285 #define PCI_MIN_MEM_ALLOC 16 286 287 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 288 289 struct mv_pcib_softc { 290 device_t sc_dev; 291 292 struct rman sc_mem_rman; 293 bus_addr_t sc_mem_base; 294 bus_addr_t sc_mem_size; 295 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 296 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 297 int sc_win_target; 298 int sc_mem_win_attr; 299 300 struct rman sc_io_rman; 301 bus_addr_t sc_io_base; 302 bus_addr_t sc_io_size; 303 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 304 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 305 int sc_io_win_attr; 306 307 struct resource *sc_res; 308 bus_space_handle_t sc_bsh; 309 bus_space_tag_t sc_bst; 310 int sc_rid; 311 312 struct mtx sc_msi_mtx; 313 uint32_t sc_msi_bitmap; 314 315 int sc_busnr; /* Host bridge bus number */ 316 int sc_devnr; /* Host bridge device number */ 317 int sc_type; 318 int sc_mode; /* Endpoint / Root Complex */ 319 320 int sc_msi_supported; 321 int sc_skip_enable_procedure; 322 int sc_enable_find_root_slot; 323 struct ofw_bus_iinfo sc_pci_iinfo; 324 325 int ap_segment; /* PCI domain */ 326 }; 327 328 /* Local forward prototypes */ 329 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 330 static void mv_pcib_hw_cfginit(void); 331 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 332 u_int, u_int, int); 333 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 334 u_int, u_int, uint32_t, int); 335 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 336 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 337 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 338 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 339 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 340 static int mv_pcib_mem_init(struct mv_pcib_softc *); 341 342 /* Forward prototypes */ 343 static int mv_pcib_probe(device_t); 344 static int mv_pcib_attach(device_t); 345 346 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 347 rman_res_t, rman_res_t, rman_res_t, u_int); 348 static int mv_pcib_release_resource(device_t, device_t, int, int, 349 struct resource *); 350 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 351 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 352 353 static int mv_pcib_maxslots(device_t); 354 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 355 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 356 uint32_t, int); 357 static int mv_pcib_route_interrupt(device_t, device_t, int); 358 359 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 360 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 361 static int mv_pcib_release_msi(device_t, device_t, int, int *); 362 363 /* 364 * Bus interface definitions. 365 */ 366 static device_method_t mv_pcib_methods[] = { 367 /* Device interface */ 368 DEVMETHOD(device_probe, mv_pcib_probe), 369 DEVMETHOD(device_attach, mv_pcib_attach), 370 371 /* Bus interface */ 372 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 373 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 374 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 375 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 376 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 377 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 378 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 379 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 380 381 /* pcib interface */ 382 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 383 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 384 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 385 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 386 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 387 388 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 389 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 390 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 391 392 /* OFW bus interface */ 393 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 394 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 395 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 396 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 397 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 398 399 DEVMETHOD_END 400 }; 401 402 static driver_t mv_pcib_driver = { 403 "pcib", 404 mv_pcib_methods, 405 sizeof(struct mv_pcib_softc), 406 }; 407 408 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0); 409 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0); 410 411 static struct mtx pcicfg_mtx; 412 413 static int 414 mv_pcib_probe(device_t self) 415 { 416 phandle_t node; 417 418 node = ofw_bus_get_node(self); 419 if (!mv_fdt_is_type(node, "pci")) 420 return (ENXIO); 421 422 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 423 ofw_bus_is_compatible(self, "mrvl,pci") || 424 ofw_bus_node_is_compatible( 425 OF_parent(node), "marvell,armada-370-pcie"))) 426 return (ENXIO); 427 428 if (!ofw_bus_status_okay(self)) 429 return (ENXIO); 430 431 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 432 return (BUS_PROBE_DEFAULT); 433 } 434 435 static int 436 mv_pcib_attach(device_t self) 437 { 438 struct mv_pcib_softc *sc; 439 phandle_t node, parnode; 440 uint32_t val, reg0; 441 int err, bus, devfn, port_id; 442 443 sc = device_get_softc(self); 444 sc->sc_dev = self; 445 446 node = ofw_bus_get_node(self); 447 parnode = OF_parent(node); 448 449 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), 450 sizeof(port_id)) <= 0) { 451 /* If port ID does not exist in the FDT set value to 0 */ 452 if (!OF_hasprop(node, "marvell,pcie-port")) 453 port_id = 0; 454 else 455 return(ENXIO); 456 } 457 458 sc->ap_segment = port_id; 459 460 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) { 461 sc->sc_type = MV_TYPE_PCIE; 462 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); 463 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); 464 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); 465 sc->sc_skip_enable_procedure = 1; 466 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { 467 sc->sc_type = MV_TYPE_PCIE; 468 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); 469 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); 470 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); 471 sc->sc_enable_find_root_slot = 1; 472 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) { 473 sc->sc_type = MV_TYPE_PCI; 474 sc->sc_win_target = MV_WIN_PCI_TARGET; 475 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 476 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 477 } else 478 return (ENXIO); 479 480 /* 481 * Retrieve our mem-mapped registers range. 482 */ 483 sc->sc_rid = 0; 484 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 485 RF_ACTIVE); 486 if (sc->sc_res == NULL) { 487 device_printf(self, "could not map memory\n"); 488 return (ENXIO); 489 } 490 sc->sc_bst = rman_get_bustag(sc->sc_res); 491 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 492 493 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 494 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 495 MV_MODE_ENDPOINT); 496 497 /* 498 * Get PCI interrupt info. 499 */ 500 if (sc->sc_mode == MV_MODE_ROOT) 501 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 502 503 /* 504 * Configure decode windows for PCI(E) access. 505 */ 506 if (mv_pcib_decode_win(node, sc) != 0) 507 return (ENXIO); 508 509 mv_pcib_hw_cfginit(); 510 511 /* 512 * Enable PCIE device. 513 */ 514 mv_pcib_enable(sc, port_id); 515 516 /* 517 * Memory management. 518 */ 519 err = mv_pcib_mem_init(sc); 520 if (err) 521 return (err); 522 523 /* 524 * Preliminary bus enumeration to find first linked devices and set 525 * appropriate bus number from which should start the actual enumeration 526 */ 527 for (bus = 0; bus < PCI_BUSMAX; bus++) { 528 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) { 529 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); 530 if (reg0 == (~0U)) 531 continue; /* no device */ 532 else { 533 sc->sc_busnr = bus; /* update bus number */ 534 break; 535 } 536 } 537 } 538 539 if (sc->sc_mode == MV_MODE_ROOT) { 540 err = mv_pcib_init(sc, sc->sc_busnr, 541 mv_pcib_maxslots(sc->sc_dev)); 542 if (err) 543 goto error; 544 545 device_add_child(self, "pci", -1); 546 } else { 547 sc->sc_devnr = 1; 548 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 549 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 550 device_add_child(self, "pci_ep", -1); 551 } 552 553 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 554 return (bus_generic_attach(self)); 555 556 error: 557 /* XXX SYS_RES_ should be released here */ 558 rman_fini(&sc->sc_mem_rman); 559 rman_fini(&sc->sc_io_rman); 560 561 return (err); 562 } 563 564 static void 565 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 566 { 567 uint32_t val; 568 int timeout; 569 570 if (sc->sc_skip_enable_procedure) 571 goto pcib_enable_root_mode; 572 573 /* 574 * Check if PCIE device is enabled. 575 */ 576 if ((sc->sc_skip_enable_procedure == 0) && 577 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) { 578 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 579 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 580 581 timeout = PCIE_LINK_TIMEOUT; 582 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 583 PCIE_REG_STATUS); 584 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 585 DELAY(1000); 586 timeout -= 1000; 587 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 588 PCIE_REG_STATUS); 589 } 590 } 591 592 pcib_enable_root_mode: 593 if (sc->sc_mode == MV_MODE_ROOT) { 594 /* 595 * Enable PCI bridge. 596 */ 597 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 598 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 599 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 601 } 602 } 603 604 static int 605 mv_pcib_mem_init(struct mv_pcib_softc *sc) 606 { 607 int err; 608 609 /* 610 * Memory management. 611 */ 612 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 613 err = rman_init(&sc->sc_mem_rman); 614 if (err) 615 return (err); 616 617 sc->sc_io_rman.rm_type = RMAN_ARRAY; 618 err = rman_init(&sc->sc_io_rman); 619 if (err) { 620 rman_fini(&sc->sc_mem_rman); 621 return (err); 622 } 623 624 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 625 sc->sc_mem_base + sc->sc_mem_size - 1); 626 if (err) 627 goto error; 628 629 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 630 sc->sc_io_base + sc->sc_io_size - 1); 631 if (err) 632 goto error; 633 634 return (0); 635 636 error: 637 rman_fini(&sc->sc_mem_rman); 638 rman_fini(&sc->sc_io_rman); 639 640 return (err); 641 } 642 643 static inline uint32_t 644 pcib_bit_get(uint32_t *map, uint32_t bit) 645 { 646 uint32_t n = bit / BITS_PER_UINT32; 647 648 bit = bit % BITS_PER_UINT32; 649 return (map[n] & (1 << bit)); 650 } 651 652 static inline void 653 pcib_bit_set(uint32_t *map, uint32_t bit) 654 { 655 uint32_t n = bit / BITS_PER_UINT32; 656 657 bit = bit % BITS_PER_UINT32; 658 map[n] |= (1 << bit); 659 } 660 661 static inline uint32_t 662 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 663 { 664 uint32_t i; 665 666 for (i = start; i < start + bits; i++) 667 if (pcib_bit_get(map, i)) 668 return (0); 669 670 return (1); 671 } 672 673 static inline void 674 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 675 { 676 uint32_t i; 677 678 for (i = start; i < start + bits; i++) 679 pcib_bit_set(map, i); 680 } 681 682 /* 683 * The idea of this allocator is taken from ARM No-Cache memory 684 * management code (sys/arm/arm/vm_machdep.c). 685 */ 686 static bus_addr_t 687 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 688 { 689 uint32_t bits, bits_limit, i, *map, min_alloc, size; 690 bus_addr_t addr = 0; 691 bus_addr_t base; 692 693 if (smask & 1) { 694 base = sc->sc_io_base; 695 min_alloc = PCI_MIN_IO_ALLOC; 696 bits_limit = sc->sc_io_size / min_alloc; 697 map = sc->sc_io_map; 698 smask &= ~0x3; 699 } else { 700 base = sc->sc_mem_base; 701 min_alloc = PCI_MIN_MEM_ALLOC; 702 bits_limit = sc->sc_mem_size / min_alloc; 703 map = sc->sc_mem_map; 704 smask &= ~0xF; 705 } 706 707 size = ~smask + 1; 708 bits = size / min_alloc; 709 710 for (i = 0; i + bits <= bits_limit; i += bits) 711 if (pcib_map_check(map, i, bits)) { 712 pcib_map_set(map, i, bits); 713 addr = base + (i * min_alloc); 714 return (addr); 715 } 716 717 return (addr); 718 } 719 720 static int 721 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 722 int barno) 723 { 724 uint32_t addr, bar; 725 int reg, width; 726 727 reg = PCIR_BAR(barno); 728 729 /* 730 * Need to init the BAR register with 0xffffffff before correct 731 * value can be read. 732 */ 733 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 734 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 735 if (bar == 0) 736 return (1); 737 738 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 739 width = ((bar & 7) == 4) ? 2 : 1; 740 741 addr = pcib_alloc(sc, bar); 742 if (!addr) 743 return (-1); 744 745 if (bootverbose) 746 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 747 bus, slot, func, reg, bar, addr); 748 749 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 750 if (width == 2) 751 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 752 0, 4); 753 754 return (width); 755 } 756 757 static void 758 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 759 { 760 bus_addr_t io_base, mem_base; 761 uint32_t io_limit, mem_limit; 762 int secbus; 763 764 io_base = sc->sc_io_base; 765 io_limit = io_base + sc->sc_io_size - 1; 766 mem_base = sc->sc_mem_base; 767 mem_limit = mem_base + sc->sc_mem_size - 1; 768 769 /* Configure I/O decode registers */ 770 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 771 io_base >> 8, 1); 772 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 773 io_base >> 16, 2); 774 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 775 io_limit >> 8, 1); 776 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 777 io_limit >> 16, 2); 778 779 /* Configure memory decode registers */ 780 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 781 mem_base >> 16, 2); 782 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 783 mem_limit >> 16, 2); 784 785 /* Disable memory prefetch decode */ 786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 787 0x10, 2); 788 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 789 0x0, 4); 790 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 791 0xF, 2); 792 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 793 0x0, 4); 794 795 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 796 PCIR_SECBUS_1, 1); 797 798 /* Configure buses behind the bridge */ 799 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 800 } 801 802 static int 803 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 804 { 805 int slot, func, maxfunc, error; 806 uint8_t hdrtype, command, class, subclass; 807 808 for (slot = 0; slot <= maxslot; slot++) { 809 maxfunc = 0; 810 for (func = 0; func <= maxfunc; func++) { 811 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 812 func, PCIR_HDRTYPE, 1); 813 814 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 815 continue; 816 817 if (func == 0 && (hdrtype & PCIM_MFDEV)) 818 maxfunc = PCI_FUNCMAX; 819 820 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 821 func, PCIR_COMMAND, 1); 822 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 823 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 824 PCIR_COMMAND, command, 1); 825 826 error = mv_pcib_init_all_bars(sc, bus, slot, func, 827 hdrtype); 828 829 if (error) 830 return (error); 831 832 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 833 PCIM_CMD_PORTEN; 834 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 835 PCIR_COMMAND, command, 1); 836 837 /* Handle PCI-PCI bridges */ 838 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 839 func, PCIR_CLASS, 1); 840 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 841 func, PCIR_SUBCLASS, 1); 842 843 if (class != PCIC_BRIDGE || 844 subclass != PCIS_BRIDGE_PCI) 845 continue; 846 847 mv_pcib_init_bridge(sc, bus, slot, func); 848 } 849 } 850 851 /* Enable all ABCD interrupts */ 852 pcib_write_irq_mask(sc, (0xF << 24)); 853 854 return (0); 855 } 856 857 static int 858 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 859 int func, int hdrtype) 860 { 861 int maxbar, bar, i; 862 863 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 864 bar = 0; 865 866 /* Program the base address registers */ 867 while (bar < maxbar) { 868 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 869 bar += i; 870 if (i < 0) { 871 device_printf(sc->sc_dev, 872 "PCI IO/Memory space exhausted\n"); 873 return (ENOMEM); 874 } 875 } 876 877 return (0); 878 } 879 880 static struct resource * 881 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 882 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 883 { 884 struct mv_pcib_softc *sc = device_get_softc(dev); 885 struct rman *rm = NULL; 886 struct resource *res; 887 888 switch (type) { 889 case SYS_RES_IOPORT: 890 rm = &sc->sc_io_rman; 891 break; 892 case SYS_RES_MEMORY: 893 rm = &sc->sc_mem_rman; 894 break; 895 #ifdef PCI_RES_BUS 896 case PCI_RES_BUS: 897 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, 898 end, count, flags)); 899 #endif 900 default: 901 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 902 type, rid, start, end, count, flags)); 903 } 904 905 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 906 start = sc->sc_mem_base; 907 end = sc->sc_mem_base + sc->sc_mem_size - 1; 908 count = sc->sc_mem_size; 909 } 910 911 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 912 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 913 return (NULL); 914 915 res = rman_reserve_resource(rm, start, end, count, flags, child); 916 if (res == NULL) 917 return (NULL); 918 919 rman_set_rid(res, *rid); 920 rman_set_bustag(res, fdtbus_bs_tag); 921 rman_set_bushandle(res, start); 922 923 if (flags & RF_ACTIVE) 924 if (bus_activate_resource(child, type, *rid, res)) { 925 rman_release_resource(res); 926 return (NULL); 927 } 928 929 return (res); 930 } 931 932 static int 933 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 934 struct resource *res) 935 { 936 #ifdef PCI_RES_BUS 937 struct mv_pcib_softc *sc = device_get_softc(dev); 938 939 if (type == PCI_RES_BUS) 940 return (pci_domain_release_bus(sc->ap_segment, child, rid, res)); 941 #endif 942 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 943 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 944 type, rid, res)); 945 946 return (rman_release_resource(res)); 947 } 948 949 static int 950 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 951 { 952 struct mv_pcib_softc *sc = device_get_softc(dev); 953 954 switch (which) { 955 case PCIB_IVAR_BUS: 956 *result = sc->sc_busnr; 957 return (0); 958 case PCIB_IVAR_DOMAIN: 959 *result = device_get_unit(dev); 960 return (0); 961 } 962 963 return (ENOENT); 964 } 965 966 static int 967 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 968 { 969 struct mv_pcib_softc *sc = device_get_softc(dev); 970 971 switch (which) { 972 case PCIB_IVAR_BUS: 973 sc->sc_busnr = value; 974 return (0); 975 } 976 977 return (ENOENT); 978 } 979 980 static inline void 981 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 982 { 983 984 if (sc->sc_type != MV_TYPE_PCIE) 985 return; 986 987 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 988 } 989 990 static void 991 mv_pcib_hw_cfginit(void) 992 { 993 static int opened = 0; 994 995 if (opened) 996 return; 997 998 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 999 opened = 1; 1000 } 1001 1002 static uint32_t 1003 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1004 u_int func, u_int reg, int bytes) 1005 { 1006 uint32_t addr, data, ca, cd; 1007 1008 ca = (sc->sc_type != MV_TYPE_PCI) ? 1009 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1010 cd = (sc->sc_type != MV_TYPE_PCI) ? 1011 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1012 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1013 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1014 1015 mtx_lock_spin(&pcicfg_mtx); 1016 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1017 1018 data = ~0; 1019 switch (bytes) { 1020 case 1: 1021 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1022 cd + (reg & 3)); 1023 break; 1024 case 2: 1025 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 1026 cd + (reg & 2))); 1027 break; 1028 case 4: 1029 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 1030 cd)); 1031 break; 1032 } 1033 mtx_unlock_spin(&pcicfg_mtx); 1034 return (data); 1035 } 1036 1037 static void 1038 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1039 u_int func, u_int reg, uint32_t data, int bytes) 1040 { 1041 uint32_t addr, ca, cd; 1042 1043 ca = (sc->sc_type != MV_TYPE_PCI) ? 1044 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1045 cd = (sc->sc_type != MV_TYPE_PCI) ? 1046 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1047 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1048 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1049 1050 mtx_lock_spin(&pcicfg_mtx); 1051 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1052 1053 switch (bytes) { 1054 case 1: 1055 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1056 cd + (reg & 3), data); 1057 break; 1058 case 2: 1059 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1060 cd + (reg & 2), htole16(data)); 1061 break; 1062 case 4: 1063 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1064 cd, htole32(data)); 1065 break; 1066 } 1067 mtx_unlock_spin(&pcicfg_mtx); 1068 } 1069 1070 static int 1071 mv_pcib_maxslots(device_t dev) 1072 { 1073 struct mv_pcib_softc *sc = device_get_softc(dev); 1074 1075 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1076 } 1077 1078 static int 1079 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1080 { 1081 struct mv_pcib_softc *sc = device_get_softc(dev); 1082 uint32_t vendor, device; 1083 1084 /* On platforms other than Armada38x, root link is always at slot 0 */ 1085 if (!sc->sc_enable_find_root_slot) 1086 return (slot == 0); 1087 1088 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1089 PCIR_VENDOR_LENGTH); 1090 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1091 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1092 1093 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1094 } 1095 1096 static uint32_t 1097 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1098 u_int reg, int bytes) 1099 { 1100 struct mv_pcib_softc *sc = device_get_softc(dev); 1101 1102 /* Return ~0 if link is inactive or trying to read from Root */ 1103 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1104 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1105 return (~0U); 1106 1107 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1108 } 1109 1110 static void 1111 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1112 u_int reg, uint32_t val, int bytes) 1113 { 1114 struct mv_pcib_softc *sc = device_get_softc(dev); 1115 1116 /* Return if link is inactive or trying to write to Root */ 1117 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1118 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1119 return; 1120 1121 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1122 } 1123 1124 static int 1125 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1126 { 1127 struct mv_pcib_softc *sc; 1128 struct ofw_pci_register reg; 1129 uint32_t pintr, mintr[4]; 1130 int icells; 1131 phandle_t iparent; 1132 1133 sc = device_get_softc(bus); 1134 pintr = pin; 1135 1136 /* Fabricate imap information in case this isn't an OFW device */ 1137 bzero(®, sizeof(reg)); 1138 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1139 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1140 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1141 1142 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1143 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1144 &iparent); 1145 if (icells > 0) 1146 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1147 1148 /* Maybe it's a real interrupt, not an intpin */ 1149 if (pin > 4) 1150 return (pin); 1151 1152 device_printf(bus, "could not route pin %d for device %d.%d\n", 1153 pin, pci_get_slot(dev), pci_get_function(dev)); 1154 return (PCI_INVALID_IRQ); 1155 } 1156 1157 static int 1158 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1159 { 1160 struct mv_pci_range io_space, mem_space; 1161 device_t dev; 1162 int error; 1163 1164 dev = sc->sc_dev; 1165 1166 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1167 device_printf(dev, "could not retrieve 'ranges' data\n"); 1168 return (error); 1169 } 1170 1171 /* Configure CPU decoding windows */ 1172 error = decode_win_cpu_set(sc->sc_win_target, 1173 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1174 if (error < 0) { 1175 device_printf(dev, "could not set up CPU decode " 1176 "window for PCI IO\n"); 1177 return (ENXIO); 1178 } 1179 error = decode_win_cpu_set(sc->sc_win_target, 1180 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1181 mem_space.base_parent); 1182 if (error < 0) { 1183 device_printf(dev, "could not set up CPU decode " 1184 "windows for PCI MEM\n"); 1185 return (ENXIO); 1186 } 1187 1188 sc->sc_io_base = io_space.base_parent; 1189 sc->sc_io_size = io_space.len; 1190 1191 sc->sc_mem_base = mem_space.base_parent; 1192 sc->sc_mem_size = mem_space.len; 1193 1194 return (0); 1195 } 1196 1197 static int 1198 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1199 uint32_t *data) 1200 { 1201 struct mv_pcib_softc *sc; 1202 1203 sc = device_get_softc(dev); 1204 if (!sc->sc_msi_supported) 1205 return (ENOTSUP); 1206 1207 irq = irq - MSI_IRQ; 1208 1209 /* validate parameters */ 1210 if (isclr(&sc->sc_msi_bitmap, irq)) { 1211 device_printf(dev, "invalid MSI 0x%x\n", irq); 1212 return (EINVAL); 1213 } 1214 1215 mv_msi_data(irq, addr, data); 1216 1217 debugf("%s: irq: %d addr: %jx data: %x\n", 1218 __func__, irq, *addr, *data); 1219 1220 return (0); 1221 } 1222 1223 static int 1224 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1225 int maxcount __unused, int *irqs) 1226 { 1227 struct mv_pcib_softc *sc; 1228 u_int start = 0, i; 1229 1230 sc = device_get_softc(dev); 1231 if (!sc->sc_msi_supported) 1232 return (ENOTSUP); 1233 1234 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1235 return (EINVAL); 1236 1237 mtx_lock(&sc->sc_msi_mtx); 1238 1239 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1240 for (i = start; i < start + count; i++) { 1241 if (isset(&sc->sc_msi_bitmap, i)) 1242 break; 1243 } 1244 if (i == start + count) 1245 break; 1246 } 1247 1248 if ((start + count) == MSI_IRQ_NUM) { 1249 mtx_unlock(&sc->sc_msi_mtx); 1250 return (ENXIO); 1251 } 1252 1253 for (i = start; i < start + count; i++) { 1254 setbit(&sc->sc_msi_bitmap, i); 1255 *irqs++ = MSI_IRQ + i; 1256 } 1257 debugf("%s: start: %x count: %x\n", __func__, start, count); 1258 1259 mtx_unlock(&sc->sc_msi_mtx); 1260 return (0); 1261 } 1262 1263 static int 1264 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1265 { 1266 struct mv_pcib_softc *sc; 1267 u_int i; 1268 1269 sc = device_get_softc(dev); 1270 if(!sc->sc_msi_supported) 1271 return (ENOTSUP); 1272 1273 mtx_lock(&sc->sc_msi_mtx); 1274 1275 for (i = 0; i < count; i++) 1276 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1277 1278 mtx_unlock(&sc->sc_msi_mtx); 1279 return (0); 1280 } 1281