xref: /freebsd/sys/arm/mv/mv_pci.c (revision c16bfb03cb834fb4b5ae43271f9aec1feab2782b)
16975124cSRafal Jaworowski /*-
251369649SPedro F. Giffuni  * SPDX-License-Identifier: BSD-3-Clause
351369649SPedro F. Giffuni  *
4db5ef4fcSRafal Jaworowski  * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
5db5ef4fcSRafal Jaworowski  * Copyright (c) 2010 The FreeBSD Foundation
61e92574fSZbigniew Bodek  * Copyright (c) 2010-2015 Semihalf
76975124cSRafal Jaworowski  * All rights reserved.
86975124cSRafal Jaworowski  *
96975124cSRafal Jaworowski  * Developed by Semihalf.
106975124cSRafal Jaworowski  *
11db5ef4fcSRafal Jaworowski  * Portions of this software were developed by Semihalf
12db5ef4fcSRafal Jaworowski  * under sponsorship from the FreeBSD Foundation.
13db5ef4fcSRafal Jaworowski  *
146975124cSRafal Jaworowski  * Redistribution and use in source and binary forms, with or without
156975124cSRafal Jaworowski  * modification, are permitted provided that the following conditions
166975124cSRafal Jaworowski  * are met:
176975124cSRafal Jaworowski  * 1. Redistributions of source code must retain the above copyright
186975124cSRafal Jaworowski  *    notice, this list of conditions and the following disclaimer.
196975124cSRafal Jaworowski  * 2. Redistributions in binary form must reproduce the above copyright
206975124cSRafal Jaworowski  *    notice, this list of conditions and the following disclaimer in the
216975124cSRafal Jaworowski  *    documentation and/or other materials provided with the distribution.
226975124cSRafal Jaworowski  * 3. Neither the name of MARVELL nor the names of contributors
236975124cSRafal Jaworowski  *    may be used to endorse or promote products derived from this software
246975124cSRafal Jaworowski  *    without specific prior written permission.
256975124cSRafal Jaworowski  *
266975124cSRafal Jaworowski  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
276975124cSRafal Jaworowski  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
286975124cSRafal Jaworowski  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
296975124cSRafal Jaworowski  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
306975124cSRafal Jaworowski  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
316975124cSRafal Jaworowski  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
326975124cSRafal Jaworowski  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
336975124cSRafal Jaworowski  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
346975124cSRafal Jaworowski  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
356975124cSRafal Jaworowski  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
366975124cSRafal Jaworowski  * SUCH DAMAGE.
376975124cSRafal Jaworowski  */
386975124cSRafal Jaworowski 
396975124cSRafal Jaworowski /*
406975124cSRafal Jaworowski  * Marvell integrated PCI/PCI-Express controller driver.
416975124cSRafal Jaworowski  */
426975124cSRafal Jaworowski 
436975124cSRafal Jaworowski #include <sys/cdefs.h>
446975124cSRafal Jaworowski __FBSDID("$FreeBSD$");
456975124cSRafal Jaworowski 
466975124cSRafal Jaworowski #include <sys/param.h>
476975124cSRafal Jaworowski #include <sys/systm.h>
486975124cSRafal Jaworowski #include <sys/kernel.h>
496975124cSRafal Jaworowski #include <sys/lock.h>
506975124cSRafal Jaworowski #include <sys/malloc.h>
516975124cSRafal Jaworowski #include <sys/module.h>
526975124cSRafal Jaworowski #include <sys/mutex.h>
536975124cSRafal Jaworowski #include <sys/queue.h>
546975124cSRafal Jaworowski #include <sys/bus.h>
556975124cSRafal Jaworowski #include <sys/rman.h>
566975124cSRafal Jaworowski #include <sys/endian.h>
5730b72b68SRuslan Bukin #include <sys/devmap.h>
586975124cSRafal Jaworowski 
59dcd08302SNathan Whitehorn #include <machine/fdt.h>
6064dc1cf3SGrzegorz Bernacki #include <machine/intr.h>
6164dc1cf3SGrzegorz Bernacki 
626975124cSRafal Jaworowski #include <vm/vm.h>
636975124cSRafal Jaworowski #include <vm/pmap.h>
646975124cSRafal Jaworowski 
65db5ef4fcSRafal Jaworowski #include <dev/fdt/fdt_common.h>
66db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus.h>
67db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus_subr.h>
68f9a32acbSAndrew Turner #include <dev/ofw/ofw_pci.h>
696975124cSRafal Jaworowski #include <dev/pci/pcivar.h>
706975124cSRafal Jaworowski #include <dev/pci/pcireg.h>
716975124cSRafal Jaworowski #include <dev/pci/pcib_private.h>
726975124cSRafal Jaworowski 
73db5ef4fcSRafal Jaworowski #include "ofw_bus_if.h"
746975124cSRafal Jaworowski #include "pcib_if.h"
756975124cSRafal Jaworowski 
766975124cSRafal Jaworowski #include <machine/resource.h>
776975124cSRafal Jaworowski #include <machine/bus.h>
786975124cSRafal Jaworowski 
796975124cSRafal Jaworowski #include <arm/mv/mvreg.h>
806975124cSRafal Jaworowski #include <arm/mv/mvvar.h>
81db5ef4fcSRafal Jaworowski #include <arm/mv/mvwin.h>
826975124cSRafal Jaworowski 
8364dc1cf3SGrzegorz Bernacki #ifdef DEBUG
8464dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
8564dc1cf3SGrzegorz Bernacki #else
8664dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...)
8764dc1cf3SGrzegorz Bernacki #endif
8864dc1cf3SGrzegorz Bernacki 
8902c7dba9SIan Lepore /*
9002c7dba9SIan Lepore  * Code and data related to fdt-based PCI configuration.
9102c7dba9SIan Lepore  *
9202c7dba9SIan Lepore  * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
9302c7dba9SIan Lepore  * always Marvell-specific so that was deleted and the code now lives here.
9402c7dba9SIan Lepore  */
9502c7dba9SIan Lepore 
9602c7dba9SIan Lepore struct mv_pci_range {
9702c7dba9SIan Lepore 	u_long	base_pci;
9802c7dba9SIan Lepore 	u_long	base_parent;
9902c7dba9SIan Lepore 	u_long	len;
10002c7dba9SIan Lepore };
10102c7dba9SIan Lepore 
10202c7dba9SIan Lepore #define FDT_RANGES_CELLS	((3 + 3 + 2) * 2)
1036534f932SOleksandr Tymoshenko #define PCI_SPACE_LEN		0x00400000
10402c7dba9SIan Lepore 
10502c7dba9SIan Lepore static void
10602c7dba9SIan Lepore mv_pci_range_dump(struct mv_pci_range *range)
10702c7dba9SIan Lepore {
10802c7dba9SIan Lepore #ifdef DEBUG
10902c7dba9SIan Lepore 	printf("\n");
11002c7dba9SIan Lepore 	printf("  base_pci = 0x%08lx\n", range->base_pci);
11102c7dba9SIan Lepore 	printf("  base_par = 0x%08lx\n", range->base_parent);
11202c7dba9SIan Lepore 	printf("  len      = 0x%08lx\n", range->len);
11302c7dba9SIan Lepore #endif
11402c7dba9SIan Lepore }
11502c7dba9SIan Lepore 
11602c7dba9SIan Lepore static int
11702c7dba9SIan Lepore mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
11802c7dba9SIan Lepore     struct mv_pci_range *mem_space)
11902c7dba9SIan Lepore {
12002c7dba9SIan Lepore 	pcell_t ranges[FDT_RANGES_CELLS];
12102c7dba9SIan Lepore 	struct mv_pci_range *pci_space;
12202c7dba9SIan Lepore 	pcell_t addr_cells, size_cells, par_addr_cells;
12302c7dba9SIan Lepore 	pcell_t *rangesptr;
124*c16bfb03SJohn Baldwin 	pcell_t cell0, cell2;
12502c7dba9SIan Lepore 	int tuple_size, tuples, i, rv, offset_cells, len;
12646db7283SMarcin Wojtas 	int  portid, is_io_space;
12702c7dba9SIan Lepore 
12802c7dba9SIan Lepore 	/*
12902c7dba9SIan Lepore 	 * Retrieve 'ranges' property.
13002c7dba9SIan Lepore 	 */
13102c7dba9SIan Lepore 	if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
13202c7dba9SIan Lepore 		return (EINVAL);
13302c7dba9SIan Lepore 	if (addr_cells != 3 || size_cells != 2)
13402c7dba9SIan Lepore 		return (ERANGE);
13502c7dba9SIan Lepore 
13602c7dba9SIan Lepore 	par_addr_cells = fdt_parent_addr_cells(node);
13702c7dba9SIan Lepore 	if (par_addr_cells > 3)
13802c7dba9SIan Lepore 		return (ERANGE);
13902c7dba9SIan Lepore 
14002c7dba9SIan Lepore 	len = OF_getproplen(node, "ranges");
14102c7dba9SIan Lepore 	if (len > sizeof(ranges))
14202c7dba9SIan Lepore 		return (ENOMEM);
14302c7dba9SIan Lepore 
14402c7dba9SIan Lepore 	if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
14502c7dba9SIan Lepore 		return (EINVAL);
14602c7dba9SIan Lepore 
14702c7dba9SIan Lepore 	tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
14802c7dba9SIan Lepore 	    size_cells);
14902c7dba9SIan Lepore 	tuples = len / tuple_size;
15002c7dba9SIan Lepore 
15102c7dba9SIan Lepore 	/*
15202c7dba9SIan Lepore 	 * Initialize the ranges so that we don't have to worry about
15302c7dba9SIan Lepore 	 * having them all defined in the FDT. In particular, it is
154db4fcadfSConrad Meyer 	 * perfectly fine not to want I/O space on PCI buses.
15502c7dba9SIan Lepore 	 */
15602c7dba9SIan Lepore 	bzero(io_space, sizeof(*io_space));
15702c7dba9SIan Lepore 	bzero(mem_space, sizeof(*mem_space));
15802c7dba9SIan Lepore 
15902c7dba9SIan Lepore 	rangesptr = &ranges[0];
16002c7dba9SIan Lepore 	offset_cells = 0;
16102c7dba9SIan Lepore 	for (i = 0; i < tuples; i++) {
16202c7dba9SIan Lepore 		cell0 = fdt_data_get((void *)rangesptr, 1);
16302c7dba9SIan Lepore 		rangesptr++;
164*c16bfb03SJohn Baldwin 		/* cell1 */
16502c7dba9SIan Lepore 		rangesptr++;
16602c7dba9SIan Lepore 		cell2 = fdt_data_get((void *)rangesptr, 1);
16702c7dba9SIan Lepore 		rangesptr++;
16846db7283SMarcin Wojtas 		portid = fdt_data_get((void *)(rangesptr+1), 1);
16902c7dba9SIan Lepore 
17002c7dba9SIan Lepore 		if (cell0 & 0x02000000) {
17102c7dba9SIan Lepore 			pci_space = mem_space;
17246db7283SMarcin Wojtas 			is_io_space = 0;
17302c7dba9SIan Lepore 		} else if (cell0 & 0x01000000) {
17402c7dba9SIan Lepore 			pci_space = io_space;
17546db7283SMarcin Wojtas 			is_io_space = 1;
17602c7dba9SIan Lepore 		} else {
17702c7dba9SIan Lepore 			rv = ERANGE;
17802c7dba9SIan Lepore 			goto out;
17902c7dba9SIan Lepore 		}
18002c7dba9SIan Lepore 
18102c7dba9SIan Lepore 		if (par_addr_cells == 3) {
18202c7dba9SIan Lepore 			/*
18302c7dba9SIan Lepore 			 * This is a PCI subnode 'ranges'. Skip cell0 and
18402c7dba9SIan Lepore 			 * cell1 of this entry and only use cell2.
18502c7dba9SIan Lepore 			 */
18602c7dba9SIan Lepore 			offset_cells = 2;
18702c7dba9SIan Lepore 			rangesptr += offset_cells;
18802c7dba9SIan Lepore 		}
18902c7dba9SIan Lepore 
1901f7f3314SRuslan Bukin 		if ((par_addr_cells - offset_cells) > 2) {
19102c7dba9SIan Lepore 			rv = ERANGE;
19202c7dba9SIan Lepore 			goto out;
19302c7dba9SIan Lepore 		}
19402c7dba9SIan Lepore 		pci_space->base_parent = fdt_data_get((void *)rangesptr,
19502c7dba9SIan Lepore 		    par_addr_cells - offset_cells);
19602c7dba9SIan Lepore 		rangesptr += par_addr_cells - offset_cells;
19702c7dba9SIan Lepore 
198dd279f7aSRuslan Bukin 		if (size_cells > 2) {
19902c7dba9SIan Lepore 			rv = ERANGE;
20002c7dba9SIan Lepore 			goto out;
20102c7dba9SIan Lepore 		}
20202c7dba9SIan Lepore 		pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
20302c7dba9SIan Lepore 		rangesptr += size_cells;
20402c7dba9SIan Lepore 
20502c7dba9SIan Lepore 		pci_space->base_pci = cell2;
20646db7283SMarcin Wojtas 
20746db7283SMarcin Wojtas 		if (pci_space->len == 0) {
20846db7283SMarcin Wojtas 			pci_space->len = PCI_SPACE_LEN;
20946db7283SMarcin Wojtas 			pci_space->base_parent = fdt_immr_va +
21046db7283SMarcin Wojtas 			    PCI_SPACE_LEN * ( 2 * portid + is_io_space);
21146db7283SMarcin Wojtas 		}
21202c7dba9SIan Lepore 	}
21302c7dba9SIan Lepore 	rv = 0;
21402c7dba9SIan Lepore out:
21502c7dba9SIan Lepore 	return (rv);
21602c7dba9SIan Lepore }
21702c7dba9SIan Lepore 
21802c7dba9SIan Lepore static int
21902c7dba9SIan Lepore mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
22002c7dba9SIan Lepore     struct mv_pci_range *mem_space)
22102c7dba9SIan Lepore {
22202c7dba9SIan Lepore 	int err;
22302c7dba9SIan Lepore 
22402c7dba9SIan Lepore 	debugf("Processing PCI node: %x\n", node);
22502c7dba9SIan Lepore 	if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
22602c7dba9SIan Lepore 		debugf("could not decode parent PCI node 'ranges'\n");
22702c7dba9SIan Lepore 		return (err);
22802c7dba9SIan Lepore 	}
22902c7dba9SIan Lepore 
23002c7dba9SIan Lepore 	debugf("Post fixup dump:\n");
23102c7dba9SIan Lepore 	mv_pci_range_dump(io_space);
23202c7dba9SIan Lepore 	mv_pci_range_dump(mem_space);
23302c7dba9SIan Lepore 	return (0);
23402c7dba9SIan Lepore }
23502c7dba9SIan Lepore 
23602c7dba9SIan Lepore int
23730b72b68SRuslan Bukin mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
23802c7dba9SIan Lepore     vm_offset_t mem_va)
23902c7dba9SIan Lepore {
24002c7dba9SIan Lepore 	struct mv_pci_range io_space, mem_space;
24102c7dba9SIan Lepore 	int error;
24202c7dba9SIan Lepore 
24302c7dba9SIan Lepore 	if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
24402c7dba9SIan Lepore 		return (error);
24502c7dba9SIan Lepore 
24602c7dba9SIan Lepore 	devmap->pd_va = (io_va ? io_va : io_space.base_parent);
24702c7dba9SIan Lepore 	devmap->pd_pa = io_space.base_parent;
24802c7dba9SIan Lepore 	devmap->pd_size = io_space.len;
24902c7dba9SIan Lepore 	devmap++;
25002c7dba9SIan Lepore 
25102c7dba9SIan Lepore 	devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
25202c7dba9SIan Lepore 	devmap->pd_pa = mem_space.base_parent;
25302c7dba9SIan Lepore 	devmap->pd_size = mem_space.len;
25402c7dba9SIan Lepore 	return (0);
25502c7dba9SIan Lepore }
25602c7dba9SIan Lepore 
25702c7dba9SIan Lepore /*
25802c7dba9SIan Lepore  * Code and data related to the Marvell pcib driver.
25902c7dba9SIan Lepore  */
26002c7dba9SIan Lepore 
2617a22215cSEitan Adler #define PCI_CFG_ENA		(1U << 31)
2626975124cSRafal Jaworowski #define PCI_CFG_BUS(bus)	(((bus) & 0xff) << 16)
2636975124cSRafal Jaworowski #define PCI_CFG_DEV(dev)	(((dev) & 0x1f) << 11)
2646975124cSRafal Jaworowski #define PCI_CFG_FUN(fun)	(((fun) & 0x7) << 8)
2656975124cSRafal Jaworowski #define PCI_CFG_PCIE_REG(reg)	((reg) & 0xfc)
2666975124cSRafal Jaworowski 
2676975124cSRafal Jaworowski #define PCI_REG_CFG_ADDR	0x0C78
2686975124cSRafal Jaworowski #define PCI_REG_CFG_DATA	0x0C7C
2696975124cSRafal Jaworowski 
2706975124cSRafal Jaworowski #define PCIE_REG_CFG_ADDR	0x18F8
2716975124cSRafal Jaworowski #define PCIE_REG_CFG_DATA	0x18FC
2726975124cSRafal Jaworowski #define PCIE_REG_CONTROL	0x1A00
2736975124cSRafal Jaworowski #define   PCIE_CTRL_LINK1X	0x00000001
2746975124cSRafal Jaworowski #define PCIE_REG_STATUS		0x1A04
2756975124cSRafal Jaworowski #define PCIE_REG_IRQ_MASK	0x1910
2766975124cSRafal Jaworowski 
277e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_ROOT_CMPLX	(1 << 1)
278e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_HOT_RESET	(1 << 24)
2796975124cSRafal Jaworowski 
280e3ac9753SGrzegorz Bernacki #define PCIE_LINK_TIMEOUT	1000000
2816975124cSRafal Jaworowski 
282e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_LINK_DOWN	1
283e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_DEV_OFFS	16
284e3ac9753SGrzegorz Bernacki 
285e3ac9753SGrzegorz Bernacki /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
286e3ac9753SGrzegorz Bernacki #define PCI_MIN_IO_ALLOC	4
287e3ac9753SGrzegorz Bernacki #define PCI_MIN_MEM_ALLOC	16
288e3ac9753SGrzegorz Bernacki 
289e3ac9753SGrzegorz Bernacki #define BITS_PER_UINT32		(NBBY * sizeof(uint32_t))
2906975124cSRafal Jaworowski 
291db5ef4fcSRafal Jaworowski struct mv_pcib_softc {
2926975124cSRafal Jaworowski 	device_t	sc_dev;
2936975124cSRafal Jaworowski 
294db5ef4fcSRafal Jaworowski 	struct rman	sc_mem_rman;
295db5ef4fcSRafal Jaworowski 	bus_addr_t	sc_mem_base;
296db5ef4fcSRafal Jaworowski 	bus_addr_t	sc_mem_size;
297e3ac9753SGrzegorz Bernacki 	uint32_t	sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
298e3ac9753SGrzegorz Bernacki 	    (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
299e3ac9753SGrzegorz Bernacki 	int		sc_win_target;
300db5ef4fcSRafal Jaworowski 	int		sc_mem_win_attr;
3016975124cSRafal Jaworowski 
302db5ef4fcSRafal Jaworowski 	struct rman	sc_io_rman;
303db5ef4fcSRafal Jaworowski 	bus_addr_t	sc_io_base;
304db5ef4fcSRafal Jaworowski 	bus_addr_t	sc_io_size;
305e3ac9753SGrzegorz Bernacki 	uint32_t	sc_io_map[MV_PCI_IO_SLICE_SIZE /
306e3ac9753SGrzegorz Bernacki 	    (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
307db5ef4fcSRafal Jaworowski 	int		sc_io_win_attr;
3086975124cSRafal Jaworowski 
3096975124cSRafal Jaworowski 	struct resource	*sc_res;
3106975124cSRafal Jaworowski 	bus_space_handle_t sc_bsh;
3116975124cSRafal Jaworowski 	bus_space_tag_t	sc_bst;
3126975124cSRafal Jaworowski 	int		sc_rid;
3136975124cSRafal Jaworowski 
31464dc1cf3SGrzegorz Bernacki 	struct mtx	sc_msi_mtx;
31564dc1cf3SGrzegorz Bernacki 	uint32_t	sc_msi_bitmap;
31664dc1cf3SGrzegorz Bernacki 
3176975124cSRafal Jaworowski 	int		sc_busnr;		/* Host bridge bus number */
3186975124cSRafal Jaworowski 	int		sc_devnr;		/* Host bridge device number */
319db5ef4fcSRafal Jaworowski 	int		sc_type;
320e3ac9753SGrzegorz Bernacki 	int		sc_mode;		/* Endpoint / Root Complex */
3216975124cSRafal Jaworowski 
322fefc2cf7SMarcin Wojtas 	int		sc_msi_supported;
323fefc2cf7SMarcin Wojtas 	int		sc_skip_enable_procedure;
324fefc2cf7SMarcin Wojtas 	int		sc_enable_find_root_slot;
325c826a643SNathan Whitehorn 	struct ofw_bus_iinfo	sc_pci_iinfo;
3263a582d09SMarcin Wojtas 
3273a582d09SMarcin Wojtas 	int		ap_segment;		/* PCI domain */
3286975124cSRafal Jaworowski };
3296975124cSRafal Jaworowski 
330db5ef4fcSRafal Jaworowski /* Local forward prototypes */
331db5ef4fcSRafal Jaworowski static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
332db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfginit(void);
333db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
334db5ef4fcSRafal Jaworowski     u_int, u_int, int);
335db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
336db5ef4fcSRafal Jaworowski     u_int, u_int, uint32_t, int);
337db5ef4fcSRafal Jaworowski static int mv_pcib_init(struct mv_pcib_softc *, int, int);
338db5ef4fcSRafal Jaworowski static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
339db5ef4fcSRafal Jaworowski static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
340db5ef4fcSRafal Jaworowski static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
341e3ac9753SGrzegorz Bernacki static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
342e3ac9753SGrzegorz Bernacki static int mv_pcib_mem_init(struct mv_pcib_softc *);
343db5ef4fcSRafal Jaworowski 
344db5ef4fcSRafal Jaworowski /* Forward prototypes */
345db5ef4fcSRafal Jaworowski static int mv_pcib_probe(device_t);
346db5ef4fcSRafal Jaworowski static int mv_pcib_attach(device_t);
347db5ef4fcSRafal Jaworowski 
348db5ef4fcSRafal Jaworowski static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
3492dd1bdf1SJustin Hibbits     rman_res_t, rman_res_t, rman_res_t, u_int);
350db5ef4fcSRafal Jaworowski static int mv_pcib_release_resource(device_t, device_t, int, int,
3516975124cSRafal Jaworowski     struct resource *);
352db5ef4fcSRafal Jaworowski static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
353db5ef4fcSRafal Jaworowski static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
3546975124cSRafal Jaworowski 
355db5ef4fcSRafal Jaworowski static int mv_pcib_maxslots(device_t);
356db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
357db5ef4fcSRafal Jaworowski static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
3586975124cSRafal Jaworowski     uint32_t, int);
359db5ef4fcSRafal Jaworowski static int mv_pcib_route_interrupt(device_t, device_t, int);
360fefc2cf7SMarcin Wojtas 
36164dc1cf3SGrzegorz Bernacki static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
36264dc1cf3SGrzegorz Bernacki static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
36364dc1cf3SGrzegorz Bernacki static int mv_pcib_release_msi(device_t, device_t, int, int *);
3646975124cSRafal Jaworowski 
3656975124cSRafal Jaworowski /*
3666975124cSRafal Jaworowski  * Bus interface definitions.
3676975124cSRafal Jaworowski  */
368db5ef4fcSRafal Jaworowski static device_method_t mv_pcib_methods[] = {
3696975124cSRafal Jaworowski 	/* Device interface */
370db5ef4fcSRafal Jaworowski 	DEVMETHOD(device_probe,			mv_pcib_probe),
371db5ef4fcSRafal Jaworowski 	DEVMETHOD(device_attach,		mv_pcib_attach),
3726975124cSRafal Jaworowski 
3736975124cSRafal Jaworowski 	/* Bus interface */
374db5ef4fcSRafal Jaworowski 	DEVMETHOD(bus_read_ivar,		mv_pcib_read_ivar),
375db5ef4fcSRafal Jaworowski 	DEVMETHOD(bus_write_ivar,		mv_pcib_write_ivar),
376db5ef4fcSRafal Jaworowski 	DEVMETHOD(bus_alloc_resource,		mv_pcib_alloc_resource),
377db5ef4fcSRafal Jaworowski 	DEVMETHOD(bus_release_resource,		mv_pcib_release_resource),
3786975124cSRafal Jaworowski 	DEVMETHOD(bus_activate_resource,	bus_generic_activate_resource),
3796975124cSRafal Jaworowski 	DEVMETHOD(bus_deactivate_resource,	bus_generic_deactivate_resource),
3806975124cSRafal Jaworowski 	DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
3816975124cSRafal Jaworowski 	DEVMETHOD(bus_teardown_intr,		bus_generic_teardown_intr),
3826975124cSRafal Jaworowski 
3836975124cSRafal Jaworowski 	/* pcib interface */
384db5ef4fcSRafal Jaworowski 	DEVMETHOD(pcib_maxslots,		mv_pcib_maxslots),
385db5ef4fcSRafal Jaworowski 	DEVMETHOD(pcib_read_config,		mv_pcib_read_config),
386db5ef4fcSRafal Jaworowski 	DEVMETHOD(pcib_write_config,		mv_pcib_write_config),
387db5ef4fcSRafal Jaworowski 	DEVMETHOD(pcib_route_interrupt,		mv_pcib_route_interrupt),
38828586889SWarner Losh 	DEVMETHOD(pcib_request_feature,		pcib_request_feature_allow),
389fefc2cf7SMarcin Wojtas 
39064dc1cf3SGrzegorz Bernacki 	DEVMETHOD(pcib_alloc_msi,		mv_pcib_alloc_msi),
39164dc1cf3SGrzegorz Bernacki 	DEVMETHOD(pcib_release_msi,		mv_pcib_release_msi),
39264dc1cf3SGrzegorz Bernacki 	DEVMETHOD(pcib_map_msi,			mv_pcib_map_msi),
39364dc1cf3SGrzegorz Bernacki 
394db5ef4fcSRafal Jaworowski 	/* OFW bus interface */
395db5ef4fcSRafal Jaworowski 	DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
396db5ef4fcSRafal Jaworowski 	DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
397db5ef4fcSRafal Jaworowski 	DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
398db5ef4fcSRafal Jaworowski 	DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
399db5ef4fcSRafal Jaworowski 	DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
4006975124cSRafal Jaworowski 
4014b7ec270SMarius Strobl 	DEVMETHOD_END
4026975124cSRafal Jaworowski };
4036975124cSRafal Jaworowski 
404db5ef4fcSRafal Jaworowski static driver_t mv_pcib_driver = {
4056975124cSRafal Jaworowski 	"pcib",
406db5ef4fcSRafal Jaworowski 	mv_pcib_methods,
407db5ef4fcSRafal Jaworowski 	sizeof(struct mv_pcib_softc),
4086975124cSRafal Jaworowski };
4096975124cSRafal Jaworowski 
4106975124cSRafal Jaworowski devclass_t pcib_devclass;
4116975124cSRafal Jaworowski 
4125b2a48fbSEmmanuel Vadot DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
4135b2a48fbSEmmanuel Vadot DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
4146975124cSRafal Jaworowski 
4156975124cSRafal Jaworowski static struct mtx pcicfg_mtx;
4166975124cSRafal Jaworowski 
417db5ef4fcSRafal Jaworowski static int
418db5ef4fcSRafal Jaworowski mv_pcib_probe(device_t self)
4196975124cSRafal Jaworowski {
4201b96faf8SMarcel Moolenaar 	phandle_t node;
4216975124cSRafal Jaworowski 
4221b96faf8SMarcel Moolenaar 	node = ofw_bus_get_node(self);
423626a1983SAndrew Turner 	if (!mv_fdt_is_type(node, "pci"))
424db5ef4fcSRafal Jaworowski 		return (ENXIO);
4251b96faf8SMarcel Moolenaar 
426c826a643SNathan Whitehorn 	if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
427c7dbc00cSMarcin Wojtas 	    ofw_bus_is_compatible(self, "mrvl,pci") ||
428c7dbc00cSMarcin Wojtas 	    ofw_bus_node_is_compatible(
429c7dbc00cSMarcin Wojtas 	    OF_parent(node), "marvell,armada-370-pcie")))
430db5ef4fcSRafal Jaworowski 		return (ENXIO);
4316975124cSRafal Jaworowski 
432afffcaa1SOleksandr Tymoshenko 	if (!ofw_bus_status_okay(self))
433afffcaa1SOleksandr Tymoshenko 		return (ENXIO);
434afffcaa1SOleksandr Tymoshenko 
435db5ef4fcSRafal Jaworowski 	device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
436db5ef4fcSRafal Jaworowski 	return (BUS_PROBE_DEFAULT);
437db5ef4fcSRafal Jaworowski }
438db5ef4fcSRafal Jaworowski 
439db5ef4fcSRafal Jaworowski static int
440db5ef4fcSRafal Jaworowski mv_pcib_attach(device_t self)
441db5ef4fcSRafal Jaworowski {
442db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc;
443db5ef4fcSRafal Jaworowski 	phandle_t node, parnode;
44485958649SZbigniew Bodek 	uint32_t val, reg0;
44585958649SZbigniew Bodek 	int err, bus, devfn, port_id;
446db5ef4fcSRafal Jaworowski 
447db5ef4fcSRafal Jaworowski 	sc = device_get_softc(self);
448db5ef4fcSRafal Jaworowski 	sc->sc_dev = self;
449db5ef4fcSRafal Jaworowski 
4501b96faf8SMarcel Moolenaar 	node = ofw_bus_get_node(self);
4511b96faf8SMarcel Moolenaar 	parnode = OF_parent(node);
45285958649SZbigniew Bodek 
45385958649SZbigniew Bodek 	if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
45485958649SZbigniew Bodek 	    sizeof(port_id)) <= 0) {
45585958649SZbigniew Bodek 		/* If port ID does not exist in the FDT set value to 0 */
45685958649SZbigniew Bodek 		if (!OF_hasprop(node, "marvell,pcie-port"))
45785958649SZbigniew Bodek 			port_id = 0;
45885958649SZbigniew Bodek 		else
45985958649SZbigniew Bodek 			return(ENXIO);
46085958649SZbigniew Bodek 	}
46185958649SZbigniew Bodek 
4623a582d09SMarcin Wojtas 	sc->ap_segment = port_id;
4633a582d09SMarcin Wojtas 
46487acb7f8SAndrew Turner 	if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
465db5ef4fcSRafal Jaworowski 		sc->sc_type = MV_TYPE_PCIE;
46685958649SZbigniew Bodek 		sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
46785958649SZbigniew Bodek 		sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
46885958649SZbigniew Bodek 		sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
469fefc2cf7SMarcin Wojtas 		sc->sc_skip_enable_procedure = 1;
470c7dbc00cSMarcin Wojtas 	} else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
471c7dbc00cSMarcin Wojtas 		sc->sc_type = MV_TYPE_PCIE;
472c7dbc00cSMarcin Wojtas 		sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
473c7dbc00cSMarcin Wojtas 		sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
474c7dbc00cSMarcin Wojtas 		sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
475c7dbc00cSMarcin Wojtas 		sc->sc_enable_find_root_slot = 1;
47687acb7f8SAndrew Turner 	} else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
477db5ef4fcSRafal Jaworowski 		sc->sc_type = MV_TYPE_PCI;
478e3ac9753SGrzegorz Bernacki 		sc->sc_win_target = MV_WIN_PCI_TARGET;
479db5ef4fcSRafal Jaworowski 		sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
480db5ef4fcSRafal Jaworowski 		sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
481db5ef4fcSRafal Jaworowski 	} else
482db5ef4fcSRafal Jaworowski 		return (ENXIO);
483db5ef4fcSRafal Jaworowski 
484db5ef4fcSRafal Jaworowski 	/*
485db5ef4fcSRafal Jaworowski 	 * Retrieve our mem-mapped registers range.
486db5ef4fcSRafal Jaworowski 	 */
487db5ef4fcSRafal Jaworowski 	sc->sc_rid = 0;
488db5ef4fcSRafal Jaworowski 	sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
489db5ef4fcSRafal Jaworowski 	    RF_ACTIVE);
490db5ef4fcSRafal Jaworowski 	if (sc->sc_res == NULL) {
491db5ef4fcSRafal Jaworowski 		device_printf(self, "could not map memory\n");
492db5ef4fcSRafal Jaworowski 		return (ENXIO);
493db5ef4fcSRafal Jaworowski 	}
494db5ef4fcSRafal Jaworowski 	sc->sc_bst = rman_get_bustag(sc->sc_res);
495db5ef4fcSRafal Jaworowski 	sc->sc_bsh = rman_get_bushandle(sc->sc_res);
496db5ef4fcSRafal Jaworowski 
497e3ac9753SGrzegorz Bernacki 	val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
498e3ac9753SGrzegorz Bernacki 	sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
499e3ac9753SGrzegorz Bernacki 	    MV_MODE_ENDPOINT);
500e3ac9753SGrzegorz Bernacki 
501e3ac9753SGrzegorz Bernacki 	/*
502e3ac9753SGrzegorz Bernacki 	 * Get PCI interrupt info.
503e3ac9753SGrzegorz Bernacki 	 */
504c826a643SNathan Whitehorn 	if (sc->sc_mode == MV_MODE_ROOT)
505c826a643SNathan Whitehorn 		ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
506e3ac9753SGrzegorz Bernacki 
507db5ef4fcSRafal Jaworowski 	/*
508db5ef4fcSRafal Jaworowski 	 * Configure decode windows for PCI(E) access.
509db5ef4fcSRafal Jaworowski 	 */
510db5ef4fcSRafal Jaworowski 	if (mv_pcib_decode_win(node, sc) != 0)
511db5ef4fcSRafal Jaworowski 		return (ENXIO);
512db5ef4fcSRafal Jaworowski 
513db5ef4fcSRafal Jaworowski 	mv_pcib_hw_cfginit();
514db5ef4fcSRafal Jaworowski 
515db5ef4fcSRafal Jaworowski 	/*
516e3ac9753SGrzegorz Bernacki 	 * Enable PCIE device.
517e3ac9753SGrzegorz Bernacki 	 */
51885958649SZbigniew Bodek 	mv_pcib_enable(sc, port_id);
519e3ac9753SGrzegorz Bernacki 
520e3ac9753SGrzegorz Bernacki 	/*
521e3ac9753SGrzegorz Bernacki 	 * Memory management.
522e3ac9753SGrzegorz Bernacki 	 */
523e3ac9753SGrzegorz Bernacki 	err = mv_pcib_mem_init(sc);
524e3ac9753SGrzegorz Bernacki 	if (err)
525e3ac9753SGrzegorz Bernacki 		return (err);
526e3ac9753SGrzegorz Bernacki 
52785958649SZbigniew Bodek 	/*
52885958649SZbigniew Bodek 	 * Preliminary bus enumeration to find first linked devices and set
52985958649SZbigniew Bodek 	 * appropriate bus number from which should start the actual enumeration
53085958649SZbigniew Bodek 	 */
53185958649SZbigniew Bodek 	for (bus = 0; bus < PCI_BUSMAX; bus++) {
53285958649SZbigniew Bodek 		for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
53385958649SZbigniew Bodek 			reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
53485958649SZbigniew Bodek 			if (reg0 == (~0U))
53585958649SZbigniew Bodek 				continue; /* no device */
53685958649SZbigniew Bodek 			else {
53785958649SZbigniew Bodek 				sc->sc_busnr = bus; /* update bus number */
53885958649SZbigniew Bodek 				break;
53985958649SZbigniew Bodek 			}
54085958649SZbigniew Bodek 		}
54185958649SZbigniew Bodek 	}
54285958649SZbigniew Bodek 
543e3ac9753SGrzegorz Bernacki 	if (sc->sc_mode == MV_MODE_ROOT) {
544e3ac9753SGrzegorz Bernacki 		err = mv_pcib_init(sc, sc->sc_busnr,
545e3ac9753SGrzegorz Bernacki 		    mv_pcib_maxslots(sc->sc_dev));
546e3ac9753SGrzegorz Bernacki 		if (err)
547e3ac9753SGrzegorz Bernacki 			goto error;
548e3ac9753SGrzegorz Bernacki 
549e3ac9753SGrzegorz Bernacki 		device_add_child(self, "pci", -1);
550e3ac9753SGrzegorz Bernacki 	} else {
551e3ac9753SGrzegorz Bernacki 		sc->sc_devnr = 1;
552e3ac9753SGrzegorz Bernacki 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
553e3ac9753SGrzegorz Bernacki 		    PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
554e3ac9753SGrzegorz Bernacki 		device_add_child(self, "pci_ep", -1);
555e3ac9753SGrzegorz Bernacki 	}
556e3ac9753SGrzegorz Bernacki 
55764dc1cf3SGrzegorz Bernacki 	mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
558e3ac9753SGrzegorz Bernacki 	return (bus_generic_attach(self));
559e3ac9753SGrzegorz Bernacki 
560e3ac9753SGrzegorz Bernacki error:
561e3ac9753SGrzegorz Bernacki 	/* XXX SYS_RES_ should be released here */
562e3ac9753SGrzegorz Bernacki 	rman_fini(&sc->sc_mem_rman);
563e3ac9753SGrzegorz Bernacki 	rman_fini(&sc->sc_io_rman);
564e3ac9753SGrzegorz Bernacki 
565e3ac9753SGrzegorz Bernacki 	return (err);
566e3ac9753SGrzegorz Bernacki }
567e3ac9753SGrzegorz Bernacki 
568e3ac9753SGrzegorz Bernacki static void
569e3ac9753SGrzegorz Bernacki mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
570e3ac9753SGrzegorz Bernacki {
571e3ac9753SGrzegorz Bernacki 	uint32_t val;
572e3ac9753SGrzegorz Bernacki 	int timeout;
573e3ac9753SGrzegorz Bernacki 
574fefc2cf7SMarcin Wojtas 	if (sc->sc_skip_enable_procedure)
575fefc2cf7SMarcin Wojtas 		goto pcib_enable_root_mode;
576fefc2cf7SMarcin Wojtas 
577e3ac9753SGrzegorz Bernacki 	/*
578e3ac9753SGrzegorz Bernacki 	 * Check if PCIE device is enabled.
579e3ac9753SGrzegorz Bernacki 	 */
5804b1bfa3fSMarcin Wojtas 	if ((sc->sc_skip_enable_procedure == 0) &&
5814b1bfa3fSMarcin Wojtas 	    (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {
582e3ac9753SGrzegorz Bernacki 		write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
583e3ac9753SGrzegorz Bernacki 		    ~(CPU_CONTROL_PCIE_DISABLE(unit)));
584e3ac9753SGrzegorz Bernacki 
585e3ac9753SGrzegorz Bernacki 		timeout = PCIE_LINK_TIMEOUT;
586e3ac9753SGrzegorz Bernacki 		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
587e3ac9753SGrzegorz Bernacki 		    PCIE_REG_STATUS);
588e3ac9753SGrzegorz Bernacki 		while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
589e3ac9753SGrzegorz Bernacki 			DELAY(1000);
590e3ac9753SGrzegorz Bernacki 			timeout -= 1000;
591e3ac9753SGrzegorz Bernacki 			val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
592e3ac9753SGrzegorz Bernacki 			    PCIE_REG_STATUS);
593e3ac9753SGrzegorz Bernacki 		}
594e3ac9753SGrzegorz Bernacki 	}
595e3ac9753SGrzegorz Bernacki 
596fefc2cf7SMarcin Wojtas pcib_enable_root_mode:
597e3ac9753SGrzegorz Bernacki 	if (sc->sc_mode == MV_MODE_ROOT) {
598e3ac9753SGrzegorz Bernacki 		/*
599db5ef4fcSRafal Jaworowski 		 * Enable PCI bridge.
600db5ef4fcSRafal Jaworowski 		 */
601e3ac9753SGrzegorz Bernacki 		val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
602e3ac9753SGrzegorz Bernacki 		val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
603e3ac9753SGrzegorz Bernacki 		    PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
604e3ac9753SGrzegorz Bernacki 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
605e3ac9753SGrzegorz Bernacki 	}
606e3ac9753SGrzegorz Bernacki }
607db5ef4fcSRafal Jaworowski 
608e3ac9753SGrzegorz Bernacki static int
609e3ac9753SGrzegorz Bernacki mv_pcib_mem_init(struct mv_pcib_softc *sc)
610e3ac9753SGrzegorz Bernacki {
611e3ac9753SGrzegorz Bernacki 	int err;
612db5ef4fcSRafal Jaworowski 
613e3ac9753SGrzegorz Bernacki 	/*
614e3ac9753SGrzegorz Bernacki 	 * Memory management.
615e3ac9753SGrzegorz Bernacki 	 */
616db5ef4fcSRafal Jaworowski 	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
617db5ef4fcSRafal Jaworowski 	err = rman_init(&sc->sc_mem_rman);
618db5ef4fcSRafal Jaworowski 	if (err)
619db5ef4fcSRafal Jaworowski 		return (err);
620db5ef4fcSRafal Jaworowski 
621db5ef4fcSRafal Jaworowski 	sc->sc_io_rman.rm_type = RMAN_ARRAY;
622db5ef4fcSRafal Jaworowski 	err = rman_init(&sc->sc_io_rman);
623db5ef4fcSRafal Jaworowski 	if (err) {
624db5ef4fcSRafal Jaworowski 		rman_fini(&sc->sc_mem_rman);
625db5ef4fcSRafal Jaworowski 		return (err);
626db5ef4fcSRafal Jaworowski 	}
627db5ef4fcSRafal Jaworowski 
628db5ef4fcSRafal Jaworowski 	err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
629db5ef4fcSRafal Jaworowski 	    sc->sc_mem_base + sc->sc_mem_size - 1);
630db5ef4fcSRafal Jaworowski 	if (err)
631db5ef4fcSRafal Jaworowski 		goto error;
632db5ef4fcSRafal Jaworowski 
633db5ef4fcSRafal Jaworowski 	err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
634db5ef4fcSRafal Jaworowski 	    sc->sc_io_base + sc->sc_io_size - 1);
635db5ef4fcSRafal Jaworowski 	if (err)
636db5ef4fcSRafal Jaworowski 		goto error;
637db5ef4fcSRafal Jaworowski 
638e3ac9753SGrzegorz Bernacki 	return (0);
639db5ef4fcSRafal Jaworowski 
640db5ef4fcSRafal Jaworowski error:
641db5ef4fcSRafal Jaworowski 	rman_fini(&sc->sc_mem_rman);
642db5ef4fcSRafal Jaworowski 	rman_fini(&sc->sc_io_rman);
643e3ac9753SGrzegorz Bernacki 
644db5ef4fcSRafal Jaworowski 	return (err);
645db5ef4fcSRafal Jaworowski }
646db5ef4fcSRafal Jaworowski 
647e3ac9753SGrzegorz Bernacki static inline uint32_t
648e3ac9753SGrzegorz Bernacki pcib_bit_get(uint32_t *map, uint32_t bit)
649e3ac9753SGrzegorz Bernacki {
650e3ac9753SGrzegorz Bernacki 	uint32_t n = bit / BITS_PER_UINT32;
651e3ac9753SGrzegorz Bernacki 
652e3ac9753SGrzegorz Bernacki 	bit = bit % BITS_PER_UINT32;
653e3ac9753SGrzegorz Bernacki 	return (map[n] & (1 << bit));
654e3ac9753SGrzegorz Bernacki }
655e3ac9753SGrzegorz Bernacki 
656e3ac9753SGrzegorz Bernacki static inline void
657e3ac9753SGrzegorz Bernacki pcib_bit_set(uint32_t *map, uint32_t bit)
658e3ac9753SGrzegorz Bernacki {
659e3ac9753SGrzegorz Bernacki 	uint32_t n = bit / BITS_PER_UINT32;
660e3ac9753SGrzegorz Bernacki 
661e3ac9753SGrzegorz Bernacki 	bit = bit % BITS_PER_UINT32;
662e3ac9753SGrzegorz Bernacki 	map[n] |= (1 << bit);
663e3ac9753SGrzegorz Bernacki }
664e3ac9753SGrzegorz Bernacki 
665e3ac9753SGrzegorz Bernacki static inline uint32_t
666e3ac9753SGrzegorz Bernacki pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
667e3ac9753SGrzegorz Bernacki {
668e3ac9753SGrzegorz Bernacki 	uint32_t i;
669e3ac9753SGrzegorz Bernacki 
670e3ac9753SGrzegorz Bernacki 	for (i = start; i < start + bits; i++)
671e3ac9753SGrzegorz Bernacki 		if (pcib_bit_get(map, i))
672e3ac9753SGrzegorz Bernacki 			return (0);
673e3ac9753SGrzegorz Bernacki 
674e3ac9753SGrzegorz Bernacki 	return (1);
675e3ac9753SGrzegorz Bernacki }
676e3ac9753SGrzegorz Bernacki 
677e3ac9753SGrzegorz Bernacki static inline void
678e3ac9753SGrzegorz Bernacki pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
679e3ac9753SGrzegorz Bernacki {
680e3ac9753SGrzegorz Bernacki 	uint32_t i;
681e3ac9753SGrzegorz Bernacki 
682e3ac9753SGrzegorz Bernacki 	for (i = start; i < start + bits; i++)
683e3ac9753SGrzegorz Bernacki 		pcib_bit_set(map, i);
684e3ac9753SGrzegorz Bernacki }
685e3ac9753SGrzegorz Bernacki 
686e3ac9753SGrzegorz Bernacki /*
687e3ac9753SGrzegorz Bernacki  * The idea of this allocator is taken from ARM No-Cache memory
688e3ac9753SGrzegorz Bernacki  * management code (sys/arm/arm/vm_machdep.c).
689e3ac9753SGrzegorz Bernacki  */
690e3ac9753SGrzegorz Bernacki static bus_addr_t
691e3ac9753SGrzegorz Bernacki pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
692e3ac9753SGrzegorz Bernacki {
693e3ac9753SGrzegorz Bernacki 	uint32_t bits, bits_limit, i, *map, min_alloc, size;
694e3ac9753SGrzegorz Bernacki 	bus_addr_t addr = 0;
695e3ac9753SGrzegorz Bernacki 	bus_addr_t base;
696e3ac9753SGrzegorz Bernacki 
697e3ac9753SGrzegorz Bernacki 	if (smask & 1) {
698e3ac9753SGrzegorz Bernacki 		base = sc->sc_io_base;
699e3ac9753SGrzegorz Bernacki 		min_alloc = PCI_MIN_IO_ALLOC;
700e3ac9753SGrzegorz Bernacki 		bits_limit = sc->sc_io_size / min_alloc;
701e3ac9753SGrzegorz Bernacki 		map = sc->sc_io_map;
702e3ac9753SGrzegorz Bernacki 		smask &= ~0x3;
703e3ac9753SGrzegorz Bernacki 	} else {
704e3ac9753SGrzegorz Bernacki 		base = sc->sc_mem_base;
705e3ac9753SGrzegorz Bernacki 		min_alloc = PCI_MIN_MEM_ALLOC;
706e3ac9753SGrzegorz Bernacki 		bits_limit = sc->sc_mem_size / min_alloc;
707e3ac9753SGrzegorz Bernacki 		map = sc->sc_mem_map;
708e3ac9753SGrzegorz Bernacki 		smask &= ~0xF;
709e3ac9753SGrzegorz Bernacki 	}
710e3ac9753SGrzegorz Bernacki 
711e3ac9753SGrzegorz Bernacki 	size = ~smask + 1;
712e3ac9753SGrzegorz Bernacki 	bits = size / min_alloc;
713e3ac9753SGrzegorz Bernacki 
714e3ac9753SGrzegorz Bernacki 	for (i = 0; i + bits <= bits_limit; i += bits)
715e3ac9753SGrzegorz Bernacki 		if (pcib_map_check(map, i, bits)) {
716e3ac9753SGrzegorz Bernacki 			pcib_map_set(map, i, bits);
717e3ac9753SGrzegorz Bernacki 			addr = base + (i * min_alloc);
718e3ac9753SGrzegorz Bernacki 			return (addr);
719e3ac9753SGrzegorz Bernacki 		}
720e3ac9753SGrzegorz Bernacki 
721e3ac9753SGrzegorz Bernacki 	return (addr);
722e3ac9753SGrzegorz Bernacki }
723e3ac9753SGrzegorz Bernacki 
724db5ef4fcSRafal Jaworowski static int
725db5ef4fcSRafal Jaworowski mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
726db5ef4fcSRafal Jaworowski     int barno)
727db5ef4fcSRafal Jaworowski {
728e3ac9753SGrzegorz Bernacki 	uint32_t addr, bar;
729db5ef4fcSRafal Jaworowski 	int reg, width;
730db5ef4fcSRafal Jaworowski 
731db5ef4fcSRafal Jaworowski 	reg = PCIR_BAR(barno);
732e3ac9753SGrzegorz Bernacki 
733e3ac9753SGrzegorz Bernacki 	/*
734e3ac9753SGrzegorz Bernacki 	 * Need to init the BAR register with 0xffffffff before correct
735e3ac9753SGrzegorz Bernacki 	 * value can be read.
736e3ac9753SGrzegorz Bernacki 	 */
737e3ac9753SGrzegorz Bernacki 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
738db5ef4fcSRafal Jaworowski 	bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
739db5ef4fcSRafal Jaworowski 	if (bar == 0)
740db5ef4fcSRafal Jaworowski 		return (1);
741db5ef4fcSRafal Jaworowski 
742db5ef4fcSRafal Jaworowski 	/* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
743db5ef4fcSRafal Jaworowski 	width = ((bar & 7) == 4) ? 2 : 1;
744db5ef4fcSRafal Jaworowski 
745e3ac9753SGrzegorz Bernacki 	addr = pcib_alloc(sc, bar);
746e3ac9753SGrzegorz Bernacki 	if (!addr)
747db5ef4fcSRafal Jaworowski 		return (-1);
748db5ef4fcSRafal Jaworowski 
749db5ef4fcSRafal Jaworowski 	if (bootverbose)
750e3ac9753SGrzegorz Bernacki 		printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
751e3ac9753SGrzegorz Bernacki 		    bus, slot, func, reg, bar, addr);
752db5ef4fcSRafal Jaworowski 
753db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
754db5ef4fcSRafal Jaworowski 	if (width == 2)
755db5ef4fcSRafal Jaworowski 		mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
756db5ef4fcSRafal Jaworowski 		    0, 4);
757db5ef4fcSRafal Jaworowski 
758db5ef4fcSRafal Jaworowski 	return (width);
7596975124cSRafal Jaworowski }
7606975124cSRafal Jaworowski 
7616975124cSRafal Jaworowski static void
762db5ef4fcSRafal Jaworowski mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
763db5ef4fcSRafal Jaworowski {
764db5ef4fcSRafal Jaworowski 	bus_addr_t io_base, mem_base;
765db5ef4fcSRafal Jaworowski 	uint32_t io_limit, mem_limit;
766db5ef4fcSRafal Jaworowski 	int secbus;
767db5ef4fcSRafal Jaworowski 
768db5ef4fcSRafal Jaworowski 	io_base = sc->sc_io_base;
769db5ef4fcSRafal Jaworowski 	io_limit = io_base + sc->sc_io_size - 1;
770db5ef4fcSRafal Jaworowski 	mem_base = sc->sc_mem_base;
771db5ef4fcSRafal Jaworowski 	mem_limit = mem_base + sc->sc_mem_size - 1;
772db5ef4fcSRafal Jaworowski 
773db5ef4fcSRafal Jaworowski 	/* Configure I/O decode registers */
774db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
775db5ef4fcSRafal Jaworowski 	    io_base >> 8, 1);
776db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
777db5ef4fcSRafal Jaworowski 	    io_base >> 16, 2);
778db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
779db5ef4fcSRafal Jaworowski 	    io_limit >> 8, 1);
780db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
781db5ef4fcSRafal Jaworowski 	    io_limit >> 16, 2);
782db5ef4fcSRafal Jaworowski 
783db5ef4fcSRafal Jaworowski 	/* Configure memory decode registers */
784db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
785db5ef4fcSRafal Jaworowski 	    mem_base >> 16, 2);
786db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
787db5ef4fcSRafal Jaworowski 	    mem_limit >> 16, 2);
788db5ef4fcSRafal Jaworowski 
789db5ef4fcSRafal Jaworowski 	/* Disable memory prefetch decode */
790db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
791db5ef4fcSRafal Jaworowski 	    0x10, 2);
792db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
793db5ef4fcSRafal Jaworowski 	    0x0, 4);
794db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
795db5ef4fcSRafal Jaworowski 	    0xF, 2);
796db5ef4fcSRafal Jaworowski 	mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
797db5ef4fcSRafal Jaworowski 	    0x0, 4);
798db5ef4fcSRafal Jaworowski 
799db5ef4fcSRafal Jaworowski 	secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
800db5ef4fcSRafal Jaworowski 	    PCIR_SECBUS_1, 1);
801db5ef4fcSRafal Jaworowski 
802db5ef4fcSRafal Jaworowski 	/* Configure buses behind the bridge */
803db5ef4fcSRafal Jaworowski 	mv_pcib_init(sc, secbus, PCI_SLOTMAX);
804db5ef4fcSRafal Jaworowski }
805db5ef4fcSRafal Jaworowski 
806db5ef4fcSRafal Jaworowski static int
807db5ef4fcSRafal Jaworowski mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
808db5ef4fcSRafal Jaworowski {
809db5ef4fcSRafal Jaworowski 	int slot, func, maxfunc, error;
810db5ef4fcSRafal Jaworowski 	uint8_t hdrtype, command, class, subclass;
811db5ef4fcSRafal Jaworowski 
812db5ef4fcSRafal Jaworowski 	for (slot = 0; slot <= maxslot; slot++) {
813db5ef4fcSRafal Jaworowski 		maxfunc = 0;
814db5ef4fcSRafal Jaworowski 		for (func = 0; func <= maxfunc; func++) {
815db5ef4fcSRafal Jaworowski 			hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
816db5ef4fcSRafal Jaworowski 			    func, PCIR_HDRTYPE, 1);
817db5ef4fcSRafal Jaworowski 
818db5ef4fcSRafal Jaworowski 			if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
819db5ef4fcSRafal Jaworowski 				continue;
820db5ef4fcSRafal Jaworowski 
821db5ef4fcSRafal Jaworowski 			if (func == 0 && (hdrtype & PCIM_MFDEV))
822db5ef4fcSRafal Jaworowski 				maxfunc = PCI_FUNCMAX;
823db5ef4fcSRafal Jaworowski 
824db5ef4fcSRafal Jaworowski 			command = mv_pcib_read_config(sc->sc_dev, bus, slot,
825db5ef4fcSRafal Jaworowski 			    func, PCIR_COMMAND, 1);
826db5ef4fcSRafal Jaworowski 			command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
827db5ef4fcSRafal Jaworowski 			mv_pcib_write_config(sc->sc_dev, bus, slot, func,
828db5ef4fcSRafal Jaworowski 			    PCIR_COMMAND, command, 1);
829db5ef4fcSRafal Jaworowski 
830db5ef4fcSRafal Jaworowski 			error = mv_pcib_init_all_bars(sc, bus, slot, func,
831db5ef4fcSRafal Jaworowski 			    hdrtype);
832db5ef4fcSRafal Jaworowski 
833db5ef4fcSRafal Jaworowski 			if (error)
834db5ef4fcSRafal Jaworowski 				return (error);
835db5ef4fcSRafal Jaworowski 
836db5ef4fcSRafal Jaworowski 			command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
837db5ef4fcSRafal Jaworowski 			    PCIM_CMD_PORTEN;
838db5ef4fcSRafal Jaworowski 			mv_pcib_write_config(sc->sc_dev, bus, slot, func,
839db5ef4fcSRafal Jaworowski 			    PCIR_COMMAND, command, 1);
840db5ef4fcSRafal Jaworowski 
841db5ef4fcSRafal Jaworowski 			/* Handle PCI-PCI bridges */
842db5ef4fcSRafal Jaworowski 			class = mv_pcib_read_config(sc->sc_dev, bus, slot,
843db5ef4fcSRafal Jaworowski 			    func, PCIR_CLASS, 1);
844db5ef4fcSRafal Jaworowski 			subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
845db5ef4fcSRafal Jaworowski 			    func, PCIR_SUBCLASS, 1);
846db5ef4fcSRafal Jaworowski 
847db5ef4fcSRafal Jaworowski 			if (class != PCIC_BRIDGE ||
848db5ef4fcSRafal Jaworowski 			    subclass != PCIS_BRIDGE_PCI)
849db5ef4fcSRafal Jaworowski 				continue;
850db5ef4fcSRafal Jaworowski 
851db5ef4fcSRafal Jaworowski 			mv_pcib_init_bridge(sc, bus, slot, func);
852db5ef4fcSRafal Jaworowski 		}
853db5ef4fcSRafal Jaworowski 	}
854db5ef4fcSRafal Jaworowski 
855db5ef4fcSRafal Jaworowski 	/* Enable all ABCD interrupts */
856db5ef4fcSRafal Jaworowski 	pcib_write_irq_mask(sc, (0xF << 24));
857db5ef4fcSRafal Jaworowski 
858db5ef4fcSRafal Jaworowski 	return (0);
859db5ef4fcSRafal Jaworowski }
860db5ef4fcSRafal Jaworowski 
861db5ef4fcSRafal Jaworowski static int
862db5ef4fcSRafal Jaworowski mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
863db5ef4fcSRafal Jaworowski     int func, int hdrtype)
864db5ef4fcSRafal Jaworowski {
865db5ef4fcSRafal Jaworowski 	int maxbar, bar, i;
866db5ef4fcSRafal Jaworowski 
867db5ef4fcSRafal Jaworowski 	maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
868db5ef4fcSRafal Jaworowski 	bar = 0;
869db5ef4fcSRafal Jaworowski 
870db5ef4fcSRafal Jaworowski 	/* Program the base address registers */
871db5ef4fcSRafal Jaworowski 	while (bar < maxbar) {
872db5ef4fcSRafal Jaworowski 		i = mv_pcib_init_bar(sc, bus, slot, func, bar);
873db5ef4fcSRafal Jaworowski 		bar += i;
874db5ef4fcSRafal Jaworowski 		if (i < 0) {
875db5ef4fcSRafal Jaworowski 			device_printf(sc->sc_dev,
876db5ef4fcSRafal Jaworowski 			    "PCI IO/Memory space exhausted\n");
877db5ef4fcSRafal Jaworowski 			return (ENOMEM);
878db5ef4fcSRafal Jaworowski 		}
879db5ef4fcSRafal Jaworowski 	}
880db5ef4fcSRafal Jaworowski 
881db5ef4fcSRafal Jaworowski 	return (0);
882db5ef4fcSRafal Jaworowski }
883db5ef4fcSRafal Jaworowski 
884db5ef4fcSRafal Jaworowski static struct resource *
885db5ef4fcSRafal Jaworowski mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
8862dd1bdf1SJustin Hibbits     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
887db5ef4fcSRafal Jaworowski {
888db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
889db5ef4fcSRafal Jaworowski 	struct rman *rm = NULL;
890db5ef4fcSRafal Jaworowski 	struct resource *res;
891db5ef4fcSRafal Jaworowski 
892db5ef4fcSRafal Jaworowski 	switch (type) {
893db5ef4fcSRafal Jaworowski 	case SYS_RES_IOPORT:
894db5ef4fcSRafal Jaworowski 		rm = &sc->sc_io_rman;
895db5ef4fcSRafal Jaworowski 		break;
896db5ef4fcSRafal Jaworowski 	case SYS_RES_MEMORY:
897db5ef4fcSRafal Jaworowski 		rm = &sc->sc_mem_rman;
898db5ef4fcSRafal Jaworowski 		break;
8993a582d09SMarcin Wojtas #ifdef PCI_RES_BUS
9003a582d09SMarcin Wojtas 	case PCI_RES_BUS:
9013a582d09SMarcin Wojtas 		return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
9023a582d09SMarcin Wojtas 		    end, count, flags));
9033a582d09SMarcin Wojtas #endif
904db5ef4fcSRafal Jaworowski 	default:
905e3ac9753SGrzegorz Bernacki 		return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
906db5ef4fcSRafal Jaworowski 		    type, rid, start, end, count, flags));
90774b8d63dSPedro F. Giffuni 	}
908db5ef4fcSRafal Jaworowski 
9097915adb5SJustin Hibbits 	if (RMAN_IS_DEFAULT_RANGE(start, end)) {
910e3ac9753SGrzegorz Bernacki 		start = sc->sc_mem_base;
911e3ac9753SGrzegorz Bernacki 		end = sc->sc_mem_base + sc->sc_mem_size - 1;
912e3ac9753SGrzegorz Bernacki 		count = sc->sc_mem_size;
913e3ac9753SGrzegorz Bernacki 	}
914e3ac9753SGrzegorz Bernacki 
915e3ac9753SGrzegorz Bernacki 	if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
916e3ac9753SGrzegorz Bernacki 	    (end > sc->sc_mem_base + sc->sc_mem_size - 1))
917e3ac9753SGrzegorz Bernacki 		return (NULL);
918e3ac9753SGrzegorz Bernacki 
919db5ef4fcSRafal Jaworowski 	res = rman_reserve_resource(rm, start, end, count, flags, child);
920db5ef4fcSRafal Jaworowski 	if (res == NULL)
921db5ef4fcSRafal Jaworowski 		return (NULL);
922db5ef4fcSRafal Jaworowski 
923db5ef4fcSRafal Jaworowski 	rman_set_rid(res, *rid);
924db5ef4fcSRafal Jaworowski 	rman_set_bustag(res, fdtbus_bs_tag);
925db5ef4fcSRafal Jaworowski 	rman_set_bushandle(res, start);
926db5ef4fcSRafal Jaworowski 
927db5ef4fcSRafal Jaworowski 	if (flags & RF_ACTIVE)
928db5ef4fcSRafal Jaworowski 		if (bus_activate_resource(child, type, *rid, res)) {
929db5ef4fcSRafal Jaworowski 			rman_release_resource(res);
930db5ef4fcSRafal Jaworowski 			return (NULL);
931db5ef4fcSRafal Jaworowski 		}
932db5ef4fcSRafal Jaworowski 
933db5ef4fcSRafal Jaworowski 	return (res);
934db5ef4fcSRafal Jaworowski }
935db5ef4fcSRafal Jaworowski 
936db5ef4fcSRafal Jaworowski static int
937db5ef4fcSRafal Jaworowski mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
938db5ef4fcSRafal Jaworowski     struct resource *res)
939db5ef4fcSRafal Jaworowski {
9403a582d09SMarcin Wojtas #ifdef PCI_RES_BUS
9413a582d09SMarcin Wojtas 	struct mv_pcib_softc *sc = device_get_softc(dev);
942db5ef4fcSRafal Jaworowski 
9433a582d09SMarcin Wojtas 	if (type == PCI_RES_BUS)
9443a582d09SMarcin Wojtas 		return (pci_domain_release_bus(sc->ap_segment, child, rid, res));
9453a582d09SMarcin Wojtas #endif
946db5ef4fcSRafal Jaworowski 	if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
947db5ef4fcSRafal Jaworowski 		return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
948db5ef4fcSRafal Jaworowski 		    type, rid, res));
949db5ef4fcSRafal Jaworowski 
950db5ef4fcSRafal Jaworowski 	return (rman_release_resource(res));
951db5ef4fcSRafal Jaworowski }
952db5ef4fcSRafal Jaworowski 
953db5ef4fcSRafal Jaworowski static int
954db5ef4fcSRafal Jaworowski mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
955db5ef4fcSRafal Jaworowski {
956db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
957db5ef4fcSRafal Jaworowski 
958db5ef4fcSRafal Jaworowski 	switch (which) {
959db5ef4fcSRafal Jaworowski 	case PCIB_IVAR_BUS:
960db5ef4fcSRafal Jaworowski 		*result = sc->sc_busnr;
961db5ef4fcSRafal Jaworowski 		return (0);
962db5ef4fcSRafal Jaworowski 	case PCIB_IVAR_DOMAIN:
963db5ef4fcSRafal Jaworowski 		*result = device_get_unit(dev);
964db5ef4fcSRafal Jaworowski 		return (0);
965db5ef4fcSRafal Jaworowski 	}
966db5ef4fcSRafal Jaworowski 
967db5ef4fcSRafal Jaworowski 	return (ENOENT);
968db5ef4fcSRafal Jaworowski }
969db5ef4fcSRafal Jaworowski 
970db5ef4fcSRafal Jaworowski static int
971db5ef4fcSRafal Jaworowski mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
972db5ef4fcSRafal Jaworowski {
973db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
974db5ef4fcSRafal Jaworowski 
975db5ef4fcSRafal Jaworowski 	switch (which) {
976db5ef4fcSRafal Jaworowski 	case PCIB_IVAR_BUS:
977db5ef4fcSRafal Jaworowski 		sc->sc_busnr = value;
978db5ef4fcSRafal Jaworowski 		return (0);
979db5ef4fcSRafal Jaworowski 	}
980db5ef4fcSRafal Jaworowski 
981db5ef4fcSRafal Jaworowski 	return (ENOENT);
982db5ef4fcSRafal Jaworowski }
983db5ef4fcSRafal Jaworowski 
984db5ef4fcSRafal Jaworowski static inline void
985db5ef4fcSRafal Jaworowski pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
986db5ef4fcSRafal Jaworowski {
987db5ef4fcSRafal Jaworowski 
98826872c13SZbigniew Bodek 	if (sc->sc_type != MV_TYPE_PCIE)
989db5ef4fcSRafal Jaworowski 		return;
990db5ef4fcSRafal Jaworowski 
991db5ef4fcSRafal Jaworowski 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
992db5ef4fcSRafal Jaworowski }
993db5ef4fcSRafal Jaworowski 
994db5ef4fcSRafal Jaworowski static void
995db5ef4fcSRafal Jaworowski mv_pcib_hw_cfginit(void)
9966975124cSRafal Jaworowski {
9976975124cSRafal Jaworowski 	static int opened = 0;
9986975124cSRafal Jaworowski 
9996975124cSRafal Jaworowski 	if (opened)
10006975124cSRafal Jaworowski 		return;
10016975124cSRafal Jaworowski 
10026975124cSRafal Jaworowski 	mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
10036975124cSRafal Jaworowski 	opened = 1;
10046975124cSRafal Jaworowski }
10056975124cSRafal Jaworowski 
10066975124cSRafal Jaworowski static uint32_t
1007db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
10086975124cSRafal Jaworowski     u_int func, u_int reg, int bytes)
10096975124cSRafal Jaworowski {
10106975124cSRafal Jaworowski 	uint32_t addr, data, ca, cd;
10116975124cSRafal Jaworowski 
1012db5ef4fcSRafal Jaworowski 	ca = (sc->sc_type != MV_TYPE_PCI) ?
10136975124cSRafal Jaworowski 	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1014db5ef4fcSRafal Jaworowski 	cd = (sc->sc_type != MV_TYPE_PCI) ?
10156975124cSRafal Jaworowski 	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
10166975124cSRafal Jaworowski 	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
10176975124cSRafal Jaworowski 	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
10186975124cSRafal Jaworowski 
10196975124cSRafal Jaworowski 	mtx_lock_spin(&pcicfg_mtx);
10206975124cSRafal Jaworowski 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
10216975124cSRafal Jaworowski 
10226975124cSRafal Jaworowski 	data = ~0;
10236975124cSRafal Jaworowski 	switch (bytes) {
10246975124cSRafal Jaworowski 	case 1:
10256975124cSRafal Jaworowski 		data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
10266975124cSRafal Jaworowski 		    cd + (reg & 3));
10276975124cSRafal Jaworowski 		break;
10286975124cSRafal Jaworowski 	case 2:
10296975124cSRafal Jaworowski 		data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
10306975124cSRafal Jaworowski 		    cd + (reg & 2)));
10316975124cSRafal Jaworowski 		break;
10326975124cSRafal Jaworowski 	case 4:
10336975124cSRafal Jaworowski 		data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
10346975124cSRafal Jaworowski 		    cd));
10356975124cSRafal Jaworowski 		break;
10366975124cSRafal Jaworowski 	}
10376975124cSRafal Jaworowski 	mtx_unlock_spin(&pcicfg_mtx);
10386975124cSRafal Jaworowski 	return (data);
10396975124cSRafal Jaworowski }
10406975124cSRafal Jaworowski 
10416975124cSRafal Jaworowski static void
1042db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
10436975124cSRafal Jaworowski     u_int func, u_int reg, uint32_t data, int bytes)
10446975124cSRafal Jaworowski {
10456975124cSRafal Jaworowski 	uint32_t addr, ca, cd;
10466975124cSRafal Jaworowski 
1047db5ef4fcSRafal Jaworowski 	ca = (sc->sc_type != MV_TYPE_PCI) ?
10486975124cSRafal Jaworowski 	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1049db5ef4fcSRafal Jaworowski 	cd = (sc->sc_type != MV_TYPE_PCI) ?
10506975124cSRafal Jaworowski 	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
10516975124cSRafal Jaworowski 	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
10526975124cSRafal Jaworowski 	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
10536975124cSRafal Jaworowski 
10546975124cSRafal Jaworowski 	mtx_lock_spin(&pcicfg_mtx);
10556975124cSRafal Jaworowski 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
10566975124cSRafal Jaworowski 
10576975124cSRafal Jaworowski 	switch (bytes) {
10586975124cSRafal Jaworowski 	case 1:
10596975124cSRafal Jaworowski 		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
10606975124cSRafal Jaworowski 		    cd + (reg & 3), data);
10616975124cSRafal Jaworowski 		break;
10626975124cSRafal Jaworowski 	case 2:
10636975124cSRafal Jaworowski 		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
10646975124cSRafal Jaworowski 		    cd + (reg & 2), htole16(data));
10656975124cSRafal Jaworowski 		break;
10666975124cSRafal Jaworowski 	case 4:
10676975124cSRafal Jaworowski 		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
10686975124cSRafal Jaworowski 		    cd, htole32(data));
10696975124cSRafal Jaworowski 		break;
10706975124cSRafal Jaworowski 	}
10716975124cSRafal Jaworowski 	mtx_unlock_spin(&pcicfg_mtx);
10726975124cSRafal Jaworowski }
10736975124cSRafal Jaworowski 
10746975124cSRafal Jaworowski static int
1075db5ef4fcSRafal Jaworowski mv_pcib_maxslots(device_t dev)
10766975124cSRafal Jaworowski {
1077db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
10786975124cSRafal Jaworowski 
1079db5ef4fcSRafal Jaworowski 	return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
10806975124cSRafal Jaworowski }
10816975124cSRafal Jaworowski 
10821e92574fSZbigniew Bodek static int
10831e92574fSZbigniew Bodek mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
10841e92574fSZbigniew Bodek {
10851e92574fSZbigniew Bodek 	struct mv_pcib_softc *sc = device_get_softc(dev);
10861e92574fSZbigniew Bodek 	uint32_t vendor, device;
10871e92574fSZbigniew Bodek 
1088fefc2cf7SMarcin Wojtas 	/* On platforms other than Armada38x, root link is always at slot 0 */
1089fefc2cf7SMarcin Wojtas 	if (!sc->sc_enable_find_root_slot)
1090fefc2cf7SMarcin Wojtas 		return (slot == 0);
1091fefc2cf7SMarcin Wojtas 
10921e92574fSZbigniew Bodek 	vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
10931e92574fSZbigniew Bodek 	    PCIR_VENDOR_LENGTH);
10941e92574fSZbigniew Bodek 	device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
10951e92574fSZbigniew Bodek 	    PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
10961e92574fSZbigniew Bodek 
10971e92574fSZbigniew Bodek 	return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
10981e92574fSZbigniew Bodek }
10991e92574fSZbigniew Bodek 
11006975124cSRafal Jaworowski static uint32_t
1101db5ef4fcSRafal Jaworowski mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
11026975124cSRafal Jaworowski     u_int reg, int bytes)
11036975124cSRafal Jaworowski {
1104db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
11056975124cSRafal Jaworowski 
1106e3ac9753SGrzegorz Bernacki 	/* Return ~0 if link is inactive or trying to read from Root */
1107e3ac9753SGrzegorz Bernacki 	if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
11081e92574fSZbigniew Bodek 	    PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
11096975124cSRafal Jaworowski 		return (~0U);
11106975124cSRafal Jaworowski 
1111db5ef4fcSRafal Jaworowski 	return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
11126975124cSRafal Jaworowski }
11136975124cSRafal Jaworowski 
11146975124cSRafal Jaworowski static void
1115db5ef4fcSRafal Jaworowski mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
11166975124cSRafal Jaworowski     u_int reg, uint32_t val, int bytes)
11176975124cSRafal Jaworowski {
1118db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc = device_get_softc(dev);
11196975124cSRafal Jaworowski 
1120e3ac9753SGrzegorz Bernacki 	/* Return if link is inactive or trying to write to Root */
1121e3ac9753SGrzegorz Bernacki 	if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
11221e92574fSZbigniew Bodek 	    PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
11236975124cSRafal Jaworowski 		return;
11246975124cSRafal Jaworowski 
1125db5ef4fcSRafal Jaworowski 	mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
11266975124cSRafal Jaworowski }
11276975124cSRafal Jaworowski 
1128db5ef4fcSRafal Jaworowski static int
1129c826a643SNathan Whitehorn mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
11306975124cSRafal Jaworowski {
1131db5ef4fcSRafal Jaworowski 	struct mv_pcib_softc *sc;
1132c826a643SNathan Whitehorn 	struct ofw_pci_register reg;
1133bbc6da03SNathan Whitehorn 	uint32_t pintr, mintr[4];
1134bbc6da03SNathan Whitehorn 	int icells;
1135c826a643SNathan Whitehorn 	phandle_t iparent;
1136db5ef4fcSRafal Jaworowski 
1137c826a643SNathan Whitehorn 	sc = device_get_softc(bus);
1138c826a643SNathan Whitehorn 	pintr = pin;
1139db5ef4fcSRafal Jaworowski 
1140c826a643SNathan Whitehorn 	/* Fabricate imap information in case this isn't an OFW device */
1141c826a643SNathan Whitehorn 	bzero(&reg, sizeof(reg));
1142c826a643SNathan Whitehorn 	reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1143c826a643SNathan Whitehorn 	    (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1144c826a643SNathan Whitehorn 	    (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1145db5ef4fcSRafal Jaworowski 
1146bbc6da03SNathan Whitehorn 	icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1147bbc6da03SNathan Whitehorn 	    &reg, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1148bbc6da03SNathan Whitehorn 	    &iparent);
1149bbc6da03SNathan Whitehorn 	if (icells > 0)
1150bbc6da03SNathan Whitehorn 		return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1151c826a643SNathan Whitehorn 
1152c826a643SNathan Whitehorn 	/* Maybe it's a real interrupt, not an intpin */
1153c826a643SNathan Whitehorn 	if (pin > 4)
1154c826a643SNathan Whitehorn 		return (pin);
1155c826a643SNathan Whitehorn 
1156c826a643SNathan Whitehorn 	device_printf(bus, "could not route pin %d for device %d.%d\n",
1157db5ef4fcSRafal Jaworowski 	    pin, pci_get_slot(dev), pci_get_function(dev));
1158db5ef4fcSRafal Jaworowski 	return (PCI_INVALID_IRQ);
1159db5ef4fcSRafal Jaworowski }
1160db5ef4fcSRafal Jaworowski 
1161db5ef4fcSRafal Jaworowski static int
1162db5ef4fcSRafal Jaworowski mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1163db5ef4fcSRafal Jaworowski {
116402c7dba9SIan Lepore 	struct mv_pci_range io_space, mem_space;
1165db5ef4fcSRafal Jaworowski 	device_t dev;
11666975124cSRafal Jaworowski 	int error;
11676975124cSRafal Jaworowski 
1168db5ef4fcSRafal Jaworowski 	dev = sc->sc_dev;
1169db5ef4fcSRafal Jaworowski 
117002c7dba9SIan Lepore 	if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1171db5ef4fcSRafal Jaworowski 		device_printf(dev, "could not retrieve 'ranges' data\n");
1172db5ef4fcSRafal Jaworowski 		return (error);
1173db5ef4fcSRafal Jaworowski 	}
1174db5ef4fcSRafal Jaworowski 
11756975124cSRafal Jaworowski 	/* Configure CPU decoding windows */
1176e3ac9753SGrzegorz Bernacki 	error = decode_win_cpu_set(sc->sc_win_target,
1177e3ac9753SGrzegorz Bernacki 	    sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
11786975124cSRafal Jaworowski 	if (error < 0) {
1179db5ef4fcSRafal Jaworowski 		device_printf(dev, "could not set up CPU decode "
11806975124cSRafal Jaworowski 		    "window for PCI IO\n");
1181db5ef4fcSRafal Jaworowski 		return (ENXIO);
11826975124cSRafal Jaworowski 	}
1183e3ac9753SGrzegorz Bernacki 	error = decode_win_cpu_set(sc->sc_win_target,
1184e3ac9753SGrzegorz Bernacki 	    sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1185e3ac9753SGrzegorz Bernacki 	    mem_space.base_parent);
11866975124cSRafal Jaworowski 	if (error < 0) {
1187db5ef4fcSRafal Jaworowski 		device_printf(dev, "could not set up CPU decode "
11886975124cSRafal Jaworowski 		    "windows for PCI MEM\n");
1189db5ef4fcSRafal Jaworowski 		return (ENXIO);
11906975124cSRafal Jaworowski 	}
11916975124cSRafal Jaworowski 
1192db5ef4fcSRafal Jaworowski 	sc->sc_io_base = io_space.base_parent;
1193db5ef4fcSRafal Jaworowski 	sc->sc_io_size = io_space.len;
1194db5ef4fcSRafal Jaworowski 
1195db5ef4fcSRafal Jaworowski 	sc->sc_mem_base = mem_space.base_parent;
1196db5ef4fcSRafal Jaworowski 	sc->sc_mem_size = mem_space.len;
1197db5ef4fcSRafal Jaworowski 
1198db5ef4fcSRafal Jaworowski 	return (0);
11996975124cSRafal Jaworowski }
12006975124cSRafal Jaworowski 
120164dc1cf3SGrzegorz Bernacki static int
120264dc1cf3SGrzegorz Bernacki mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
120364dc1cf3SGrzegorz Bernacki     uint32_t *data)
120464dc1cf3SGrzegorz Bernacki {
120564dc1cf3SGrzegorz Bernacki 	struct mv_pcib_softc *sc;
120664dc1cf3SGrzegorz Bernacki 
120764dc1cf3SGrzegorz Bernacki 	sc = device_get_softc(dev);
1208fefc2cf7SMarcin Wojtas 	if (!sc->sc_msi_supported)
1209fefc2cf7SMarcin Wojtas 		return (ENOTSUP);
1210fefc2cf7SMarcin Wojtas 
121164dc1cf3SGrzegorz Bernacki 	irq = irq - MSI_IRQ;
121264dc1cf3SGrzegorz Bernacki 
121364dc1cf3SGrzegorz Bernacki 	/* validate parameters */
121464dc1cf3SGrzegorz Bernacki 	if (isclr(&sc->sc_msi_bitmap, irq)) {
121564dc1cf3SGrzegorz Bernacki 		device_printf(dev, "invalid MSI 0x%x\n", irq);
121664dc1cf3SGrzegorz Bernacki 		return (EINVAL);
121764dc1cf3SGrzegorz Bernacki 	}
121864dc1cf3SGrzegorz Bernacki 
121964dc1cf3SGrzegorz Bernacki 	mv_msi_data(irq, addr, data);
122064dc1cf3SGrzegorz Bernacki 
122164dc1cf3SGrzegorz Bernacki 	debugf("%s: irq: %d addr: %jx data: %x\n",
122264dc1cf3SGrzegorz Bernacki 	    __func__, irq, *addr, *data);
122364dc1cf3SGrzegorz Bernacki 
122464dc1cf3SGrzegorz Bernacki 	return (0);
122564dc1cf3SGrzegorz Bernacki }
122664dc1cf3SGrzegorz Bernacki 
122764dc1cf3SGrzegorz Bernacki static int
122864dc1cf3SGrzegorz Bernacki mv_pcib_alloc_msi(device_t dev, device_t child, int count,
122964dc1cf3SGrzegorz Bernacki     int maxcount __unused, int *irqs)
123064dc1cf3SGrzegorz Bernacki {
123164dc1cf3SGrzegorz Bernacki 	struct mv_pcib_softc *sc;
123264dc1cf3SGrzegorz Bernacki 	u_int start = 0, i;
123364dc1cf3SGrzegorz Bernacki 
1234fefc2cf7SMarcin Wojtas 	sc = device_get_softc(dev);
1235fefc2cf7SMarcin Wojtas 	if (!sc->sc_msi_supported)
1236fefc2cf7SMarcin Wojtas 		return (ENOTSUP);
1237fefc2cf7SMarcin Wojtas 
123864dc1cf3SGrzegorz Bernacki 	if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
123964dc1cf3SGrzegorz Bernacki 		return (EINVAL);
124064dc1cf3SGrzegorz Bernacki 
124164dc1cf3SGrzegorz Bernacki 	mtx_lock(&sc->sc_msi_mtx);
124264dc1cf3SGrzegorz Bernacki 
124364dc1cf3SGrzegorz Bernacki 	for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
124464dc1cf3SGrzegorz Bernacki 		for (i = start; i < start + count; i++) {
124564dc1cf3SGrzegorz Bernacki 			if (isset(&sc->sc_msi_bitmap, i))
124664dc1cf3SGrzegorz Bernacki 				break;
124764dc1cf3SGrzegorz Bernacki 		}
124864dc1cf3SGrzegorz Bernacki 		if (i == start + count)
124964dc1cf3SGrzegorz Bernacki 			break;
125064dc1cf3SGrzegorz Bernacki 	}
125164dc1cf3SGrzegorz Bernacki 
125264dc1cf3SGrzegorz Bernacki 	if ((start + count) == MSI_IRQ_NUM) {
125364dc1cf3SGrzegorz Bernacki 		mtx_unlock(&sc->sc_msi_mtx);
125464dc1cf3SGrzegorz Bernacki 		return (ENXIO);
125564dc1cf3SGrzegorz Bernacki 	}
125664dc1cf3SGrzegorz Bernacki 
125764dc1cf3SGrzegorz Bernacki 	for (i = start; i < start + count; i++) {
125864dc1cf3SGrzegorz Bernacki 		setbit(&sc->sc_msi_bitmap, i);
125989489567SZbigniew Bodek 		*irqs++ = MSI_IRQ + i;
126064dc1cf3SGrzegorz Bernacki 	}
126164dc1cf3SGrzegorz Bernacki 	debugf("%s: start: %x count: %x\n", __func__, start, count);
126264dc1cf3SGrzegorz Bernacki 
126364dc1cf3SGrzegorz Bernacki 	mtx_unlock(&sc->sc_msi_mtx);
126464dc1cf3SGrzegorz Bernacki 	return (0);
126564dc1cf3SGrzegorz Bernacki }
126664dc1cf3SGrzegorz Bernacki 
126764dc1cf3SGrzegorz Bernacki static int
126864dc1cf3SGrzegorz Bernacki mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
126964dc1cf3SGrzegorz Bernacki {
127064dc1cf3SGrzegorz Bernacki 	struct mv_pcib_softc *sc;
127164dc1cf3SGrzegorz Bernacki 	u_int i;
127264dc1cf3SGrzegorz Bernacki 
127364dc1cf3SGrzegorz Bernacki 	sc = device_get_softc(dev);
1274fefc2cf7SMarcin Wojtas 	if(!sc->sc_msi_supported)
1275fefc2cf7SMarcin Wojtas 		return (ENOTSUP);
1276fefc2cf7SMarcin Wojtas 
127764dc1cf3SGrzegorz Bernacki 	mtx_lock(&sc->sc_msi_mtx);
127864dc1cf3SGrzegorz Bernacki 
127964dc1cf3SGrzegorz Bernacki 	for (i = 0; i < count; i++)
128064dc1cf3SGrzegorz Bernacki 		clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
128164dc1cf3SGrzegorz Bernacki 
128264dc1cf3SGrzegorz Bernacki 	mtx_unlock(&sc->sc_msi_mtx);
128364dc1cf3SGrzegorz Bernacki 	return (0);
128464dc1cf3SGrzegorz Bernacki }
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