16975124cSRafal Jaworowski /*- 2db5ef4fcSRafal Jaworowski * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3db5ef4fcSRafal Jaworowski * Copyright (c) 2010 The FreeBSD Foundation 4e3ac9753SGrzegorz Bernacki * Copyright (c) 2010-2012 Semihalf 56975124cSRafal Jaworowski * All rights reserved. 66975124cSRafal Jaworowski * 76975124cSRafal Jaworowski * Developed by Semihalf. 86975124cSRafal Jaworowski * 9db5ef4fcSRafal Jaworowski * Portions of this software were developed by Semihalf 10db5ef4fcSRafal Jaworowski * under sponsorship from the FreeBSD Foundation. 11db5ef4fcSRafal Jaworowski * 126975124cSRafal Jaworowski * Redistribution and use in source and binary forms, with or without 136975124cSRafal Jaworowski * modification, are permitted provided that the following conditions 146975124cSRafal Jaworowski * are met: 156975124cSRafal Jaworowski * 1. Redistributions of source code must retain the above copyright 166975124cSRafal Jaworowski * notice, this list of conditions and the following disclaimer. 176975124cSRafal Jaworowski * 2. Redistributions in binary form must reproduce the above copyright 186975124cSRafal Jaworowski * notice, this list of conditions and the following disclaimer in the 196975124cSRafal Jaworowski * documentation and/or other materials provided with the distribution. 206975124cSRafal Jaworowski * 3. Neither the name of MARVELL nor the names of contributors 216975124cSRafal Jaworowski * may be used to endorse or promote products derived from this software 226975124cSRafal Jaworowski * without specific prior written permission. 236975124cSRafal Jaworowski * 246975124cSRafal Jaworowski * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 256975124cSRafal Jaworowski * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 266975124cSRafal Jaworowski * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 276975124cSRafal Jaworowski * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 286975124cSRafal Jaworowski * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 296975124cSRafal Jaworowski * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 306975124cSRafal Jaworowski * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 316975124cSRafal Jaworowski * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 326975124cSRafal Jaworowski * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 336975124cSRafal Jaworowski * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 346975124cSRafal Jaworowski * SUCH DAMAGE. 356975124cSRafal Jaworowski */ 366975124cSRafal Jaworowski 376975124cSRafal Jaworowski /* 386975124cSRafal Jaworowski * Marvell integrated PCI/PCI-Express controller driver. 396975124cSRafal Jaworowski */ 406975124cSRafal Jaworowski 416975124cSRafal Jaworowski #include <sys/cdefs.h> 426975124cSRafal Jaworowski __FBSDID("$FreeBSD$"); 436975124cSRafal Jaworowski 446975124cSRafal Jaworowski #include <sys/param.h> 456975124cSRafal Jaworowski #include <sys/systm.h> 466975124cSRafal Jaworowski #include <sys/kernel.h> 476975124cSRafal Jaworowski #include <sys/lock.h> 486975124cSRafal Jaworowski #include <sys/malloc.h> 496975124cSRafal Jaworowski #include <sys/module.h> 506975124cSRafal Jaworowski #include <sys/mutex.h> 516975124cSRafal Jaworowski #include <sys/queue.h> 526975124cSRafal Jaworowski #include <sys/bus.h> 536975124cSRafal Jaworowski #include <sys/rman.h> 546975124cSRafal Jaworowski #include <sys/endian.h> 556975124cSRafal Jaworowski 56*64dc1cf3SGrzegorz Bernacki #include <machine/intr.h> 57*64dc1cf3SGrzegorz Bernacki 586975124cSRafal Jaworowski #include <vm/vm.h> 596975124cSRafal Jaworowski #include <vm/pmap.h> 606975124cSRafal Jaworowski 61db5ef4fcSRafal Jaworowski #include <dev/fdt/fdt_common.h> 62db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus.h> 63db5ef4fcSRafal Jaworowski #include <dev/ofw/ofw_bus_subr.h> 646975124cSRafal Jaworowski #include <dev/pci/pcivar.h> 656975124cSRafal Jaworowski #include <dev/pci/pcireg.h> 666975124cSRafal Jaworowski #include <dev/pci/pcib_private.h> 676975124cSRafal Jaworowski 68db5ef4fcSRafal Jaworowski #include "ofw_bus_if.h" 696975124cSRafal Jaworowski #include "pcib_if.h" 706975124cSRafal Jaworowski 716975124cSRafal Jaworowski #include <machine/resource.h> 726975124cSRafal Jaworowski #include <machine/bus.h> 736975124cSRafal Jaworowski 746975124cSRafal Jaworowski #include <arm/mv/mvreg.h> 756975124cSRafal Jaworowski #include <arm/mv/mvvar.h> 76db5ef4fcSRafal Jaworowski #include <arm/mv/mvwin.h> 776975124cSRafal Jaworowski 78*64dc1cf3SGrzegorz Bernacki #ifdef DEBUG 79*64dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 80*64dc1cf3SGrzegorz Bernacki #else 81*64dc1cf3SGrzegorz Bernacki #define debugf(fmt, args...) 82*64dc1cf3SGrzegorz Bernacki #endif 83*64dc1cf3SGrzegorz Bernacki 846975124cSRafal Jaworowski #define PCI_CFG_ENA (1 << 31) 856975124cSRafal Jaworowski #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 866975124cSRafal Jaworowski #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 876975124cSRafal Jaworowski #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 886975124cSRafal Jaworowski #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 896975124cSRafal Jaworowski 906975124cSRafal Jaworowski #define PCI_REG_CFG_ADDR 0x0C78 916975124cSRafal Jaworowski #define PCI_REG_CFG_DATA 0x0C7C 926975124cSRafal Jaworowski 936975124cSRafal Jaworowski #define PCIE_REG_CFG_ADDR 0x18F8 946975124cSRafal Jaworowski #define PCIE_REG_CFG_DATA 0x18FC 956975124cSRafal Jaworowski #define PCIE_REG_CONTROL 0x1A00 966975124cSRafal Jaworowski #define PCIE_CTRL_LINK1X 0x00000001 976975124cSRafal Jaworowski #define PCIE_REG_STATUS 0x1A04 986975124cSRafal Jaworowski #define PCIE_REG_IRQ_MASK 0x1910 996975124cSRafal Jaworowski 100e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 101e3ac9753SGrzegorz Bernacki #define PCIE_CONTROL_HOT_RESET (1 << 24) 1026975124cSRafal Jaworowski 103e3ac9753SGrzegorz Bernacki #define PCIE_LINK_TIMEOUT 1000000 1046975124cSRafal Jaworowski 105e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_LINK_DOWN 1 106e3ac9753SGrzegorz Bernacki #define PCIE_STATUS_DEV_OFFS 16 107e3ac9753SGrzegorz Bernacki 108e3ac9753SGrzegorz Bernacki /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 109e3ac9753SGrzegorz Bernacki #define PCI_MIN_IO_ALLOC 4 110e3ac9753SGrzegorz Bernacki #define PCI_MIN_MEM_ALLOC 16 111e3ac9753SGrzegorz Bernacki 112e3ac9753SGrzegorz Bernacki #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 1136975124cSRafal Jaworowski 114db5ef4fcSRafal Jaworowski struct mv_pcib_softc { 1156975124cSRafal Jaworowski device_t sc_dev; 1166975124cSRafal Jaworowski 117db5ef4fcSRafal Jaworowski struct rman sc_mem_rman; 118db5ef4fcSRafal Jaworowski bus_addr_t sc_mem_base; 119db5ef4fcSRafal Jaworowski bus_addr_t sc_mem_size; 120e3ac9753SGrzegorz Bernacki uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 121e3ac9753SGrzegorz Bernacki (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 122e3ac9753SGrzegorz Bernacki int sc_win_target; 123db5ef4fcSRafal Jaworowski int sc_mem_win_attr; 1246975124cSRafal Jaworowski 125db5ef4fcSRafal Jaworowski struct rman sc_io_rman; 126db5ef4fcSRafal Jaworowski bus_addr_t sc_io_base; 127db5ef4fcSRafal Jaworowski bus_addr_t sc_io_size; 128e3ac9753SGrzegorz Bernacki uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 129e3ac9753SGrzegorz Bernacki (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 130db5ef4fcSRafal Jaworowski int sc_io_win_attr; 1316975124cSRafal Jaworowski 1326975124cSRafal Jaworowski struct resource *sc_res; 1336975124cSRafal Jaworowski bus_space_handle_t sc_bsh; 1346975124cSRafal Jaworowski bus_space_tag_t sc_bst; 1356975124cSRafal Jaworowski int sc_rid; 1366975124cSRafal Jaworowski 137*64dc1cf3SGrzegorz Bernacki struct mtx sc_msi_mtx; 138*64dc1cf3SGrzegorz Bernacki uint32_t sc_msi_bitmap; 139*64dc1cf3SGrzegorz Bernacki 1406975124cSRafal Jaworowski int sc_busnr; /* Host bridge bus number */ 1416975124cSRafal Jaworowski int sc_devnr; /* Host bridge device number */ 142db5ef4fcSRafal Jaworowski int sc_type; 143e3ac9753SGrzegorz Bernacki int sc_mode; /* Endpoint / Root Complex */ 1446975124cSRafal Jaworowski 145db5ef4fcSRafal Jaworowski struct fdt_pci_intr sc_intr_info; 1466975124cSRafal Jaworowski }; 1476975124cSRafal Jaworowski 148db5ef4fcSRafal Jaworowski /* Local forward prototypes */ 149db5ef4fcSRafal Jaworowski static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 150db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfginit(void); 151db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 152db5ef4fcSRafal Jaworowski u_int, u_int, int); 153db5ef4fcSRafal Jaworowski static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 154db5ef4fcSRafal Jaworowski u_int, u_int, uint32_t, int); 155db5ef4fcSRafal Jaworowski static int mv_pcib_init(struct mv_pcib_softc *, int, int); 156db5ef4fcSRafal Jaworowski static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 157db5ef4fcSRafal Jaworowski static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 158db5ef4fcSRafal Jaworowski static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *); 159db5ef4fcSRafal Jaworowski static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 160e3ac9753SGrzegorz Bernacki static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 161e3ac9753SGrzegorz Bernacki static int mv_pcib_mem_init(struct mv_pcib_softc *); 162db5ef4fcSRafal Jaworowski 163db5ef4fcSRafal Jaworowski /* Forward prototypes */ 164db5ef4fcSRafal Jaworowski static int mv_pcib_probe(device_t); 165db5ef4fcSRafal Jaworowski static int mv_pcib_attach(device_t); 166db5ef4fcSRafal Jaworowski 167db5ef4fcSRafal Jaworowski static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 1686975124cSRafal Jaworowski u_long, u_long, u_long, u_int); 169db5ef4fcSRafal Jaworowski static int mv_pcib_release_resource(device_t, device_t, int, int, 1706975124cSRafal Jaworowski struct resource *); 171db5ef4fcSRafal Jaworowski static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 172db5ef4fcSRafal Jaworowski static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 1736975124cSRafal Jaworowski 174db5ef4fcSRafal Jaworowski static int mv_pcib_maxslots(device_t); 175db5ef4fcSRafal Jaworowski static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 176db5ef4fcSRafal Jaworowski static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 1776975124cSRafal Jaworowski uint32_t, int); 178db5ef4fcSRafal Jaworowski static int mv_pcib_route_interrupt(device_t, device_t, int); 179*64dc1cf3SGrzegorz Bernacki #if defined(SOC_MV_ARMADAXP) 180*64dc1cf3SGrzegorz Bernacki static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 181*64dc1cf3SGrzegorz Bernacki static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 182*64dc1cf3SGrzegorz Bernacki static int mv_pcib_release_msi(device_t, device_t, int, int *); 183*64dc1cf3SGrzegorz Bernacki #endif 1846975124cSRafal Jaworowski 1856975124cSRafal Jaworowski /* 1866975124cSRafal Jaworowski * Bus interface definitions. 1876975124cSRafal Jaworowski */ 188db5ef4fcSRafal Jaworowski static device_method_t mv_pcib_methods[] = { 1896975124cSRafal Jaworowski /* Device interface */ 190db5ef4fcSRafal Jaworowski DEVMETHOD(device_probe, mv_pcib_probe), 191db5ef4fcSRafal Jaworowski DEVMETHOD(device_attach, mv_pcib_attach), 1926975124cSRafal Jaworowski 1936975124cSRafal Jaworowski /* Bus interface */ 194db5ef4fcSRafal Jaworowski DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 195db5ef4fcSRafal Jaworowski DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 196db5ef4fcSRafal Jaworowski DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 197db5ef4fcSRafal Jaworowski DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 1986975124cSRafal Jaworowski DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 1996975124cSRafal Jaworowski DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 2006975124cSRafal Jaworowski DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 2016975124cSRafal Jaworowski DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 2026975124cSRafal Jaworowski 2036975124cSRafal Jaworowski /* pcib interface */ 204db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 205db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_read_config, mv_pcib_read_config), 206db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_write_config, mv_pcib_write_config), 207db5ef4fcSRafal Jaworowski DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 208db5ef4fcSRafal Jaworowski 209*64dc1cf3SGrzegorz Bernacki #if defined(SOC_MV_ARMADAXP) 210*64dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 211*64dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 212*64dc1cf3SGrzegorz Bernacki DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 213*64dc1cf3SGrzegorz Bernacki #endif 214*64dc1cf3SGrzegorz Bernacki 215db5ef4fcSRafal Jaworowski /* OFW bus interface */ 216db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 217db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 218db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 219db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 220db5ef4fcSRafal Jaworowski DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 2216975124cSRafal Jaworowski 2224b7ec270SMarius Strobl DEVMETHOD_END 2236975124cSRafal Jaworowski }; 2246975124cSRafal Jaworowski 225db5ef4fcSRafal Jaworowski static driver_t mv_pcib_driver = { 2266975124cSRafal Jaworowski "pcib", 227db5ef4fcSRafal Jaworowski mv_pcib_methods, 228db5ef4fcSRafal Jaworowski sizeof(struct mv_pcib_softc), 2296975124cSRafal Jaworowski }; 2306975124cSRafal Jaworowski 2316975124cSRafal Jaworowski devclass_t pcib_devclass; 2326975124cSRafal Jaworowski 233db5ef4fcSRafal Jaworowski DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0); 2346975124cSRafal Jaworowski 2356975124cSRafal Jaworowski static struct mtx pcicfg_mtx; 2366975124cSRafal Jaworowski 237db5ef4fcSRafal Jaworowski static int 238db5ef4fcSRafal Jaworowski mv_pcib_probe(device_t self) 2396975124cSRafal Jaworowski { 2401b96faf8SMarcel Moolenaar phandle_t node; 2416975124cSRafal Jaworowski 2421b96faf8SMarcel Moolenaar node = ofw_bus_get_node(self); 2431b96faf8SMarcel Moolenaar if (!fdt_is_type(node, "pci")) 244db5ef4fcSRafal Jaworowski return (ENXIO); 2451b96faf8SMarcel Moolenaar 2461b96faf8SMarcel Moolenaar if (!(fdt_is_compatible(node, "mrvl,pcie") || 2471b96faf8SMarcel Moolenaar fdt_is_compatible(node, "mrvl,pci"))) 248db5ef4fcSRafal Jaworowski return (ENXIO); 2496975124cSRafal Jaworowski 250db5ef4fcSRafal Jaworowski device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 251db5ef4fcSRafal Jaworowski return (BUS_PROBE_DEFAULT); 252db5ef4fcSRafal Jaworowski } 253db5ef4fcSRafal Jaworowski 254db5ef4fcSRafal Jaworowski static int 255db5ef4fcSRafal Jaworowski mv_pcib_attach(device_t self) 256db5ef4fcSRafal Jaworowski { 257db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc; 258db5ef4fcSRafal Jaworowski phandle_t node, parnode; 259e3ac9753SGrzegorz Bernacki uint32_t val, unit; 260db5ef4fcSRafal Jaworowski int err; 261db5ef4fcSRafal Jaworowski 262db5ef4fcSRafal Jaworowski sc = device_get_softc(self); 263db5ef4fcSRafal Jaworowski sc->sc_dev = self; 264e3ac9753SGrzegorz Bernacki unit = fdt_get_unit(self); 265e3ac9753SGrzegorz Bernacki 266db5ef4fcSRafal Jaworowski 2671b96faf8SMarcel Moolenaar node = ofw_bus_get_node(self); 2681b96faf8SMarcel Moolenaar parnode = OF_parent(node); 2691b96faf8SMarcel Moolenaar if (fdt_is_compatible(node, "mrvl,pcie")) { 270db5ef4fcSRafal Jaworowski sc->sc_type = MV_TYPE_PCIE; 271e3ac9753SGrzegorz Bernacki sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 272e3ac9753SGrzegorz Bernacki sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 273e3ac9753SGrzegorz Bernacki sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 2741b96faf8SMarcel Moolenaar } else if (fdt_is_compatible(node, "mrvl,pci")) { 275db5ef4fcSRafal Jaworowski sc->sc_type = MV_TYPE_PCI; 276e3ac9753SGrzegorz Bernacki sc->sc_win_target = MV_WIN_PCI_TARGET; 277db5ef4fcSRafal Jaworowski sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 278db5ef4fcSRafal Jaworowski sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 279db5ef4fcSRafal Jaworowski } else 280db5ef4fcSRafal Jaworowski return (ENXIO); 281db5ef4fcSRafal Jaworowski 282db5ef4fcSRafal Jaworowski /* 283db5ef4fcSRafal Jaworowski * Retrieve our mem-mapped registers range. 284db5ef4fcSRafal Jaworowski */ 285db5ef4fcSRafal Jaworowski sc->sc_rid = 0; 286db5ef4fcSRafal Jaworowski sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 287db5ef4fcSRafal Jaworowski RF_ACTIVE); 288db5ef4fcSRafal Jaworowski if (sc->sc_res == NULL) { 289db5ef4fcSRafal Jaworowski device_printf(self, "could not map memory\n"); 290db5ef4fcSRafal Jaworowski return (ENXIO); 291db5ef4fcSRafal Jaworowski } 292db5ef4fcSRafal Jaworowski sc->sc_bst = rman_get_bustag(sc->sc_res); 293db5ef4fcSRafal Jaworowski sc->sc_bsh = rman_get_bushandle(sc->sc_res); 294db5ef4fcSRafal Jaworowski 295e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 296e3ac9753SGrzegorz Bernacki sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 297e3ac9753SGrzegorz Bernacki MV_MODE_ENDPOINT); 298e3ac9753SGrzegorz Bernacki 299e3ac9753SGrzegorz Bernacki /* 300e3ac9753SGrzegorz Bernacki * Get PCI interrupt info. 301e3ac9753SGrzegorz Bernacki */ 302e3ac9753SGrzegorz Bernacki if ((sc->sc_mode == MV_MODE_ROOT) && 303e3ac9753SGrzegorz Bernacki (mv_pcib_intr_info(node, sc) != 0)) { 304e3ac9753SGrzegorz Bernacki device_printf(self, "could not retrieve interrupt info\n"); 305e3ac9753SGrzegorz Bernacki return (ENXIO); 306e3ac9753SGrzegorz Bernacki } 307e3ac9753SGrzegorz Bernacki 308db5ef4fcSRafal Jaworowski /* 309db5ef4fcSRafal Jaworowski * Configure decode windows for PCI(E) access. 310db5ef4fcSRafal Jaworowski */ 311db5ef4fcSRafal Jaworowski if (mv_pcib_decode_win(node, sc) != 0) 312db5ef4fcSRafal Jaworowski return (ENXIO); 313db5ef4fcSRafal Jaworowski 314db5ef4fcSRafal Jaworowski mv_pcib_hw_cfginit(); 315db5ef4fcSRafal Jaworowski 316db5ef4fcSRafal Jaworowski /* 317e3ac9753SGrzegorz Bernacki * Enable PCIE device. 318e3ac9753SGrzegorz Bernacki */ 319e3ac9753SGrzegorz Bernacki mv_pcib_enable(sc, unit); 320e3ac9753SGrzegorz Bernacki 321e3ac9753SGrzegorz Bernacki /* 322e3ac9753SGrzegorz Bernacki * Memory management. 323e3ac9753SGrzegorz Bernacki */ 324e3ac9753SGrzegorz Bernacki err = mv_pcib_mem_init(sc); 325e3ac9753SGrzegorz Bernacki if (err) 326e3ac9753SGrzegorz Bernacki return (err); 327e3ac9753SGrzegorz Bernacki 328e3ac9753SGrzegorz Bernacki if (sc->sc_mode == MV_MODE_ROOT) { 329e3ac9753SGrzegorz Bernacki err = mv_pcib_init(sc, sc->sc_busnr, 330e3ac9753SGrzegorz Bernacki mv_pcib_maxslots(sc->sc_dev)); 331e3ac9753SGrzegorz Bernacki if (err) 332e3ac9753SGrzegorz Bernacki goto error; 333e3ac9753SGrzegorz Bernacki 334e3ac9753SGrzegorz Bernacki device_add_child(self, "pci", -1); 335e3ac9753SGrzegorz Bernacki } else { 336e3ac9753SGrzegorz Bernacki sc->sc_devnr = 1; 337e3ac9753SGrzegorz Bernacki bus_space_write_4(sc->sc_bst, sc->sc_bsh, 338e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 339e3ac9753SGrzegorz Bernacki device_add_child(self, "pci_ep", -1); 340e3ac9753SGrzegorz Bernacki } 341e3ac9753SGrzegorz Bernacki 342*64dc1cf3SGrzegorz Bernacki mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 343e3ac9753SGrzegorz Bernacki return (bus_generic_attach(self)); 344e3ac9753SGrzegorz Bernacki 345e3ac9753SGrzegorz Bernacki error: 346e3ac9753SGrzegorz Bernacki /* XXX SYS_RES_ should be released here */ 347e3ac9753SGrzegorz Bernacki rman_fini(&sc->sc_mem_rman); 348e3ac9753SGrzegorz Bernacki rman_fini(&sc->sc_io_rman); 349e3ac9753SGrzegorz Bernacki 350e3ac9753SGrzegorz Bernacki return (err); 351e3ac9753SGrzegorz Bernacki } 352e3ac9753SGrzegorz Bernacki 353e3ac9753SGrzegorz Bernacki static void 354e3ac9753SGrzegorz Bernacki mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 355e3ac9753SGrzegorz Bernacki { 356e3ac9753SGrzegorz Bernacki uint32_t val; 357e3ac9753SGrzegorz Bernacki #if !defined(SOC_MV_ARMADAXP) 358e3ac9753SGrzegorz Bernacki int timeout; 359e3ac9753SGrzegorz Bernacki 360e3ac9753SGrzegorz Bernacki /* 361e3ac9753SGrzegorz Bernacki * Check if PCIE device is enabled. 362e3ac9753SGrzegorz Bernacki */ 363e3ac9753SGrzegorz Bernacki if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 364e3ac9753SGrzegorz Bernacki write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 365e3ac9753SGrzegorz Bernacki ~(CPU_CONTROL_PCIE_DISABLE(unit))); 366e3ac9753SGrzegorz Bernacki 367e3ac9753SGrzegorz Bernacki timeout = PCIE_LINK_TIMEOUT; 368e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 369e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS); 370e3ac9753SGrzegorz Bernacki while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 371e3ac9753SGrzegorz Bernacki DELAY(1000); 372e3ac9753SGrzegorz Bernacki timeout -= 1000; 373e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 374e3ac9753SGrzegorz Bernacki PCIE_REG_STATUS); 375e3ac9753SGrzegorz Bernacki } 376e3ac9753SGrzegorz Bernacki } 377e3ac9753SGrzegorz Bernacki #endif 378e3ac9753SGrzegorz Bernacki 379e3ac9753SGrzegorz Bernacki 380e3ac9753SGrzegorz Bernacki if (sc->sc_mode == MV_MODE_ROOT) { 381e3ac9753SGrzegorz Bernacki /* 382db5ef4fcSRafal Jaworowski * Enable PCI bridge. 383db5ef4fcSRafal Jaworowski */ 384e3ac9753SGrzegorz Bernacki val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 385e3ac9753SGrzegorz Bernacki val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 386e3ac9753SGrzegorz Bernacki PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 387e3ac9753SGrzegorz Bernacki bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 388e3ac9753SGrzegorz Bernacki } 389e3ac9753SGrzegorz Bernacki } 390db5ef4fcSRafal Jaworowski 391e3ac9753SGrzegorz Bernacki static int 392e3ac9753SGrzegorz Bernacki mv_pcib_mem_init(struct mv_pcib_softc *sc) 393e3ac9753SGrzegorz Bernacki { 394e3ac9753SGrzegorz Bernacki int err; 395db5ef4fcSRafal Jaworowski 396e3ac9753SGrzegorz Bernacki /* 397e3ac9753SGrzegorz Bernacki * Memory management. 398e3ac9753SGrzegorz Bernacki */ 399db5ef4fcSRafal Jaworowski sc->sc_mem_rman.rm_type = RMAN_ARRAY; 400db5ef4fcSRafal Jaworowski err = rman_init(&sc->sc_mem_rman); 401db5ef4fcSRafal Jaworowski if (err) 402db5ef4fcSRafal Jaworowski return (err); 403db5ef4fcSRafal Jaworowski 404db5ef4fcSRafal Jaworowski sc->sc_io_rman.rm_type = RMAN_ARRAY; 405db5ef4fcSRafal Jaworowski err = rman_init(&sc->sc_io_rman); 406db5ef4fcSRafal Jaworowski if (err) { 407db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_mem_rman); 408db5ef4fcSRafal Jaworowski return (err); 409db5ef4fcSRafal Jaworowski } 410db5ef4fcSRafal Jaworowski 411db5ef4fcSRafal Jaworowski err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 412db5ef4fcSRafal Jaworowski sc->sc_mem_base + sc->sc_mem_size - 1); 413db5ef4fcSRafal Jaworowski if (err) 414db5ef4fcSRafal Jaworowski goto error; 415db5ef4fcSRafal Jaworowski 416db5ef4fcSRafal Jaworowski err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 417db5ef4fcSRafal Jaworowski sc->sc_io_base + sc->sc_io_size - 1); 418db5ef4fcSRafal Jaworowski if (err) 419db5ef4fcSRafal Jaworowski goto error; 420db5ef4fcSRafal Jaworowski 421e3ac9753SGrzegorz Bernacki return (0); 422db5ef4fcSRafal Jaworowski 423db5ef4fcSRafal Jaworowski error: 424db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_mem_rman); 425db5ef4fcSRafal Jaworowski rman_fini(&sc->sc_io_rman); 426e3ac9753SGrzegorz Bernacki 427db5ef4fcSRafal Jaworowski return (err); 428db5ef4fcSRafal Jaworowski } 429db5ef4fcSRafal Jaworowski 430e3ac9753SGrzegorz Bernacki static inline uint32_t 431e3ac9753SGrzegorz Bernacki pcib_bit_get(uint32_t *map, uint32_t bit) 432e3ac9753SGrzegorz Bernacki { 433e3ac9753SGrzegorz Bernacki uint32_t n = bit / BITS_PER_UINT32; 434e3ac9753SGrzegorz Bernacki 435e3ac9753SGrzegorz Bernacki bit = bit % BITS_PER_UINT32; 436e3ac9753SGrzegorz Bernacki return (map[n] & (1 << bit)); 437e3ac9753SGrzegorz Bernacki } 438e3ac9753SGrzegorz Bernacki 439e3ac9753SGrzegorz Bernacki static inline void 440e3ac9753SGrzegorz Bernacki pcib_bit_set(uint32_t *map, uint32_t bit) 441e3ac9753SGrzegorz Bernacki { 442e3ac9753SGrzegorz Bernacki uint32_t n = bit / BITS_PER_UINT32; 443e3ac9753SGrzegorz Bernacki 444e3ac9753SGrzegorz Bernacki bit = bit % BITS_PER_UINT32; 445e3ac9753SGrzegorz Bernacki map[n] |= (1 << bit); 446e3ac9753SGrzegorz Bernacki } 447e3ac9753SGrzegorz Bernacki 448e3ac9753SGrzegorz Bernacki static inline uint32_t 449e3ac9753SGrzegorz Bernacki pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 450e3ac9753SGrzegorz Bernacki { 451e3ac9753SGrzegorz Bernacki uint32_t i; 452e3ac9753SGrzegorz Bernacki 453e3ac9753SGrzegorz Bernacki for (i = start; i < start + bits; i++) 454e3ac9753SGrzegorz Bernacki if (pcib_bit_get(map, i)) 455e3ac9753SGrzegorz Bernacki return (0); 456e3ac9753SGrzegorz Bernacki 457e3ac9753SGrzegorz Bernacki return (1); 458e3ac9753SGrzegorz Bernacki } 459e3ac9753SGrzegorz Bernacki 460e3ac9753SGrzegorz Bernacki static inline void 461e3ac9753SGrzegorz Bernacki pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 462e3ac9753SGrzegorz Bernacki { 463e3ac9753SGrzegorz Bernacki uint32_t i; 464e3ac9753SGrzegorz Bernacki 465e3ac9753SGrzegorz Bernacki for (i = start; i < start + bits; i++) 466e3ac9753SGrzegorz Bernacki pcib_bit_set(map, i); 467e3ac9753SGrzegorz Bernacki } 468e3ac9753SGrzegorz Bernacki 469e3ac9753SGrzegorz Bernacki /* 470e3ac9753SGrzegorz Bernacki * The idea of this allocator is taken from ARM No-Cache memory 471e3ac9753SGrzegorz Bernacki * management code (sys/arm/arm/vm_machdep.c). 472e3ac9753SGrzegorz Bernacki */ 473e3ac9753SGrzegorz Bernacki static bus_addr_t 474e3ac9753SGrzegorz Bernacki pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 475e3ac9753SGrzegorz Bernacki { 476e3ac9753SGrzegorz Bernacki uint32_t bits, bits_limit, i, *map, min_alloc, size; 477e3ac9753SGrzegorz Bernacki bus_addr_t addr = 0; 478e3ac9753SGrzegorz Bernacki bus_addr_t base; 479e3ac9753SGrzegorz Bernacki 480e3ac9753SGrzegorz Bernacki if (smask & 1) { 481e3ac9753SGrzegorz Bernacki base = sc->sc_io_base; 482e3ac9753SGrzegorz Bernacki min_alloc = PCI_MIN_IO_ALLOC; 483e3ac9753SGrzegorz Bernacki bits_limit = sc->sc_io_size / min_alloc; 484e3ac9753SGrzegorz Bernacki map = sc->sc_io_map; 485e3ac9753SGrzegorz Bernacki smask &= ~0x3; 486e3ac9753SGrzegorz Bernacki } else { 487e3ac9753SGrzegorz Bernacki base = sc->sc_mem_base; 488e3ac9753SGrzegorz Bernacki min_alloc = PCI_MIN_MEM_ALLOC; 489e3ac9753SGrzegorz Bernacki bits_limit = sc->sc_mem_size / min_alloc; 490e3ac9753SGrzegorz Bernacki map = sc->sc_mem_map; 491e3ac9753SGrzegorz Bernacki smask &= ~0xF; 492e3ac9753SGrzegorz Bernacki } 493e3ac9753SGrzegorz Bernacki 494e3ac9753SGrzegorz Bernacki size = ~smask + 1; 495e3ac9753SGrzegorz Bernacki bits = size / min_alloc; 496e3ac9753SGrzegorz Bernacki 497e3ac9753SGrzegorz Bernacki for (i = 0; i + bits <= bits_limit; i += bits) 498e3ac9753SGrzegorz Bernacki if (pcib_map_check(map, i, bits)) { 499e3ac9753SGrzegorz Bernacki pcib_map_set(map, i, bits); 500e3ac9753SGrzegorz Bernacki addr = base + (i * min_alloc); 501e3ac9753SGrzegorz Bernacki return (addr); 502e3ac9753SGrzegorz Bernacki } 503e3ac9753SGrzegorz Bernacki 504e3ac9753SGrzegorz Bernacki return (addr); 505e3ac9753SGrzegorz Bernacki } 506e3ac9753SGrzegorz Bernacki 507db5ef4fcSRafal Jaworowski static int 508db5ef4fcSRafal Jaworowski mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 509db5ef4fcSRafal Jaworowski int barno) 510db5ef4fcSRafal Jaworowski { 511e3ac9753SGrzegorz Bernacki uint32_t addr, bar; 512db5ef4fcSRafal Jaworowski int reg, width; 513db5ef4fcSRafal Jaworowski 514db5ef4fcSRafal Jaworowski reg = PCIR_BAR(barno); 515e3ac9753SGrzegorz Bernacki 516e3ac9753SGrzegorz Bernacki /* 517e3ac9753SGrzegorz Bernacki * Need to init the BAR register with 0xffffffff before correct 518e3ac9753SGrzegorz Bernacki * value can be read. 519e3ac9753SGrzegorz Bernacki */ 520e3ac9753SGrzegorz Bernacki mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 521db5ef4fcSRafal Jaworowski bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 522db5ef4fcSRafal Jaworowski if (bar == 0) 523db5ef4fcSRafal Jaworowski return (1); 524db5ef4fcSRafal Jaworowski 525db5ef4fcSRafal Jaworowski /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 526db5ef4fcSRafal Jaworowski width = ((bar & 7) == 4) ? 2 : 1; 527db5ef4fcSRafal Jaworowski 528e3ac9753SGrzegorz Bernacki addr = pcib_alloc(sc, bar); 529e3ac9753SGrzegorz Bernacki if (!addr) 530db5ef4fcSRafal Jaworowski return (-1); 531db5ef4fcSRafal Jaworowski 532db5ef4fcSRafal Jaworowski if (bootverbose) 533e3ac9753SGrzegorz Bernacki printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 534e3ac9753SGrzegorz Bernacki bus, slot, func, reg, bar, addr); 535db5ef4fcSRafal Jaworowski 536db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 537db5ef4fcSRafal Jaworowski if (width == 2) 538db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 539db5ef4fcSRafal Jaworowski 0, 4); 540db5ef4fcSRafal Jaworowski 541db5ef4fcSRafal Jaworowski return (width); 5426975124cSRafal Jaworowski } 5436975124cSRafal Jaworowski 5446975124cSRafal Jaworowski static void 545db5ef4fcSRafal Jaworowski mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 546db5ef4fcSRafal Jaworowski { 547db5ef4fcSRafal Jaworowski bus_addr_t io_base, mem_base; 548db5ef4fcSRafal Jaworowski uint32_t io_limit, mem_limit; 549db5ef4fcSRafal Jaworowski int secbus; 550db5ef4fcSRafal Jaworowski 551db5ef4fcSRafal Jaworowski io_base = sc->sc_io_base; 552db5ef4fcSRafal Jaworowski io_limit = io_base + sc->sc_io_size - 1; 553db5ef4fcSRafal Jaworowski mem_base = sc->sc_mem_base; 554db5ef4fcSRafal Jaworowski mem_limit = mem_base + sc->sc_mem_size - 1; 555db5ef4fcSRafal Jaworowski 556db5ef4fcSRafal Jaworowski /* Configure I/O decode registers */ 557db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 558db5ef4fcSRafal Jaworowski io_base >> 8, 1); 559db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 560db5ef4fcSRafal Jaworowski io_base >> 16, 2); 561db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 562db5ef4fcSRafal Jaworowski io_limit >> 8, 1); 563db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 564db5ef4fcSRafal Jaworowski io_limit >> 16, 2); 565db5ef4fcSRafal Jaworowski 566db5ef4fcSRafal Jaworowski /* Configure memory decode registers */ 567db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 568db5ef4fcSRafal Jaworowski mem_base >> 16, 2); 569db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 570db5ef4fcSRafal Jaworowski mem_limit >> 16, 2); 571db5ef4fcSRafal Jaworowski 572db5ef4fcSRafal Jaworowski /* Disable memory prefetch decode */ 573db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 574db5ef4fcSRafal Jaworowski 0x10, 2); 575db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 576db5ef4fcSRafal Jaworowski 0x0, 4); 577db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 578db5ef4fcSRafal Jaworowski 0xF, 2); 579db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 580db5ef4fcSRafal Jaworowski 0x0, 4); 581db5ef4fcSRafal Jaworowski 582db5ef4fcSRafal Jaworowski secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 583db5ef4fcSRafal Jaworowski PCIR_SECBUS_1, 1); 584db5ef4fcSRafal Jaworowski 585db5ef4fcSRafal Jaworowski /* Configure buses behind the bridge */ 586db5ef4fcSRafal Jaworowski mv_pcib_init(sc, secbus, PCI_SLOTMAX); 587db5ef4fcSRafal Jaworowski } 588db5ef4fcSRafal Jaworowski 589db5ef4fcSRafal Jaworowski static int 590db5ef4fcSRafal Jaworowski mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 591db5ef4fcSRafal Jaworowski { 592db5ef4fcSRafal Jaworowski int slot, func, maxfunc, error; 593db5ef4fcSRafal Jaworowski uint8_t hdrtype, command, class, subclass; 594db5ef4fcSRafal Jaworowski 595db5ef4fcSRafal Jaworowski for (slot = 0; slot <= maxslot; slot++) { 596db5ef4fcSRafal Jaworowski maxfunc = 0; 597db5ef4fcSRafal Jaworowski for (func = 0; func <= maxfunc; func++) { 598db5ef4fcSRafal Jaworowski hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 599db5ef4fcSRafal Jaworowski func, PCIR_HDRTYPE, 1); 600db5ef4fcSRafal Jaworowski 601db5ef4fcSRafal Jaworowski if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 602db5ef4fcSRafal Jaworowski continue; 603db5ef4fcSRafal Jaworowski 604db5ef4fcSRafal Jaworowski if (func == 0 && (hdrtype & PCIM_MFDEV)) 605db5ef4fcSRafal Jaworowski maxfunc = PCI_FUNCMAX; 606db5ef4fcSRafal Jaworowski 607db5ef4fcSRafal Jaworowski command = mv_pcib_read_config(sc->sc_dev, bus, slot, 608db5ef4fcSRafal Jaworowski func, PCIR_COMMAND, 1); 609db5ef4fcSRafal Jaworowski command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 610db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, 611db5ef4fcSRafal Jaworowski PCIR_COMMAND, command, 1); 612db5ef4fcSRafal Jaworowski 613db5ef4fcSRafal Jaworowski error = mv_pcib_init_all_bars(sc, bus, slot, func, 614db5ef4fcSRafal Jaworowski hdrtype); 615db5ef4fcSRafal Jaworowski 616db5ef4fcSRafal Jaworowski if (error) 617db5ef4fcSRafal Jaworowski return (error); 618db5ef4fcSRafal Jaworowski 619db5ef4fcSRafal Jaworowski command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 620db5ef4fcSRafal Jaworowski PCIM_CMD_PORTEN; 621db5ef4fcSRafal Jaworowski mv_pcib_write_config(sc->sc_dev, bus, slot, func, 622db5ef4fcSRafal Jaworowski PCIR_COMMAND, command, 1); 623db5ef4fcSRafal Jaworowski 624db5ef4fcSRafal Jaworowski /* Handle PCI-PCI bridges */ 625db5ef4fcSRafal Jaworowski class = mv_pcib_read_config(sc->sc_dev, bus, slot, 626db5ef4fcSRafal Jaworowski func, PCIR_CLASS, 1); 627db5ef4fcSRafal Jaworowski subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 628db5ef4fcSRafal Jaworowski func, PCIR_SUBCLASS, 1); 629db5ef4fcSRafal Jaworowski 630db5ef4fcSRafal Jaworowski if (class != PCIC_BRIDGE || 631db5ef4fcSRafal Jaworowski subclass != PCIS_BRIDGE_PCI) 632db5ef4fcSRafal Jaworowski continue; 633db5ef4fcSRafal Jaworowski 634db5ef4fcSRafal Jaworowski mv_pcib_init_bridge(sc, bus, slot, func); 635db5ef4fcSRafal Jaworowski } 636db5ef4fcSRafal Jaworowski } 637db5ef4fcSRafal Jaworowski 638db5ef4fcSRafal Jaworowski /* Enable all ABCD interrupts */ 639db5ef4fcSRafal Jaworowski pcib_write_irq_mask(sc, (0xF << 24)); 640db5ef4fcSRafal Jaworowski 641db5ef4fcSRafal Jaworowski return (0); 642db5ef4fcSRafal Jaworowski } 643db5ef4fcSRafal Jaworowski 644db5ef4fcSRafal Jaworowski static int 645db5ef4fcSRafal Jaworowski mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 646db5ef4fcSRafal Jaworowski int func, int hdrtype) 647db5ef4fcSRafal Jaworowski { 648db5ef4fcSRafal Jaworowski int maxbar, bar, i; 649db5ef4fcSRafal Jaworowski 650db5ef4fcSRafal Jaworowski maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 651db5ef4fcSRafal Jaworowski bar = 0; 652db5ef4fcSRafal Jaworowski 653db5ef4fcSRafal Jaworowski /* Program the base address registers */ 654db5ef4fcSRafal Jaworowski while (bar < maxbar) { 655db5ef4fcSRafal Jaworowski i = mv_pcib_init_bar(sc, bus, slot, func, bar); 656db5ef4fcSRafal Jaworowski bar += i; 657db5ef4fcSRafal Jaworowski if (i < 0) { 658db5ef4fcSRafal Jaworowski device_printf(sc->sc_dev, 659db5ef4fcSRafal Jaworowski "PCI IO/Memory space exhausted\n"); 660db5ef4fcSRafal Jaworowski return (ENOMEM); 661db5ef4fcSRafal Jaworowski } 662db5ef4fcSRafal Jaworowski } 663db5ef4fcSRafal Jaworowski 664db5ef4fcSRafal Jaworowski return (0); 665db5ef4fcSRafal Jaworowski } 666db5ef4fcSRafal Jaworowski 667db5ef4fcSRafal Jaworowski static struct resource * 668db5ef4fcSRafal Jaworowski mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 669db5ef4fcSRafal Jaworowski u_long start, u_long end, u_long count, u_int flags) 670db5ef4fcSRafal Jaworowski { 671db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 672db5ef4fcSRafal Jaworowski struct rman *rm = NULL; 673db5ef4fcSRafal Jaworowski struct resource *res; 674db5ef4fcSRafal Jaworowski 675db5ef4fcSRafal Jaworowski switch (type) { 676db5ef4fcSRafal Jaworowski case SYS_RES_IOPORT: 677db5ef4fcSRafal Jaworowski rm = &sc->sc_io_rman; 678db5ef4fcSRafal Jaworowski break; 679db5ef4fcSRafal Jaworowski case SYS_RES_MEMORY: 680db5ef4fcSRafal Jaworowski rm = &sc->sc_mem_rman; 681db5ef4fcSRafal Jaworowski break; 682db5ef4fcSRafal Jaworowski default: 683e3ac9753SGrzegorz Bernacki return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 684db5ef4fcSRafal Jaworowski type, rid, start, end, count, flags)); 685db5ef4fcSRafal Jaworowski }; 686db5ef4fcSRafal Jaworowski 687e3ac9753SGrzegorz Bernacki if ((start == 0UL) && (end == ~0UL)) { 688e3ac9753SGrzegorz Bernacki start = sc->sc_mem_base; 689e3ac9753SGrzegorz Bernacki end = sc->sc_mem_base + sc->sc_mem_size - 1; 690e3ac9753SGrzegorz Bernacki count = sc->sc_mem_size; 691e3ac9753SGrzegorz Bernacki } 692e3ac9753SGrzegorz Bernacki 693e3ac9753SGrzegorz Bernacki if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 694e3ac9753SGrzegorz Bernacki (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 695e3ac9753SGrzegorz Bernacki return (NULL); 696e3ac9753SGrzegorz Bernacki 697db5ef4fcSRafal Jaworowski res = rman_reserve_resource(rm, start, end, count, flags, child); 698db5ef4fcSRafal Jaworowski if (res == NULL) 699db5ef4fcSRafal Jaworowski return (NULL); 700db5ef4fcSRafal Jaworowski 701db5ef4fcSRafal Jaworowski rman_set_rid(res, *rid); 702db5ef4fcSRafal Jaworowski rman_set_bustag(res, fdtbus_bs_tag); 703db5ef4fcSRafal Jaworowski rman_set_bushandle(res, start); 704db5ef4fcSRafal Jaworowski 705db5ef4fcSRafal Jaworowski if (flags & RF_ACTIVE) 706db5ef4fcSRafal Jaworowski if (bus_activate_resource(child, type, *rid, res)) { 707db5ef4fcSRafal Jaworowski rman_release_resource(res); 708db5ef4fcSRafal Jaworowski return (NULL); 709db5ef4fcSRafal Jaworowski } 710db5ef4fcSRafal Jaworowski 711db5ef4fcSRafal Jaworowski return (res); 712db5ef4fcSRafal Jaworowski } 713db5ef4fcSRafal Jaworowski 714db5ef4fcSRafal Jaworowski static int 715db5ef4fcSRafal Jaworowski mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 716db5ef4fcSRafal Jaworowski struct resource *res) 717db5ef4fcSRafal Jaworowski { 718db5ef4fcSRafal Jaworowski 719db5ef4fcSRafal Jaworowski if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 720db5ef4fcSRafal Jaworowski return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 721db5ef4fcSRafal Jaworowski type, rid, res)); 722db5ef4fcSRafal Jaworowski 723db5ef4fcSRafal Jaworowski return (rman_release_resource(res)); 724db5ef4fcSRafal Jaworowski } 725db5ef4fcSRafal Jaworowski 726db5ef4fcSRafal Jaworowski static int 727db5ef4fcSRafal Jaworowski mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 728db5ef4fcSRafal Jaworowski { 729db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 730db5ef4fcSRafal Jaworowski 731db5ef4fcSRafal Jaworowski switch (which) { 732db5ef4fcSRafal Jaworowski case PCIB_IVAR_BUS: 733db5ef4fcSRafal Jaworowski *result = sc->sc_busnr; 734db5ef4fcSRafal Jaworowski return (0); 735db5ef4fcSRafal Jaworowski case PCIB_IVAR_DOMAIN: 736db5ef4fcSRafal Jaworowski *result = device_get_unit(dev); 737db5ef4fcSRafal Jaworowski return (0); 738db5ef4fcSRafal Jaworowski } 739db5ef4fcSRafal Jaworowski 740db5ef4fcSRafal Jaworowski return (ENOENT); 741db5ef4fcSRafal Jaworowski } 742db5ef4fcSRafal Jaworowski 743db5ef4fcSRafal Jaworowski static int 744db5ef4fcSRafal Jaworowski mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 745db5ef4fcSRafal Jaworowski { 746db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 747db5ef4fcSRafal Jaworowski 748db5ef4fcSRafal Jaworowski switch (which) { 749db5ef4fcSRafal Jaworowski case PCIB_IVAR_BUS: 750db5ef4fcSRafal Jaworowski sc->sc_busnr = value; 751db5ef4fcSRafal Jaworowski return (0); 752db5ef4fcSRafal Jaworowski } 753db5ef4fcSRafal Jaworowski 754db5ef4fcSRafal Jaworowski return (ENOENT); 755db5ef4fcSRafal Jaworowski } 756db5ef4fcSRafal Jaworowski 757db5ef4fcSRafal Jaworowski static inline void 758db5ef4fcSRafal Jaworowski pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 759db5ef4fcSRafal Jaworowski { 760db5ef4fcSRafal Jaworowski 761db5ef4fcSRafal Jaworowski if (!sc->sc_type != MV_TYPE_PCI) 762db5ef4fcSRafal Jaworowski return; 763db5ef4fcSRafal Jaworowski 764db5ef4fcSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 765db5ef4fcSRafal Jaworowski } 766db5ef4fcSRafal Jaworowski 767db5ef4fcSRafal Jaworowski static void 768db5ef4fcSRafal Jaworowski mv_pcib_hw_cfginit(void) 7696975124cSRafal Jaworowski { 7706975124cSRafal Jaworowski static int opened = 0; 7716975124cSRafal Jaworowski 7726975124cSRafal Jaworowski if (opened) 7736975124cSRafal Jaworowski return; 7746975124cSRafal Jaworowski 7756975124cSRafal Jaworowski mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 7766975124cSRafal Jaworowski opened = 1; 7776975124cSRafal Jaworowski } 7786975124cSRafal Jaworowski 7796975124cSRafal Jaworowski static uint32_t 780db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 7816975124cSRafal Jaworowski u_int func, u_int reg, int bytes) 7826975124cSRafal Jaworowski { 7836975124cSRafal Jaworowski uint32_t addr, data, ca, cd; 7846975124cSRafal Jaworowski 785db5ef4fcSRafal Jaworowski ca = (sc->sc_type != MV_TYPE_PCI) ? 7866975124cSRafal Jaworowski PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 787db5ef4fcSRafal Jaworowski cd = (sc->sc_type != MV_TYPE_PCI) ? 7886975124cSRafal Jaworowski PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 7896975124cSRafal Jaworowski addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 7906975124cSRafal Jaworowski PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 7916975124cSRafal Jaworowski 7926975124cSRafal Jaworowski mtx_lock_spin(&pcicfg_mtx); 7936975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 7946975124cSRafal Jaworowski 7956975124cSRafal Jaworowski data = ~0; 7966975124cSRafal Jaworowski switch (bytes) { 7976975124cSRafal Jaworowski case 1: 7986975124cSRafal Jaworowski data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 7996975124cSRafal Jaworowski cd + (reg & 3)); 8006975124cSRafal Jaworowski break; 8016975124cSRafal Jaworowski case 2: 8026975124cSRafal Jaworowski data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 8036975124cSRafal Jaworowski cd + (reg & 2))); 8046975124cSRafal Jaworowski break; 8056975124cSRafal Jaworowski case 4: 8066975124cSRafal Jaworowski data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 8076975124cSRafal Jaworowski cd)); 8086975124cSRafal Jaworowski break; 8096975124cSRafal Jaworowski } 8106975124cSRafal Jaworowski mtx_unlock_spin(&pcicfg_mtx); 8116975124cSRafal Jaworowski return (data); 8126975124cSRafal Jaworowski } 8136975124cSRafal Jaworowski 8146975124cSRafal Jaworowski static void 815db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 8166975124cSRafal Jaworowski u_int func, u_int reg, uint32_t data, int bytes) 8176975124cSRafal Jaworowski { 8186975124cSRafal Jaworowski uint32_t addr, ca, cd; 8196975124cSRafal Jaworowski 820db5ef4fcSRafal Jaworowski ca = (sc->sc_type != MV_TYPE_PCI) ? 8216975124cSRafal Jaworowski PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 822db5ef4fcSRafal Jaworowski cd = (sc->sc_type != MV_TYPE_PCI) ? 8236975124cSRafal Jaworowski PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 8246975124cSRafal Jaworowski addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 8256975124cSRafal Jaworowski PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 8266975124cSRafal Jaworowski 8276975124cSRafal Jaworowski mtx_lock_spin(&pcicfg_mtx); 8286975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 8296975124cSRafal Jaworowski 8306975124cSRafal Jaworowski switch (bytes) { 8316975124cSRafal Jaworowski case 1: 8326975124cSRafal Jaworowski bus_space_write_1(sc->sc_bst, sc->sc_bsh, 8336975124cSRafal Jaworowski cd + (reg & 3), data); 8346975124cSRafal Jaworowski break; 8356975124cSRafal Jaworowski case 2: 8366975124cSRafal Jaworowski bus_space_write_2(sc->sc_bst, sc->sc_bsh, 8376975124cSRafal Jaworowski cd + (reg & 2), htole16(data)); 8386975124cSRafal Jaworowski break; 8396975124cSRafal Jaworowski case 4: 8406975124cSRafal Jaworowski bus_space_write_4(sc->sc_bst, sc->sc_bsh, 8416975124cSRafal Jaworowski cd, htole32(data)); 8426975124cSRafal Jaworowski break; 8436975124cSRafal Jaworowski } 8446975124cSRafal Jaworowski mtx_unlock_spin(&pcicfg_mtx); 8456975124cSRafal Jaworowski } 8466975124cSRafal Jaworowski 8476975124cSRafal Jaworowski static int 848db5ef4fcSRafal Jaworowski mv_pcib_maxslots(device_t dev) 8496975124cSRafal Jaworowski { 850db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 8516975124cSRafal Jaworowski 852db5ef4fcSRafal Jaworowski return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 8536975124cSRafal Jaworowski } 8546975124cSRafal Jaworowski 8556975124cSRafal Jaworowski static uint32_t 856db5ef4fcSRafal Jaworowski mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 8576975124cSRafal Jaworowski u_int reg, int bytes) 8586975124cSRafal Jaworowski { 859db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 8606975124cSRafal Jaworowski 861e3ac9753SGrzegorz Bernacki /* Return ~0 if link is inactive or trying to read from Root */ 862e3ac9753SGrzegorz Bernacki if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 863e3ac9753SGrzegorz Bernacki PCIE_STATUS_LINK_DOWN) || (slot == 0)) 8646975124cSRafal Jaworowski return (~0U); 8656975124cSRafal Jaworowski 866db5ef4fcSRafal Jaworowski return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 8676975124cSRafal Jaworowski } 8686975124cSRafal Jaworowski 8696975124cSRafal Jaworowski static void 870db5ef4fcSRafal Jaworowski mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 8716975124cSRafal Jaworowski u_int reg, uint32_t val, int bytes) 8726975124cSRafal Jaworowski { 873db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc = device_get_softc(dev); 8746975124cSRafal Jaworowski 875e3ac9753SGrzegorz Bernacki /* Return if link is inactive or trying to write to Root */ 876e3ac9753SGrzegorz Bernacki if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 877e3ac9753SGrzegorz Bernacki PCIE_STATUS_LINK_DOWN) || (slot == 0)) 8786975124cSRafal Jaworowski return; 8796975124cSRafal Jaworowski 880db5ef4fcSRafal Jaworowski mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 8816975124cSRafal Jaworowski } 8826975124cSRafal Jaworowski 883db5ef4fcSRafal Jaworowski static int 884db5ef4fcSRafal Jaworowski mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin) 8856975124cSRafal Jaworowski { 886db5ef4fcSRafal Jaworowski struct mv_pcib_softc *sc; 887db5ef4fcSRafal Jaworowski int err, interrupt; 888db5ef4fcSRafal Jaworowski 889db5ef4fcSRafal Jaworowski sc = device_get_softc(pcib); 890db5ef4fcSRafal Jaworowski 891db5ef4fcSRafal Jaworowski err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev), 892db5ef4fcSRafal Jaworowski pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt); 893db5ef4fcSRafal Jaworowski if (err == 0) 894db5ef4fcSRafal Jaworowski return (interrupt); 895db5ef4fcSRafal Jaworowski 896db5ef4fcSRafal Jaworowski device_printf(pcib, "could not route pin %d for device %d.%d\n", 897db5ef4fcSRafal Jaworowski pin, pci_get_slot(dev), pci_get_function(dev)); 898db5ef4fcSRafal Jaworowski return (PCI_INVALID_IRQ); 899db5ef4fcSRafal Jaworowski } 900db5ef4fcSRafal Jaworowski 901db5ef4fcSRafal Jaworowski static int 902db5ef4fcSRafal Jaworowski mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 903db5ef4fcSRafal Jaworowski { 904db5ef4fcSRafal Jaworowski struct fdt_pci_range io_space, mem_space; 905db5ef4fcSRafal Jaworowski device_t dev; 9066975124cSRafal Jaworowski int error; 9076975124cSRafal Jaworowski 908db5ef4fcSRafal Jaworowski dev = sc->sc_dev; 909db5ef4fcSRafal Jaworowski 910db5ef4fcSRafal Jaworowski if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 911db5ef4fcSRafal Jaworowski device_printf(dev, "could not retrieve 'ranges' data\n"); 912db5ef4fcSRafal Jaworowski return (error); 913db5ef4fcSRafal Jaworowski } 914db5ef4fcSRafal Jaworowski 9156975124cSRafal Jaworowski /* Configure CPU decoding windows */ 916e3ac9753SGrzegorz Bernacki error = decode_win_cpu_set(sc->sc_win_target, 917e3ac9753SGrzegorz Bernacki sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 9186975124cSRafal Jaworowski if (error < 0) { 919db5ef4fcSRafal Jaworowski device_printf(dev, "could not set up CPU decode " 9206975124cSRafal Jaworowski "window for PCI IO\n"); 921db5ef4fcSRafal Jaworowski return (ENXIO); 9226975124cSRafal Jaworowski } 923e3ac9753SGrzegorz Bernacki error = decode_win_cpu_set(sc->sc_win_target, 924e3ac9753SGrzegorz Bernacki sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 925e3ac9753SGrzegorz Bernacki mem_space.base_parent); 9266975124cSRafal Jaworowski if (error < 0) { 927db5ef4fcSRafal Jaworowski device_printf(dev, "could not set up CPU decode " 9286975124cSRafal Jaworowski "windows for PCI MEM\n"); 929db5ef4fcSRafal Jaworowski return (ENXIO); 9306975124cSRafal Jaworowski } 9316975124cSRafal Jaworowski 932db5ef4fcSRafal Jaworowski sc->sc_io_base = io_space.base_parent; 933db5ef4fcSRafal Jaworowski sc->sc_io_size = io_space.len; 934db5ef4fcSRafal Jaworowski 935db5ef4fcSRafal Jaworowski sc->sc_mem_base = mem_space.base_parent; 936db5ef4fcSRafal Jaworowski sc->sc_mem_size = mem_space.len; 937db5ef4fcSRafal Jaworowski 938db5ef4fcSRafal Jaworowski return (0); 9396975124cSRafal Jaworowski } 9406975124cSRafal Jaworowski 941db5ef4fcSRafal Jaworowski static int 942db5ef4fcSRafal Jaworowski mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc) 9436975124cSRafal Jaworowski { 944db5ef4fcSRafal Jaworowski int error; 9456975124cSRafal Jaworowski 946db5ef4fcSRafal Jaworowski if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0) 947db5ef4fcSRafal Jaworowski return (error); 9486975124cSRafal Jaworowski 949db5ef4fcSRafal Jaworowski return (0); 9506975124cSRafal Jaworowski } 9516975124cSRafal Jaworowski 952*64dc1cf3SGrzegorz Bernacki #if defined(SOC_MV_ARMADAXP) 953*64dc1cf3SGrzegorz Bernacki static int 954*64dc1cf3SGrzegorz Bernacki mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 955*64dc1cf3SGrzegorz Bernacki uint32_t *data) 956*64dc1cf3SGrzegorz Bernacki { 957*64dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc; 958*64dc1cf3SGrzegorz Bernacki 959*64dc1cf3SGrzegorz Bernacki sc = device_get_softc(dev); 960*64dc1cf3SGrzegorz Bernacki irq = irq - MSI_IRQ; 961*64dc1cf3SGrzegorz Bernacki 962*64dc1cf3SGrzegorz Bernacki /* validate parameters */ 963*64dc1cf3SGrzegorz Bernacki if (isclr(&sc->sc_msi_bitmap, irq)) { 964*64dc1cf3SGrzegorz Bernacki device_printf(dev, "invalid MSI 0x%x\n", irq); 965*64dc1cf3SGrzegorz Bernacki return (EINVAL); 966*64dc1cf3SGrzegorz Bernacki } 967*64dc1cf3SGrzegorz Bernacki 968*64dc1cf3SGrzegorz Bernacki mv_msi_data(irq, addr, data); 969*64dc1cf3SGrzegorz Bernacki 970*64dc1cf3SGrzegorz Bernacki debugf("%s: irq: %d addr: %jx data: %x\n", 971*64dc1cf3SGrzegorz Bernacki __func__, irq, *addr, *data); 972*64dc1cf3SGrzegorz Bernacki 973*64dc1cf3SGrzegorz Bernacki return (0); 974*64dc1cf3SGrzegorz Bernacki } 975*64dc1cf3SGrzegorz Bernacki 976*64dc1cf3SGrzegorz Bernacki static int 977*64dc1cf3SGrzegorz Bernacki mv_pcib_alloc_msi(device_t dev, device_t child, int count, 978*64dc1cf3SGrzegorz Bernacki int maxcount __unused, int *irqs) 979*64dc1cf3SGrzegorz Bernacki { 980*64dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc; 981*64dc1cf3SGrzegorz Bernacki u_int start = 0, i; 982*64dc1cf3SGrzegorz Bernacki 983*64dc1cf3SGrzegorz Bernacki if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 984*64dc1cf3SGrzegorz Bernacki return (EINVAL); 985*64dc1cf3SGrzegorz Bernacki 986*64dc1cf3SGrzegorz Bernacki sc = device_get_softc(dev); 987*64dc1cf3SGrzegorz Bernacki mtx_lock(&sc->sc_msi_mtx); 988*64dc1cf3SGrzegorz Bernacki 989*64dc1cf3SGrzegorz Bernacki for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 990*64dc1cf3SGrzegorz Bernacki for (i = start; i < start + count; i++) { 991*64dc1cf3SGrzegorz Bernacki if (isset(&sc->sc_msi_bitmap, i)) 992*64dc1cf3SGrzegorz Bernacki break; 993*64dc1cf3SGrzegorz Bernacki } 994*64dc1cf3SGrzegorz Bernacki if (i == start + count) 995*64dc1cf3SGrzegorz Bernacki break; 996*64dc1cf3SGrzegorz Bernacki } 997*64dc1cf3SGrzegorz Bernacki 998*64dc1cf3SGrzegorz Bernacki if ((start + count) == MSI_IRQ_NUM) { 999*64dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx); 1000*64dc1cf3SGrzegorz Bernacki return (ENXIO); 1001*64dc1cf3SGrzegorz Bernacki } 1002*64dc1cf3SGrzegorz Bernacki 1003*64dc1cf3SGrzegorz Bernacki for (i = start; i < start + count; i++) { 1004*64dc1cf3SGrzegorz Bernacki setbit(&sc->sc_msi_bitmap, i); 1005*64dc1cf3SGrzegorz Bernacki irqs[i] = MSI_IRQ + i; 1006*64dc1cf3SGrzegorz Bernacki } 1007*64dc1cf3SGrzegorz Bernacki debugf("%s: start: %x count: %x\n", __func__, start, count); 1008*64dc1cf3SGrzegorz Bernacki 1009*64dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx); 1010*64dc1cf3SGrzegorz Bernacki return (0); 1011*64dc1cf3SGrzegorz Bernacki } 1012*64dc1cf3SGrzegorz Bernacki 1013*64dc1cf3SGrzegorz Bernacki static int 1014*64dc1cf3SGrzegorz Bernacki mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1015*64dc1cf3SGrzegorz Bernacki { 1016*64dc1cf3SGrzegorz Bernacki struct mv_pcib_softc *sc; 1017*64dc1cf3SGrzegorz Bernacki u_int i; 1018*64dc1cf3SGrzegorz Bernacki 1019*64dc1cf3SGrzegorz Bernacki sc = device_get_softc(dev); 1020*64dc1cf3SGrzegorz Bernacki mtx_lock(&sc->sc_msi_mtx); 1021*64dc1cf3SGrzegorz Bernacki 1022*64dc1cf3SGrzegorz Bernacki for (i = 0; i < count; i++) 1023*64dc1cf3SGrzegorz Bernacki clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1024*64dc1cf3SGrzegorz Bernacki 1025*64dc1cf3SGrzegorz Bernacki mtx_unlock(&sc->sc_msi_mtx); 1026*64dc1cf3SGrzegorz Bernacki return (0); 1027*64dc1cf3SGrzegorz Bernacki } 1028*64dc1cf3SGrzegorz Bernacki #endif 1029