1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/rman.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 39 #include <machine/bus.h> 40 #include <machine/resource.h> 41 #include <machine/intr.h> 42 43 #include <dev/extres/clk/clk_fixed.h> 44 #include <dev/extres/clk/clk_gate.h> 45 #include <dev/extres/syscon/syscon.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <arm/mv/mv_cp110_clock.h> 51 52 #include "clkdev_if.h" 53 #include "syscon_if.h" 54 55 /* Clocks */ 56 static struct clk_fixed_def cp110_clk_pll_0 = { 57 .clkdef.id = CP110_PLL_0, 58 .freq = 1000000000, 59 }; 60 61 static const char *clk_parents_0[] = {"cp110-pll0-0"}; 62 static const char *clk_parents_1[] = {"cp110-pll0-1"}; 63 64 static struct clk_fixed_def cp110_clk_ppv2_core = { 65 .clkdef.id = CP110_PPV2_CORE, 66 .clkdef.parent_cnt = 1, 67 .mult = 1, 68 .div = 3, 69 }; 70 71 static struct clk_fixed_def cp110_clk_x2core = { 72 .clkdef.id = CP110_X2CORE, 73 .clkdef.parent_cnt = 1, 74 .mult = 1, 75 .div = 2, 76 }; 77 78 static const char *core_parents_0[] = {"cp110-x2core-0"}; 79 static const char *core_parents_1[] = {"cp110-x2core-1"}; 80 81 static struct clk_fixed_def cp110_clk_core = { 82 .clkdef.id = CP110_CORE, 83 .clkdef.parent_cnt = 1, 84 .mult = 1, 85 .div = 2, 86 }; 87 88 static struct clk_fixed_def cp110_clk_sdio = { 89 .clkdef.id = CP110_SDIO, 90 .clkdef.parent_cnt = 1, 91 .mult = 2, 92 .div = 5, 93 }; 94 95 /* Gates */ 96 97 static struct cp110_gate cp110_gates[] = { 98 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0) 99 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1) 100 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */ 101 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3) 102 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4) 103 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5) 104 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6) 105 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7) 106 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8) 107 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9) 108 CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11) 109 CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12) 110 CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13) 111 CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14) 112 CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15) 113 CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16) 114 CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17) 115 CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18) 116 CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21) 117 CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22) 118 CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23) 119 CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24) 120 CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25) 121 CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26) 122 }; 123 124 struct mv_cp110_clock_softc { 125 device_t dev; 126 struct syscon *syscon; 127 struct mtx mtx; 128 }; 129 130 static struct ofw_compat_data compat_data[] = { 131 {"marvell,cp110-clock", 1}, 132 {NULL, 0} 133 }; 134 135 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) 136 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) 137 138 static char * 139 mv_cp110_clock_name(device_t dev, const char *name) 140 { 141 char *clkname = NULL; 142 int unit; 143 144 unit = device_get_unit(dev); 145 if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0) 146 panic("Cannot generate unique clock name for %s\n", name); 147 return (clkname); 148 } 149 150 static int 151 mv_cp110_clock_probe(device_t dev) 152 { 153 154 if (!ofw_bus_status_okay(dev)) 155 return (ENXIO); 156 157 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 158 return (ENXIO); 159 160 device_set_desc(dev, "Marvell CP110 Clock Controller"); 161 return (BUS_PROBE_DEFAULT); 162 } 163 164 static int 165 cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells, 166 phandle_t *cells, struct clknode **clk) 167 { 168 int id = 0; 169 170 if (ncells != 2) 171 return (ENXIO); 172 173 id = cells[1]; 174 if (cells[0] == 1) 175 id += CP110_MAX_CLOCK; 176 177 *clk = clknode_find_by_id(clkdom, id); 178 179 return (0); 180 } 181 182 static int 183 mv_cp110_clock_attach(device_t dev) 184 { 185 struct mv_cp110_clock_softc *sc; 186 struct clkdom *clkdom; 187 struct clk_gate_def def; 188 char *pll0_name; 189 int unit, i; 190 191 sc = device_get_softc(dev); 192 sc->dev = dev; 193 194 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || 195 sc->syscon == NULL) { 196 device_printf(dev, "cannot get syscon for device\n"); 197 return (ENXIO); 198 } 199 200 unit = device_get_unit(dev); 201 if (unit > 1) { 202 device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit); 203 return (ENXIO); 204 } 205 206 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 207 208 clkdom = clkdom_create(dev); 209 clkdom_set_ofw_mapper(clkdom, cp110_ofw_map); 210 211 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0"); 212 cp110_clk_pll_0.clkdef.name = pll0_name; 213 clknode_fixed_register(clkdom, &cp110_clk_pll_0); 214 215 cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2"); 216 cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 217 clknode_fixed_register(clkdom, &cp110_clk_ppv2_core); 218 219 cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core"); 220 cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 221 clknode_fixed_register(clkdom, &cp110_clk_x2core); 222 223 cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core"); 224 cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1; 225 clknode_fixed_register(clkdom, &cp110_clk_core); 226 227 /* NAND missing */ 228 229 cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio"); 230 cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 231 clknode_fixed_register(clkdom, &cp110_clk_sdio); 232 233 for (i = 0; i < nitems(cp110_gates); i++) { 234 if (cp110_gates[i].name == NULL) 235 continue; 236 237 memset(&def, 0, sizeof(def)); 238 def.clkdef.id = CP110_MAX_CLOCK + i; 239 def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name); 240 def.clkdef.parent_cnt = 1; 241 def.offset = CP110_CLOCK_GATING_OFFSET; 242 def.shift = cp110_gates[i].shift; 243 def.mask = 1; 244 def.on_value = 1; 245 def.off_value = 0; 246 247 switch (i) { 248 case CP110_GATE_MG: 249 case CP110_GATE_GOP_DP: 250 case CP110_GATE_PPV2: 251 def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name; 252 break; 253 case CP110_GATE_SDIO: 254 def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name; 255 break; 256 case CP110_GATE_MAIN: 257 case CP110_GATE_PCIE_XOR: 258 case CP110_GATE_PCIE_X4: 259 case CP110_GATE_EIP150: 260 case CP110_GATE_EIP197: 261 def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name; 262 break; 263 default: 264 def.clkdef.parent_names = &cp110_clk_core.clkdef.name; 265 break; 266 } 267 268 clknode_gate_register(clkdom, &def); 269 } 270 271 clkdom_finit(clkdom); 272 273 if (bootverbose) 274 clkdom_dump(clkdom); 275 276 return (0); 277 } 278 279 static int 280 mv_cp110_clock_detach(device_t dev) 281 { 282 283 return (EBUSY); 284 } 285 286 static int 287 mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val) 288 { 289 struct mv_cp110_clock_softc *sc; 290 291 sc = device_get_softc(dev); 292 WR4(sc, addr, val); 293 return (0); 294 } 295 296 static int 297 mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 298 { 299 struct mv_cp110_clock_softc *sc; 300 301 sc = device_get_softc(dev); 302 303 *val = RD4(sc, addr); 304 return (0); 305 } 306 307 static int 308 mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) 309 { 310 struct mv_cp110_clock_softc *sc; 311 uint32_t reg; 312 313 sc = device_get_softc(dev); 314 315 reg = RD4(sc, addr); 316 reg &= ~clr; 317 reg |= set; 318 WR4(sc, addr, reg); 319 320 return (0); 321 } 322 323 static void 324 mv_cp110_clock_device_lock(device_t dev) 325 { 326 struct mv_cp110_clock_softc *sc; 327 328 sc = device_get_softc(dev); 329 mtx_lock(&sc->mtx); 330 } 331 332 static void 333 mv_cp110_clock_device_unlock(device_t dev) 334 { 335 struct mv_cp110_clock_softc *sc; 336 337 sc = device_get_softc(dev); 338 mtx_unlock(&sc->mtx); 339 } 340 341 static device_method_t mv_cp110_clock_methods[] = { 342 /* Device interface */ 343 DEVMETHOD(device_probe, mv_cp110_clock_probe), 344 DEVMETHOD(device_attach, mv_cp110_clock_attach), 345 DEVMETHOD(device_detach, mv_cp110_clock_detach), 346 347 /* clkdev interface */ 348 DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4), 349 DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4), 350 DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4), 351 DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock), 352 DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock), 353 354 DEVMETHOD_END 355 }; 356 357 static driver_t mv_cp110_clock_driver = { 358 "mv_cp110_clock", 359 mv_cp110_clock_methods, 360 sizeof(struct mv_cp110_clock_softc), 361 }; 362 363 EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver, 0, 0, 364 BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 365