1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/rman.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <machine/intr.h> 44 45 #include <dev/extres/clk/clk_fixed.h> 46 #include <dev/extres/clk/clk_gate.h> 47 #include <dev/extres/syscon/syscon.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <arm/mv/mv_cp110_clock.h> 53 54 #include "clkdev_if.h" 55 #include "syscon_if.h" 56 57 /* Clocks */ 58 static struct clk_fixed_def cp110_clk_pll_0 = { 59 .clkdef.id = CP110_PLL_0, 60 .freq = 1000000000, 61 }; 62 63 static const char *clk_parents_0[] = {"cp110-pll0-0"}; 64 static const char *clk_parents_1[] = {"cp110-pll0-1"}; 65 66 static struct clk_fixed_def cp110_clk_ppv2_core = { 67 .clkdef.id = CP110_PPV2_CORE, 68 .clkdef.parent_cnt = 1, 69 .mult = 1, 70 .div = 3, 71 }; 72 73 static struct clk_fixed_def cp110_clk_x2core = { 74 .clkdef.id = CP110_X2CORE, 75 .clkdef.parent_cnt = 1, 76 .mult = 1, 77 .div = 2, 78 }; 79 80 static const char *core_parents_0[] = {"cp110-x2core-0"}; 81 static const char *core_parents_1[] = {"cp110-x2core-1"}; 82 83 static struct clk_fixed_def cp110_clk_core = { 84 .clkdef.id = CP110_CORE, 85 .clkdef.parent_cnt = 1, 86 .mult = 1, 87 .div = 2, 88 }; 89 90 static struct clk_fixed_def cp110_clk_sdio = { 91 .clkdef.id = CP110_SDIO, 92 .clkdef.parent_cnt = 1, 93 .mult = 2, 94 .div = 5, 95 }; 96 97 /* Gates */ 98 99 static struct cp110_gate cp110_gates[] = { 100 CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0) 101 CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1) 102 /* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */ 103 CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3) 104 CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4) 105 CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5) 106 CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6) 107 CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7) 108 CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8) 109 CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9) 110 CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11) 111 CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12) 112 CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13) 113 CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14) 114 CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15) 115 CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16) 116 CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17) 117 CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18) 118 CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21) 119 CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22) 120 CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23) 121 CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24) 122 CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25) 123 CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26) 124 }; 125 126 struct mv_cp110_clock_softc { 127 device_t dev; 128 struct syscon *syscon; 129 struct mtx mtx; 130 }; 131 132 static struct ofw_compat_data compat_data[] = { 133 {"marvell,cp110-clock", 1}, 134 {NULL, 0} 135 }; 136 137 #define RD4(sc, reg) SYSCON_READ_4((sc)->syscon, (reg)) 138 #define WR4(sc, reg, val) SYSCON_WRITE_4((sc)->syscon, (reg), (val)) 139 140 static char * 141 mv_cp110_clock_name(device_t dev, const char *name) 142 { 143 char *clkname = NULL; 144 int unit; 145 146 unit = device_get_unit(dev); 147 if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0) 148 panic("Cannot generate unique clock name for %s\n", name); 149 return (clkname); 150 } 151 152 static int 153 mv_cp110_clock_probe(device_t dev) 154 { 155 156 if (!ofw_bus_status_okay(dev)) 157 return (ENXIO); 158 159 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 160 return (ENXIO); 161 162 device_set_desc(dev, "Marvell CP110 Clock Controller"); 163 return (BUS_PROBE_DEFAULT); 164 } 165 166 static int 167 cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells, 168 phandle_t *cells, struct clknode **clk) 169 { 170 int id = 0; 171 172 if (ncells != 2) 173 return (ENXIO); 174 175 id = cells[1]; 176 if (cells[0] == 1) 177 id += CP110_MAX_CLOCK; 178 179 *clk = clknode_find_by_id(clkdom, id); 180 181 return (0); 182 } 183 184 static int 185 mv_cp110_clock_attach(device_t dev) 186 { 187 struct mv_cp110_clock_softc *sc; 188 struct clkdom *clkdom; 189 struct clk_gate_def def; 190 char *pll0_name; 191 int unit, i; 192 193 sc = device_get_softc(dev); 194 sc->dev = dev; 195 196 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || 197 sc->syscon == NULL) { 198 device_printf(dev, "cannot get syscon for device\n"); 199 return (ENXIO); 200 } 201 202 unit = device_get_unit(dev); 203 if (unit > 1) { 204 device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit); 205 return (ENXIO); 206 } 207 208 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 209 210 clkdom = clkdom_create(dev); 211 clkdom_set_ofw_mapper(clkdom, cp110_ofw_map); 212 213 pll0_name = mv_cp110_clock_name(dev, "cp110-pll0"); 214 cp110_clk_pll_0.clkdef.name = pll0_name; 215 clknode_fixed_register(clkdom, &cp110_clk_pll_0); 216 217 cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2"); 218 cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 219 clknode_fixed_register(clkdom, &cp110_clk_ppv2_core); 220 221 cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core"); 222 cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 223 clknode_fixed_register(clkdom, &cp110_clk_x2core); 224 225 cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core"); 226 cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1; 227 clknode_fixed_register(clkdom, &cp110_clk_core); 228 229 /* NAND missing */ 230 231 cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio"); 232 cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1; 233 clknode_fixed_register(clkdom, &cp110_clk_sdio); 234 235 for (i = 0; i < nitems(cp110_gates); i++) { 236 if (cp110_gates[i].name == NULL) 237 continue; 238 239 memset(&def, 0, sizeof(def)); 240 def.clkdef.id = CP110_MAX_CLOCK + i; 241 def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name); 242 def.clkdef.parent_cnt = 1; 243 def.offset = CP110_CLOCK_GATING_OFFSET; 244 def.shift = cp110_gates[i].shift; 245 def.mask = 1; 246 def.on_value = 1; 247 def.off_value = 0; 248 249 switch (i) { 250 case CP110_GATE_MG: 251 case CP110_GATE_GOP_DP: 252 case CP110_GATE_PPV2: 253 def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name; 254 break; 255 case CP110_GATE_SDIO: 256 def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name; 257 break; 258 case CP110_GATE_MAIN: 259 case CP110_GATE_PCIE_XOR: 260 case CP110_GATE_PCIE_X4: 261 case CP110_GATE_EIP150: 262 case CP110_GATE_EIP197: 263 def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name; 264 break; 265 default: 266 def.clkdef.parent_names = &cp110_clk_core.clkdef.name; 267 break; 268 } 269 270 clknode_gate_register(clkdom, &def); 271 } 272 273 clkdom_finit(clkdom); 274 275 if (bootverbose) 276 clkdom_dump(clkdom); 277 278 return (0); 279 } 280 281 static int 282 mv_cp110_clock_detach(device_t dev) 283 { 284 285 return (EBUSY); 286 } 287 288 static int 289 mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val) 290 { 291 struct mv_cp110_clock_softc *sc; 292 293 sc = device_get_softc(dev); 294 WR4(sc, addr, val); 295 return (0); 296 } 297 298 static int 299 mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 300 { 301 struct mv_cp110_clock_softc *sc; 302 303 sc = device_get_softc(dev); 304 305 *val = RD4(sc, addr); 306 return (0); 307 } 308 309 static int 310 mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) 311 { 312 struct mv_cp110_clock_softc *sc; 313 uint32_t reg; 314 315 sc = device_get_softc(dev); 316 317 reg = RD4(sc, addr); 318 reg &= ~clr; 319 reg |= set; 320 WR4(sc, addr, reg); 321 322 return (0); 323 } 324 325 static void 326 mv_cp110_clock_device_lock(device_t dev) 327 { 328 struct mv_cp110_clock_softc *sc; 329 330 sc = device_get_softc(dev); 331 mtx_lock(&sc->mtx); 332 } 333 334 static void 335 mv_cp110_clock_device_unlock(device_t dev) 336 { 337 struct mv_cp110_clock_softc *sc; 338 339 sc = device_get_softc(dev); 340 mtx_unlock(&sc->mtx); 341 } 342 343 static device_method_t mv_cp110_clock_methods[] = { 344 /* Device interface */ 345 DEVMETHOD(device_probe, mv_cp110_clock_probe), 346 DEVMETHOD(device_attach, mv_cp110_clock_attach), 347 DEVMETHOD(device_detach, mv_cp110_clock_detach), 348 349 /* clkdev interface */ 350 DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4), 351 DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4), 352 DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4), 353 DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock), 354 DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock), 355 356 DEVMETHOD_END 357 }; 358 359 static driver_t mv_cp110_clock_driver = { 360 "mv_cp110_clock", 361 mv_cp110_clock_methods, 362 sizeof(struct mv_cp110_clock_softc), 363 }; 364 365 EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver, 0, 0, 366 BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 367