1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 #ifndef SOC_MV_FREY 80 static int decode_win_cpu_valid(void); 81 #endif 82 static int decode_win_usb_valid(void); 83 static int decode_win_usb3_valid(void); 84 static int decode_win_eth_valid(void); 85 static int decode_win_pcie_valid(void); 86 static int decode_win_sata_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 #ifndef SOC_MV_FREY 92 static void decode_win_cpu_setup(void); 93 #endif 94 #ifdef SOC_MV_ARMADAXP 95 static int decode_win_sdram_fixup(void); 96 #endif 97 static void decode_win_usb_setup(u_long); 98 static void decode_win_usb3_setup(u_long); 99 static void decode_win_eth_setup(u_long); 100 static void decode_win_sata_setup(u_long); 101 static void decode_win_ahci_setup(u_long); 102 103 static void decode_win_idma_setup(u_long); 104 static void decode_win_xor_setup(u_long); 105 106 static void decode_win_usb_dump(u_long); 107 static void decode_win_usb3_dump(u_long); 108 static void decode_win_eth_dump(u_long base); 109 static void decode_win_idma_dump(u_long base); 110 static void decode_win_xor_dump(u_long base); 111 static void decode_win_ahci_dump(u_long base); 112 113 static int fdt_get_ranges(const char *, void *, int, int *, int *); 114 #ifdef SOC_MV_ARMADA38X 115 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 116 int *trig, int *pol); 117 #endif 118 119 static int win_cpu_from_dt(void); 120 static int fdt_win_setup(void); 121 122 static uint32_t dev_mask = 0; 123 static int cpu_wins_no = 0; 124 static int eth_port = 0; 125 static int usb_port = 0; 126 127 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 128 129 const struct decode_win *cpu_wins = cpu_win_tbl; 130 131 typedef void (*decode_win_setup_t)(u_long); 132 typedef void (*dump_win_t)(u_long); 133 134 struct soc_node_spec { 135 const char *compat; 136 decode_win_setup_t decode_handler; 137 dump_win_t dump_handler; 138 }; 139 140 static struct soc_node_spec soc_nodes[] = { 141 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 142 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 143 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 144 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 145 { "mrvl,sata", &decode_win_sata_setup, NULL }, 146 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 147 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 148 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 149 { NULL, NULL, NULL }, 150 }; 151 152 struct fdt_pm_mask_entry { 153 char *compat; 154 uint32_t mask; 155 }; 156 157 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 158 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 159 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 160 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 161 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 162 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 163 { "mrvl,xor", CPU_PM_CTRL_XOR }, 164 { "mrvl,sata", CPU_PM_CTRL_SATA }, 165 166 { NULL, 0 } 167 }; 168 169 static __inline int 170 pm_is_disabled(uint32_t mask) 171 { 172 #if defined(SOC_MV_KIRKWOOD) 173 return (soc_power_ctrl_get(mask) == mask); 174 #else 175 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 176 #endif 177 } 178 179 /* 180 * Disable device using power management register. 181 * 1 - Device Power On 182 * 0 - Device Power Off 183 * Mask can be set in loader. 184 * EXAMPLE: 185 * loader> set hw.pm-disable-mask=0x2 186 * 187 * Common mask: 188 * |-------------------------------| 189 * | Device | Kirkwood | Discovery | 190 * |-------------------------------| 191 * | USB0 | 0x00008 | 0x020000 | 192 * |-------------------------------| 193 * | USB1 | - | 0x040000 | 194 * |-------------------------------| 195 * | USB2 | - | 0x080000 | 196 * |-------------------------------| 197 * | GE0 | 0x00001 | 0x000002 | 198 * |-------------------------------| 199 * | GE1 | - | 0x000004 | 200 * |-------------------------------| 201 * | IDMA | - | 0x100000 | 202 * |-------------------------------| 203 * | XOR | 0x10000 | 0x200000 | 204 * |-------------------------------| 205 * | CESA | 0x20000 | 0x400000 | 206 * |-------------------------------| 207 * | SATA | 0x04000 | 0x004000 | 208 * --------------------------------| 209 * This feature can be used only on Kirkwood and Discovery 210 * machines. 211 */ 212 static __inline void 213 pm_disable_device(int mask) 214 { 215 #ifdef DIAGNOSTIC 216 uint32_t reg; 217 218 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 219 printf("Power Management Register: 0%x\n", reg); 220 221 reg &= ~mask; 222 soc_power_ctrl_set(reg); 223 printf("Device %x is disabled\n", mask); 224 225 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 226 printf("Power Management Register: 0%x\n", reg); 227 #endif 228 } 229 230 int 231 fdt_pm(phandle_t node) 232 { 233 uint32_t cpu_pm_ctrl; 234 int i, ena, compat; 235 236 ena = 1; 237 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 238 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 239 if (dev_mask & (1 << i)) 240 continue; 241 242 compat = ofw_bus_node_is_compatible(node, 243 fdt_pm_mask_table[i].compat); 244 #if defined(SOC_MV_KIRKWOOD) 245 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 246 dev_mask |= (1 << i); 247 ena = 0; 248 break; 249 } else if (compat) { 250 dev_mask |= (1 << i); 251 break; 252 } 253 #else 254 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 255 dev_mask |= (1 << i); 256 ena = 0; 257 break; 258 } else if (compat) { 259 dev_mask |= (1 << i); 260 break; 261 } 262 #endif 263 } 264 265 return (ena); 266 } 267 268 uint32_t 269 read_cpu_ctrl(uint32_t reg) 270 { 271 272 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 273 } 274 275 void 276 write_cpu_ctrl(uint32_t reg, uint32_t val) 277 { 278 279 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 280 } 281 282 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 283 uint32_t 284 read_cpu_mp_clocks(uint32_t reg) 285 { 286 287 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 288 } 289 290 void 291 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 292 { 293 294 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 295 } 296 297 uint32_t 298 read_cpu_misc(uint32_t reg) 299 { 300 301 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 302 } 303 304 void 305 write_cpu_misc(uint32_t reg, uint32_t val) 306 { 307 308 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 309 } 310 #endif 311 312 void 313 cpu_reset(void) 314 { 315 316 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 317 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 318 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 319 #else 320 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 321 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 322 #endif 323 while (1); 324 } 325 326 uint32_t 327 cpu_extra_feat(void) 328 { 329 uint32_t dev, rev; 330 uint32_t ef = 0; 331 332 soc_id(&dev, &rev); 333 334 switch (dev) { 335 case MV_DEV_88F6281: 336 case MV_DEV_88F6282: 337 case MV_DEV_88RC8180: 338 case MV_DEV_MV78100_Z0: 339 case MV_DEV_MV78100: 340 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 341 break; 342 case MV_DEV_88F5182: 343 case MV_DEV_88F5281: 344 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 345 break; 346 default: 347 if (bootverbose) 348 printf("This ARM Core does not support any extra features\n"); 349 } 350 351 return (ef); 352 } 353 354 /* 355 * Get the power status of device. This feature is only supported on 356 * Kirkwood and Discovery SoCs. 357 */ 358 uint32_t 359 soc_power_ctrl_get(uint32_t mask) 360 { 361 362 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY) 363 if (mask != CPU_PM_CTRL_NONE) 364 mask &= read_cpu_ctrl(CPU_PM_CTRL); 365 366 return (mask); 367 #else 368 return (mask); 369 #endif 370 } 371 372 /* 373 * Set the power status of device. This feature is only supported on 374 * Kirkwood and Discovery SoCs. 375 */ 376 void 377 soc_power_ctrl_set(uint32_t mask) 378 { 379 380 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) 381 if (mask != CPU_PM_CTRL_NONE) 382 write_cpu_ctrl(CPU_PM_CTRL, mask); 383 #endif 384 } 385 386 void 387 soc_id(uint32_t *dev, uint32_t *rev) 388 { 389 390 /* 391 * Notice: system identifiers are available in the registers range of 392 * PCIE controller, so using this function is only allowed (and 393 * possible) after the internal registers range has been mapped in via 394 * devmap_bootstrap(). 395 */ 396 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 397 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 398 } 399 400 static void 401 soc_identify(void) 402 { 403 uint32_t d, r, size, mode; 404 const char *dev; 405 const char *rev; 406 407 soc_id(&d, &r); 408 409 printf("SOC: "); 410 if (bootverbose) 411 printf("(0x%4x:0x%02x) ", d, r); 412 413 rev = ""; 414 switch (d) { 415 case MV_DEV_88F5181: 416 dev = "Marvell 88F5181"; 417 if (r == 3) 418 rev = "B1"; 419 break; 420 case MV_DEV_88F5182: 421 dev = "Marvell 88F5182"; 422 if (r == 2) 423 rev = "A2"; 424 break; 425 case MV_DEV_88F5281: 426 dev = "Marvell 88F5281"; 427 if (r == 4) 428 rev = "D0"; 429 else if (r == 5) 430 rev = "D1"; 431 else if (r == 6) 432 rev = "D2"; 433 break; 434 case MV_DEV_88F6281: 435 dev = "Marvell 88F6281"; 436 if (r == 0) 437 rev = "Z0"; 438 else if (r == 2) 439 rev = "A0"; 440 else if (r == 3) 441 rev = "A1"; 442 break; 443 case MV_DEV_88RC8180: 444 dev = "Marvell 88RC8180"; 445 break; 446 case MV_DEV_88RC9480: 447 dev = "Marvell 88RC9480"; 448 break; 449 case MV_DEV_88RC9580: 450 dev = "Marvell 88RC9580"; 451 break; 452 case MV_DEV_88F6781: 453 dev = "Marvell 88F6781"; 454 if (r == 2) 455 rev = "Y0"; 456 break; 457 case MV_DEV_88F6282: 458 dev = "Marvell 88F6282"; 459 if (r == 0) 460 rev = "A0"; 461 else if (r == 1) 462 rev = "A1"; 463 break; 464 case MV_DEV_88F6828: 465 dev = "Marvell 88F6828"; 466 break; 467 case MV_DEV_88F6820: 468 dev = "Marvell 88F6820"; 469 break; 470 case MV_DEV_88F6810: 471 dev = "Marvell 88F6810"; 472 break; 473 case MV_DEV_MV78100_Z0: 474 dev = "Marvell MV78100 Z0"; 475 break; 476 case MV_DEV_MV78100: 477 dev = "Marvell MV78100"; 478 break; 479 case MV_DEV_MV78160: 480 dev = "Marvell MV78160"; 481 break; 482 case MV_DEV_MV78260: 483 dev = "Marvell MV78260"; 484 break; 485 case MV_DEV_MV78460: 486 dev = "Marvell MV78460"; 487 break; 488 default: 489 dev = "UNKNOWN"; 490 break; 491 } 492 493 printf("%s", dev); 494 if (*rev != '\0') 495 printf(" rev %s", rev); 496 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 497 498 mode = read_cpu_ctrl(CPU_CONFIG); 499 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 500 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 501 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 502 503 switch (d) { 504 case MV_DEV_88F6281: 505 case MV_DEV_88F6282: 506 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 507 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 508 mode ? "write-through" : "write-back"); 509 break; 510 case MV_DEV_MV78100: 511 mode = read_cpu_ctrl(CPU_CONTROL); 512 size = mode & CPU_CONTROL_L2_SIZE; 513 mode = mode & CPU_CONTROL_L2_MODE; 514 printf(" %s set-associative %s unified L2 cache\n", 515 size ? "256KB 4-way" : "512KB 8-way", 516 mode ? "write-through" : "write-back"); 517 break; 518 default: 519 break; 520 } 521 } 522 523 static void 524 platform_identify(void *dummy) 525 { 526 527 soc_identify(); 528 529 /* 530 * XXX Board identification e.g. read out from FPGA or similar should 531 * go here 532 */ 533 } 534 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 535 NULL); 536 537 #ifdef KDB 538 static void 539 mv_enter_debugger(void *dummy) 540 { 541 542 if (boothowto & RB_KDB) 543 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 544 } 545 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 546 #endif 547 548 int 549 soc_decode_win(void) 550 { 551 uint32_t dev, rev; 552 int mask, err; 553 554 mask = 0; 555 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 556 557 if (mask != 0) 558 pm_disable_device(mask); 559 560 /* Retrieve data about physical addresses from device tree. */ 561 if ((err = win_cpu_from_dt()) != 0) 562 return (err); 563 564 /* Retrieve our ID: some windows facilities vary between SoC models */ 565 soc_id(&dev, &rev); 566 567 #ifdef SOC_MV_ARMADAXP 568 if ((err = decode_win_sdram_fixup()) != 0) 569 return(err); 570 #endif 571 572 #ifndef SOC_MV_FREY 573 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 574 !decode_win_eth_valid() || !decode_win_idma_valid() || 575 !decode_win_pcie_valid() || !decode_win_sata_valid() || 576 !decode_win_xor_valid() || !decode_win_usb3_valid()) 577 return (EINVAL); 578 579 decode_win_cpu_setup(); 580 #else 581 if (!decode_win_usb_valid() || 582 !decode_win_eth_valid() || !decode_win_idma_valid() || 583 !decode_win_pcie_valid() || !decode_win_sata_valid() || 584 !decode_win_xor_valid() || !decode_win_usb3_valid()) 585 return (EINVAL); 586 #endif 587 if (MV_DUMP_WIN) 588 soc_dump_decode_win(); 589 590 eth_port = 0; 591 usb_port = 0; 592 if ((err = fdt_win_setup()) != 0) 593 return (err); 594 595 return (0); 596 } 597 598 /************************************************************************** 599 * Decode windows registers accessors 600 **************************************************************************/ 601 #if !defined(SOC_MV_FREY) 602 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 603 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 604 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 605 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 606 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 607 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 608 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 609 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 610 #endif 611 612 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 613 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 614 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 615 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 616 617 #ifdef SOC_MV_ARMADA38X 618 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 619 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 620 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 621 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 622 #endif 623 624 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 625 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 626 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 627 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 628 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 629 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 630 631 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 632 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 633 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 634 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 635 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 636 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 637 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 638 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 639 640 WIN_REG_BASE_RD(win_eth, bare, 0x290) 641 WIN_REG_BASE_RD(win_eth, epap, 0x294) 642 WIN_REG_BASE_WR(win_eth, bare, 0x290) 643 WIN_REG_BASE_WR(win_eth, epap, 0x294) 644 645 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 646 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 647 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 648 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 649 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 650 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 651 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 652 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 653 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 654 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 655 656 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 657 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 658 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 659 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 660 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 661 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 662 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 663 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 664 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 665 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 666 667 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 668 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 669 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 670 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 671 #if defined(SOC_MV_ARMADA38X) 672 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 673 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 674 #endif 675 676 #ifndef SOC_MV_DOVE 677 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 678 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 679 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 680 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 681 #else 682 /* 683 * On 88F6781 (Dove) SoC DDR Controller is accessed through 684 * single MBUS <-> AXI bridge. In this case we provide emulated 685 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 686 * with common decoding windows setup code. 687 */ 688 689 static inline uint32_t ddr_br_read(int i) 690 { 691 uint32_t mmap; 692 693 /* Read Memory Address Map Register for CS i */ 694 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 695 696 /* Return CS i base address */ 697 return (mmap & 0xFF000000); 698 } 699 700 static inline uint32_t ddr_sz_read(int i) 701 { 702 uint32_t mmap, size; 703 704 /* Read Memory Address Map Register for CS i */ 705 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 706 707 /* Extract size of CS space in 64kB units */ 708 size = (1 << ((mmap >> 16) & 0x0F)); 709 710 /* Return CS size and enable/disable status */ 711 return (((size - 1) << 16) | (mmap & 0x01)); 712 } 713 #endif 714 715 #if !defined(SOC_MV_FREY) 716 /************************************************************************** 717 * Decode windows helper routines 718 **************************************************************************/ 719 void 720 soc_dump_decode_win(void) 721 { 722 uint32_t dev, rev; 723 int i; 724 725 soc_id(&dev, &rev); 726 727 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 728 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 729 win_cpu_cr_read(i), 730 win_cpu_br_read(i)); 731 732 if (win_cpu_can_remap(i)) 733 printf(", rl 0x%08x, rh 0x%08x", 734 win_cpu_remap_l_read(i), 735 win_cpu_remap_h_read(i)); 736 737 printf("\n"); 738 } 739 printf("Internal regs base: 0x%08x\n", 740 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 741 742 for (i = 0; i < MV_WIN_DDR_MAX; i++) 743 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 744 ddr_br_read(i), ddr_sz_read(i)); 745 } 746 747 /************************************************************************** 748 * CPU windows routines 749 **************************************************************************/ 750 int 751 win_cpu_can_remap(int i) 752 { 753 uint32_t dev, rev; 754 755 soc_id(&dev, &rev); 756 757 /* Depending on the SoC certain windows have remap capability */ 758 if ((dev == MV_DEV_88F5182 && i < 2) || 759 (dev == MV_DEV_88F5281 && i < 4) || 760 (dev == MV_DEV_88F6281 && i < 4) || 761 (dev == MV_DEV_88F6282 && i < 4) || 762 (dev == MV_DEV_88F6828 && i < 20) || 763 (dev == MV_DEV_88F6820 && i < 20) || 764 (dev == MV_DEV_88F6810 && i < 20) || 765 (dev == MV_DEV_88RC8180 && i < 2) || 766 (dev == MV_DEV_88F6781 && i < 4) || 767 (dev == MV_DEV_MV78100_Z0 && i < 8) || 768 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 769 return (1); 770 771 return (0); 772 } 773 774 /* XXX This should check for overlapping remap fields too.. */ 775 int 776 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 777 { 778 const struct decode_win *tab; 779 int i; 780 781 tab = wintab; 782 783 for (i = 0; i < win_no; i++, tab++) { 784 if (i == win) 785 /* Skip self */ 786 continue; 787 788 if ((tab->base + tab->size - 1) < (wintab + win)->base) 789 continue; 790 791 else if (((wintab + win)->base + (wintab + win)->size - 1) < 792 tab->base) 793 continue; 794 else 795 return (i); 796 } 797 798 return (-1); 799 } 800 801 static int 802 decode_win_cpu_valid(void) 803 { 804 int i, j, rv; 805 uint32_t b, e, s; 806 807 if (cpu_wins_no > MV_WIN_CPU_MAX) { 808 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 809 return (0); 810 } 811 812 rv = 1; 813 for (i = 0; i < cpu_wins_no; i++) { 814 815 if (cpu_wins[i].target == 0) { 816 printf("CPU window#%d: DDR target window is not " 817 "supposed to be reprogrammed!\n", i); 818 rv = 0; 819 } 820 821 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 822 printf("CPU window#%d: not capable of remapping, but " 823 "val 0x%08x defined\n", i, cpu_wins[i].remap); 824 rv = 0; 825 } 826 827 s = cpu_wins[i].size; 828 b = cpu_wins[i].base; 829 e = b + s - 1; 830 if (s > (0xFFFFFFFF - b + 1)) { 831 /* 832 * XXX this boundary check should account for 64bit 833 * and remapping.. 834 */ 835 printf("CPU window#%d: no space for size 0x%08x at " 836 "0x%08x\n", i, s, b); 837 rv = 0; 838 continue; 839 } 840 841 if (b != rounddown2(b, s)) { 842 printf("CPU window#%d: address 0x%08x is not aligned " 843 "to 0x%08x\n", i, b, s); 844 rv = 0; 845 continue; 846 } 847 848 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 849 if (j >= 0) { 850 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 851 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 852 cpu_wins[j].base, 853 cpu_wins[j].base + cpu_wins[j].size - 1); 854 rv = 0; 855 } 856 } 857 858 return (rv); 859 } 860 861 int 862 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 863 vm_paddr_t remap) 864 { 865 uint32_t br, cr; 866 int win, i; 867 868 if (remap == ~0) { 869 win = MV_WIN_CPU_MAX - 1; 870 i = -1; 871 } else { 872 win = 0; 873 i = 1; 874 } 875 876 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 877 cr = win_cpu_cr_read(win); 878 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 879 break; 880 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 881 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 882 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 883 (target << MV_WIN_CPU_TARGET_SHIFT))) 884 break; 885 win += i; 886 } 887 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 888 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 889 return (-1); 890 891 br = base & 0xffff0000; 892 win_cpu_br_write(win, br); 893 894 if (win_cpu_can_remap(win)) { 895 if (remap != ~0) { 896 win_cpu_remap_l_write(win, remap & 0xffff0000); 897 win_cpu_remap_h_write(win, 0); 898 } else { 899 /* 900 * Remap function is not used for a given window 901 * (capable of remapping) - set remap field with the 902 * same value as base. 903 */ 904 win_cpu_remap_l_write(win, base & 0xffff0000); 905 win_cpu_remap_h_write(win, 0); 906 } 907 } 908 909 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 910 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 911 win_cpu_cr_write(win, cr); 912 913 return (0); 914 } 915 916 static void 917 decode_win_cpu_setup(void) 918 { 919 int i; 920 921 /* Disable all CPU windows */ 922 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 923 win_cpu_cr_write(i, 0); 924 win_cpu_br_write(i, 0); 925 if (win_cpu_can_remap(i)) { 926 win_cpu_remap_l_write(i, 0); 927 win_cpu_remap_h_write(i, 0); 928 } 929 } 930 931 for (i = 0; i < cpu_wins_no; i++) 932 if (cpu_wins[i].target > 0) 933 decode_win_cpu_set(cpu_wins[i].target, 934 cpu_wins[i].attr, cpu_wins[i].base, 935 cpu_wins[i].size, cpu_wins[i].remap); 936 937 } 938 #endif 939 940 #ifdef SOC_MV_ARMADAXP 941 static int 942 decode_win_sdram_fixup(void) 943 { 944 struct mem_region mr[FDT_MEM_REGIONS]; 945 uint8_t window_valid[MV_WIN_DDR_MAX]; 946 int mr_cnt, err, i, j; 947 uint32_t valid_win_num = 0; 948 949 /* Grab physical memory regions information from device tree. */ 950 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 951 if (err != 0) 952 return (err); 953 954 for (i = 0; i < MV_WIN_DDR_MAX; i++) 955 window_valid[i] = 0; 956 957 /* Try to match entries from device tree with settings from u-boot */ 958 for (i = 0; i < mr_cnt; i++) { 959 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 960 if (ddr_is_active(j) && 961 (ddr_base(j) == mr[i].mr_start) && 962 (ddr_size(j) == mr[i].mr_size)) { 963 window_valid[j] = 1; 964 valid_win_num++; 965 } 966 } 967 } 968 969 if (mr_cnt != valid_win_num) 970 return (EINVAL); 971 972 /* Destroy windows without corresponding device tree entry */ 973 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 974 if (ddr_is_active(j) && (window_valid[j] != 1)) { 975 printf("Disabling SDRAM decoding window: %d\n", j); 976 ddr_disable(j); 977 } 978 } 979 980 return (0); 981 } 982 #endif 983 /* 984 * Check if we're able to cover all active DDR banks. 985 */ 986 static int 987 decode_win_can_cover_ddr(int max) 988 { 989 int i, c; 990 991 c = 0; 992 for (i = 0; i < MV_WIN_DDR_MAX; i++) 993 if (ddr_is_active(i)) 994 c++; 995 996 if (c > max) { 997 printf("Unable to cover all active DDR banks: " 998 "%d, available windows: %d\n", c, max); 999 return (0); 1000 } 1001 1002 return (1); 1003 } 1004 1005 /************************************************************************** 1006 * DDR windows routines 1007 **************************************************************************/ 1008 int 1009 ddr_is_active(int i) 1010 { 1011 1012 if (ddr_sz_read(i) & 0x1) 1013 return (1); 1014 1015 return (0); 1016 } 1017 1018 void 1019 ddr_disable(int i) 1020 { 1021 1022 ddr_sz_write(i, 0); 1023 ddr_br_write(i, 0); 1024 } 1025 1026 uint32_t 1027 ddr_base(int i) 1028 { 1029 1030 return (ddr_br_read(i) & 0xff000000); 1031 } 1032 1033 uint32_t 1034 ddr_size(int i) 1035 { 1036 1037 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1038 } 1039 1040 uint32_t 1041 ddr_attr(int i) 1042 { 1043 uint32_t dev, rev; 1044 1045 soc_id(&dev, &rev); 1046 if (dev == MV_DEV_88RC8180) 1047 return ((ddr_sz_read(i) & 0xf0) >> 4); 1048 if (dev == MV_DEV_88F6781) 1049 return (0); 1050 1051 return (i == 0 ? 0xe : 1052 (i == 1 ? 0xd : 1053 (i == 2 ? 0xb : 1054 (i == 3 ? 0x7 : 0xff)))); 1055 } 1056 1057 uint32_t 1058 ddr_target(int i) 1059 { 1060 uint32_t dev, rev; 1061 1062 soc_id(&dev, &rev); 1063 if (dev == MV_DEV_88RC8180) { 1064 i = (ddr_sz_read(i) & 0xf0) >> 4; 1065 return (i == 0xe ? 0xc : 1066 (i == 0xd ? 0xd : 1067 (i == 0xb ? 0xe : 1068 (i == 0x7 ? 0xf : 0xc)))); 1069 } 1070 1071 /* 1072 * On SOCs other than 88RC8180 Mbus unit ID for 1073 * DDR SDRAM controller is always 0x0. 1074 */ 1075 return (0); 1076 } 1077 1078 /************************************************************************** 1079 * USB windows routines 1080 **************************************************************************/ 1081 static int 1082 decode_win_usb_valid(void) 1083 { 1084 1085 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1086 } 1087 1088 static void 1089 decode_win_usb_dump(u_long base) 1090 { 1091 int i; 1092 1093 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1094 return; 1095 1096 for (i = 0; i < MV_WIN_USB_MAX; i++) 1097 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1098 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1099 } 1100 1101 /* 1102 * Set USB decode windows. 1103 */ 1104 static void 1105 decode_win_usb_setup(u_long base) 1106 { 1107 uint32_t br, cr; 1108 int i, j; 1109 1110 1111 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1112 return; 1113 1114 usb_port++; 1115 1116 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1117 win_usb_cr_write(base, i, 0); 1118 win_usb_br_write(base, i, 0); 1119 } 1120 1121 /* Only access to active DRAM banks is required */ 1122 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1123 if (ddr_is_active(i)) { 1124 br = ddr_base(i); 1125 /* 1126 * XXX for 6281 we should handle Mbus write 1127 * burst limit field in the ctrl reg 1128 */ 1129 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1130 (ddr_attr(i) << 8) | 1131 (ddr_target(i) << 4) | 1); 1132 1133 /* Set the first free USB window */ 1134 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1135 if (win_usb_cr_read(base, j) & 0x1) 1136 continue; 1137 1138 win_usb_br_write(base, j, br); 1139 win_usb_cr_write(base, j, cr); 1140 break; 1141 } 1142 } 1143 } 1144 } 1145 1146 /************************************************************************** 1147 * USB3 windows routines 1148 **************************************************************************/ 1149 #ifdef SOC_MV_ARMADA38X 1150 static int 1151 decode_win_usb3_valid(void) 1152 { 1153 1154 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1155 } 1156 1157 static void 1158 decode_win_usb3_dump(u_long base) 1159 { 1160 int i; 1161 1162 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1163 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1164 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1165 } 1166 1167 /* 1168 * Set USB3 decode windows 1169 */ 1170 static void 1171 decode_win_usb3_setup(u_long base) 1172 { 1173 uint32_t br, cr; 1174 int i, j; 1175 1176 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1177 win_usb3_cr_write(base, i, 0); 1178 win_usb3_br_write(base, i, 0); 1179 } 1180 1181 /* Only access to active DRAM banks is required */ 1182 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1183 if (ddr_is_active(i)) { 1184 br = ddr_base(i); 1185 cr = (((ddr_size(i) - 1) & 1186 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1187 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1188 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1189 IO_WIN_ENA_MASK); 1190 1191 /* Set the first free USB3.0 window */ 1192 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1193 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1194 continue; 1195 1196 win_usb3_br_write(base, j, br); 1197 win_usb3_cr_write(base, j, cr); 1198 break; 1199 } 1200 } 1201 } 1202 } 1203 #else 1204 /* 1205 * Provide dummy functions to satisfy the build 1206 * for SoCs not equipped with USB3 1207 */ 1208 static int 1209 decode_win_usb3_valid(void) 1210 { 1211 1212 return (1); 1213 } 1214 1215 static void 1216 decode_win_usb3_setup(u_long base) 1217 { 1218 } 1219 1220 static void 1221 decode_win_usb3_dump(u_long base) 1222 { 1223 } 1224 #endif 1225 /************************************************************************** 1226 * ETH windows routines 1227 **************************************************************************/ 1228 1229 static int 1230 win_eth_can_remap(int i) 1231 { 1232 1233 /* ETH encode windows 0-3 have remap capability */ 1234 if (i < 4) 1235 return (1); 1236 1237 return (0); 1238 } 1239 1240 static int 1241 eth_bare_read(uint32_t base, int i) 1242 { 1243 uint32_t v; 1244 1245 v = win_eth_bare_read(base); 1246 v &= (1 << i); 1247 1248 return (v >> i); 1249 } 1250 1251 static void 1252 eth_bare_write(uint32_t base, int i, int val) 1253 { 1254 uint32_t v; 1255 1256 v = win_eth_bare_read(base); 1257 v &= ~(1 << i); 1258 v |= (val << i); 1259 win_eth_bare_write(base, v); 1260 } 1261 1262 static void 1263 eth_epap_write(uint32_t base, int i, int val) 1264 { 1265 uint32_t v; 1266 1267 v = win_eth_epap_read(base); 1268 v &= ~(0x3 << (i * 2)); 1269 v |= (val << (i * 2)); 1270 win_eth_epap_write(base, v); 1271 } 1272 1273 static void 1274 decode_win_eth_dump(u_long base) 1275 { 1276 int i; 1277 1278 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1279 return; 1280 1281 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1282 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1283 win_eth_br_read(base, i), 1284 win_eth_sz_read(base, i)); 1285 1286 if (win_eth_can_remap(i)) 1287 printf(", ha 0x%08x", 1288 win_eth_har_read(base, i)); 1289 1290 printf("\n"); 1291 } 1292 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1293 win_eth_bare_read(base), 1294 win_eth_epap_read(base)); 1295 } 1296 1297 #if defined(SOC_MV_LOKIPLUS) 1298 #define MV_WIN_ETH_DDR_TRGT(n) 0 1299 #else 1300 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1301 #endif 1302 1303 static void 1304 decode_win_eth_setup(u_long base) 1305 { 1306 uint32_t br, sz; 1307 int i, j; 1308 1309 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1310 return; 1311 1312 eth_port++; 1313 1314 /* Disable, clear and revoke protection for all ETH windows */ 1315 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1316 1317 eth_bare_write(base, i, 1); 1318 eth_epap_write(base, i, 0); 1319 win_eth_br_write(base, i, 0); 1320 win_eth_sz_write(base, i, 0); 1321 if (win_eth_can_remap(i)) 1322 win_eth_har_write(base, i, 0); 1323 } 1324 1325 /* Only access to active DRAM banks is required */ 1326 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1327 if (ddr_is_active(i)) { 1328 1329 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1330 sz = ((ddr_size(i) - 1) & 0xffff0000); 1331 1332 /* Set the first free ETH window */ 1333 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1334 if (eth_bare_read(base, j) == 0) 1335 continue; 1336 1337 win_eth_br_write(base, j, br); 1338 win_eth_sz_write(base, j, sz); 1339 1340 /* XXX remapping ETH windows not supported */ 1341 1342 /* Set protection RW */ 1343 eth_epap_write(base, j, 0x3); 1344 1345 /* Enable window */ 1346 eth_bare_write(base, j, 0); 1347 break; 1348 } 1349 } 1350 } 1351 1352 static int 1353 decode_win_eth_valid(void) 1354 { 1355 1356 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1357 } 1358 1359 /************************************************************************** 1360 * PCIE windows routines 1361 **************************************************************************/ 1362 1363 void 1364 decode_win_pcie_setup(u_long base) 1365 { 1366 uint32_t size = 0, ddrbase = ~0; 1367 uint32_t cr, br; 1368 int i, j; 1369 1370 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1371 pcie_bar_br_write(base, i, 1372 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1373 if (i < 3) 1374 pcie_bar_brh_write(base, i, 0); 1375 if (i > 0) 1376 pcie_bar_cr_write(base, i, 0); 1377 } 1378 1379 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1380 win_pcie_cr_write(base, i, 0); 1381 win_pcie_br_write(base, i, 0); 1382 win_pcie_remap_write(base, i, 0); 1383 } 1384 1385 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1386 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1387 & MV_PCIE_ROOT_CMPLX) == 0) { 1388 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1389 return; 1390 } 1391 1392 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1393 if (ddr_is_active(i)) { 1394 /* Map DDR to BAR 1 */ 1395 cr = (ddr_size(i) - 1) & 0xffff0000; 1396 size += ddr_size(i) & 0xffff0000; 1397 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1398 br = ddr_base(i); 1399 if (br < ddrbase) 1400 ddrbase = br; 1401 1402 /* Use the first available PCIE window */ 1403 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1404 if (win_pcie_cr_read(base, j) != 0) 1405 continue; 1406 1407 win_pcie_br_write(base, j, br); 1408 win_pcie_cr_write(base, j, cr); 1409 break; 1410 } 1411 } 1412 } 1413 1414 /* 1415 * Upper 16 bits in BAR register is interpreted as BAR size 1416 * (in 64 kB units) plus 64kB, so subtract 0x10000 1417 * form value passed to register to get correct value. 1418 */ 1419 size -= 0x10000; 1420 pcie_bar_cr_write(base, 1, size | 1); 1421 pcie_bar_br_write(base, 1, ddrbase | 1422 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1423 pcie_bar_br_write(base, 0, fdt_immr_pa | 1424 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1425 } 1426 1427 static int 1428 decode_win_pcie_valid(void) 1429 { 1430 1431 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1432 } 1433 1434 /************************************************************************** 1435 * IDMA windows routines 1436 **************************************************************************/ 1437 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1438 static int 1439 idma_bare_read(u_long base, int i) 1440 { 1441 uint32_t v; 1442 1443 v = win_idma_bare_read(base); 1444 v &= (1 << i); 1445 1446 return (v >> i); 1447 } 1448 1449 static void 1450 idma_bare_write(u_long base, int i, int val) 1451 { 1452 uint32_t v; 1453 1454 v = win_idma_bare_read(base); 1455 v &= ~(1 << i); 1456 v |= (val << i); 1457 win_idma_bare_write(base, v); 1458 } 1459 1460 /* 1461 * Sets channel protection 'val' for window 'w' on channel 'c' 1462 */ 1463 static void 1464 idma_cap_write(u_long base, int c, int w, int val) 1465 { 1466 uint32_t v; 1467 1468 v = win_idma_cap_read(base, c); 1469 v &= ~(0x3 << (w * 2)); 1470 v |= (val << (w * 2)); 1471 win_idma_cap_write(base, c, v); 1472 } 1473 1474 /* 1475 * Set protection 'val' on all channels for window 'w' 1476 */ 1477 static void 1478 idma_set_prot(u_long base, int w, int val) 1479 { 1480 int c; 1481 1482 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1483 idma_cap_write(base, c, w, val); 1484 } 1485 1486 static int 1487 win_idma_can_remap(int i) 1488 { 1489 1490 /* IDMA decode windows 0-3 have remap capability */ 1491 if (i < 4) 1492 return (1); 1493 1494 return (0); 1495 } 1496 1497 void 1498 decode_win_idma_setup(u_long base) 1499 { 1500 uint32_t br, sz; 1501 int i, j; 1502 1503 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1504 return; 1505 /* 1506 * Disable and clear all IDMA windows, revoke protection for all channels 1507 */ 1508 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1509 1510 idma_bare_write(base, i, 1); 1511 win_idma_br_write(base, i, 0); 1512 win_idma_sz_write(base, i, 0); 1513 if (win_idma_can_remap(i) == 1) 1514 win_idma_har_write(base, i, 0); 1515 } 1516 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1517 win_idma_cap_write(base, i, 0); 1518 1519 /* 1520 * Set up access to all active DRAM banks 1521 */ 1522 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1523 if (ddr_is_active(i)) { 1524 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1525 sz = ((ddr_size(i) - 1) & 0xffff0000); 1526 1527 /* Place DDR entries in non-remapped windows */ 1528 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1529 if (win_idma_can_remap(j) != 1 && 1530 idma_bare_read(base, j) == 1) { 1531 1532 /* Configure window */ 1533 win_idma_br_write(base, j, br); 1534 win_idma_sz_write(base, j, sz); 1535 1536 /* Set protection RW on all channels */ 1537 idma_set_prot(base, j, 0x3); 1538 1539 /* Enable window */ 1540 idma_bare_write(base, j, 0); 1541 break; 1542 } 1543 } 1544 1545 /* 1546 * Remaining targets -- from statically defined table 1547 */ 1548 for (i = 0; i < idma_wins_no; i++) 1549 if (idma_wins[i].target > 0) { 1550 br = (idma_wins[i].base & 0xffff0000) | 1551 (idma_wins[i].attr << 8) | idma_wins[i].target; 1552 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1553 1554 /* Set the first free IDMA window */ 1555 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1556 if (idma_bare_read(base, j) == 0) 1557 continue; 1558 1559 /* Configure window */ 1560 win_idma_br_write(base, j, br); 1561 win_idma_sz_write(base, j, sz); 1562 if (win_idma_can_remap(j) && 1563 idma_wins[j].remap >= 0) 1564 win_idma_har_write(base, j, 1565 idma_wins[j].remap); 1566 1567 /* Set protection RW on all channels */ 1568 idma_set_prot(base, j, 0x3); 1569 1570 /* Enable window */ 1571 idma_bare_write(base, j, 0); 1572 break; 1573 } 1574 } 1575 } 1576 1577 int 1578 decode_win_idma_valid(void) 1579 { 1580 const struct decode_win *wintab; 1581 int c, i, j, rv; 1582 uint32_t b, e, s; 1583 1584 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1585 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1586 return (0); 1587 } 1588 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1589 if (ddr_is_active(i)) 1590 c++; 1591 1592 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1593 printf("IDMA windows: too many entries: %d, available: %d\n", 1594 idma_wins_no, MV_WIN_IDMA_MAX - c); 1595 return (0); 1596 } 1597 1598 wintab = idma_wins; 1599 rv = 1; 1600 for (i = 0; i < idma_wins_no; i++, wintab++) { 1601 1602 if (wintab->target == 0) { 1603 printf("IDMA window#%d: DDR target window is not " 1604 "supposed to be reprogrammed!\n", i); 1605 rv = 0; 1606 } 1607 1608 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1609 printf("IDMA window#%d: not capable of remapping, but " 1610 "val 0x%08x defined\n", i, wintab->remap); 1611 rv = 0; 1612 } 1613 1614 s = wintab->size; 1615 b = wintab->base; 1616 e = b + s - 1; 1617 if (s > (0xFFFFFFFF - b + 1)) { 1618 /* XXX this boundary check should account for 64bit and 1619 * remapping.. */ 1620 printf("IDMA window#%d: no space for size 0x%08x at " 1621 "0x%08x\n", i, s, b); 1622 rv = 0; 1623 continue; 1624 } 1625 1626 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1627 if (j >= 0) { 1628 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1629 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1630 idma_wins[j].base, 1631 idma_wins[j].base + idma_wins[j].size - 1); 1632 rv = 0; 1633 } 1634 } 1635 1636 return (rv); 1637 } 1638 1639 void 1640 decode_win_idma_dump(u_long base) 1641 { 1642 int i; 1643 1644 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1645 return; 1646 1647 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1648 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1649 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1650 1651 if (win_idma_can_remap(i)) 1652 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1653 1654 printf("\n"); 1655 } 1656 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1657 printf("IDMA channel#%d: ap 0x%08x\n", i, 1658 win_idma_cap_read(base, i)); 1659 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1660 } 1661 #else 1662 1663 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1664 int 1665 decode_win_idma_valid(void) 1666 { 1667 1668 return (1); 1669 } 1670 1671 void 1672 decode_win_idma_setup(u_long base) 1673 { 1674 } 1675 1676 void 1677 decode_win_idma_dump(u_long base) 1678 { 1679 } 1680 #endif 1681 1682 /************************************************************************** 1683 * XOR windows routines 1684 **************************************************************************/ 1685 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1686 static int 1687 xor_ctrl_read(u_long base, int i, int c, int e) 1688 { 1689 uint32_t v; 1690 v = win_xor_ctrl_read(base, c, e); 1691 v &= (1 << i); 1692 1693 return (v >> i); 1694 } 1695 1696 static void 1697 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1698 { 1699 uint32_t v; 1700 1701 v = win_xor_ctrl_read(base, c, e); 1702 v &= ~(1 << i); 1703 v |= (val << i); 1704 win_xor_ctrl_write(base, c, e, v); 1705 } 1706 1707 /* 1708 * Set channel protection 'val' for window 'w' on channel 'c' 1709 */ 1710 static void 1711 xor_chan_write(u_long base, int c, int e, int w, int val) 1712 { 1713 uint32_t v; 1714 1715 v = win_xor_ctrl_read(base, c, e); 1716 v &= ~(0x3 << (w * 2 + 16)); 1717 v |= (val << (w * 2 + 16)); 1718 win_xor_ctrl_write(base, c, e, v); 1719 } 1720 1721 /* 1722 * Set protection 'val' on all channels for window 'w' on engine 'e' 1723 */ 1724 static void 1725 xor_set_prot(u_long base, int w, int e, int val) 1726 { 1727 int c; 1728 1729 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1730 xor_chan_write(base, c, e, w, val); 1731 } 1732 1733 static int 1734 win_xor_can_remap(int i) 1735 { 1736 1737 /* XOR decode windows 0-3 have remap capability */ 1738 if (i < 4) 1739 return (1); 1740 1741 return (0); 1742 } 1743 1744 static int 1745 xor_max_eng(void) 1746 { 1747 uint32_t dev, rev; 1748 1749 soc_id(&dev, &rev); 1750 switch (dev) { 1751 case MV_DEV_88F6281: 1752 case MV_DEV_88F6282: 1753 case MV_DEV_MV78130: 1754 case MV_DEV_MV78160: 1755 case MV_DEV_MV78230: 1756 case MV_DEV_MV78260: 1757 case MV_DEV_MV78460: 1758 return (2); 1759 case MV_DEV_MV78100: 1760 case MV_DEV_MV78100_Z0: 1761 return (1); 1762 default: 1763 return (0); 1764 } 1765 } 1766 1767 static void 1768 xor_active_dram(u_long base, int c, int e, int *window) 1769 { 1770 uint32_t br, sz; 1771 int i, m, w; 1772 1773 /* 1774 * Set up access to all active DRAM banks 1775 */ 1776 m = xor_max_eng(); 1777 for (i = 0; i < m; i++) 1778 if (ddr_is_active(i)) { 1779 br = ddr_base(i) | (ddr_attr(i) << 8) | 1780 ddr_target(i); 1781 sz = ((ddr_size(i) - 1) & 0xffff0000); 1782 1783 /* Place DDR entries in non-remapped windows */ 1784 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1785 if (win_xor_can_remap(w) != 1 && 1786 (xor_ctrl_read(base, w, c, e) == 0) && 1787 w > *window) { 1788 /* Configure window */ 1789 win_xor_br_write(base, w, e, br); 1790 win_xor_sz_write(base, w, e, sz); 1791 1792 /* Set protection RW on all channels */ 1793 xor_set_prot(base, w, e, 0x3); 1794 1795 /* Enable window */ 1796 xor_ctrl_write(base, w, c, e, 1); 1797 (*window)++; 1798 break; 1799 } 1800 } 1801 } 1802 1803 void 1804 decode_win_xor_setup(u_long base) 1805 { 1806 uint32_t br, sz; 1807 int i, j, z, e = 1, m, window; 1808 1809 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1810 return; 1811 1812 /* 1813 * Disable and clear all XOR windows, revoke protection for all 1814 * channels 1815 */ 1816 m = xor_max_eng(); 1817 for (j = 0; j < m; j++, e--) { 1818 1819 /* Number of non-remaped windows */ 1820 window = MV_XOR_NON_REMAP - 1; 1821 1822 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1823 win_xor_br_write(base, i, e, 0); 1824 win_xor_sz_write(base, i, e, 0); 1825 } 1826 1827 if (win_xor_can_remap(i) == 1) 1828 win_xor_har_write(base, i, e, 0); 1829 1830 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1831 win_xor_ctrl_write(base, i, e, 0); 1832 xor_active_dram(base, i, e, &window); 1833 } 1834 1835 /* 1836 * Remaining targets -- from a statically defined table 1837 */ 1838 for (i = 0; i < xor_wins_no; i++) 1839 if (xor_wins[i].target > 0) { 1840 br = (xor_wins[i].base & 0xffff0000) | 1841 (xor_wins[i].attr << 8) | 1842 xor_wins[i].target; 1843 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1844 1845 /* Set the first free XOR window */ 1846 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1847 if (xor_ctrl_read(base, z, 0, e) && 1848 xor_ctrl_read(base, z, 1, e)) 1849 continue; 1850 1851 /* Configure window */ 1852 win_xor_br_write(base, z, e, br); 1853 win_xor_sz_write(base, z, e, sz); 1854 if (win_xor_can_remap(z) && 1855 xor_wins[z].remap >= 0) 1856 win_xor_har_write(base, z, e, 1857 xor_wins[z].remap); 1858 1859 /* Set protection RW on all channels */ 1860 xor_set_prot(base, z, e, 0x3); 1861 1862 /* Enable window */ 1863 xor_ctrl_write(base, z, 0, e, 1); 1864 xor_ctrl_write(base, z, 1, e, 1); 1865 break; 1866 } 1867 } 1868 } 1869 } 1870 1871 int 1872 decode_win_xor_valid(void) 1873 { 1874 const struct decode_win *wintab; 1875 int c, i, j, rv; 1876 uint32_t b, e, s; 1877 1878 if (xor_wins_no > MV_WIN_XOR_MAX) { 1879 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1880 return (0); 1881 } 1882 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1883 if (ddr_is_active(i)) 1884 c++; 1885 1886 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1887 printf("XOR windows: too many entries: %d, available: %d\n", 1888 xor_wins_no, MV_WIN_IDMA_MAX - c); 1889 return (0); 1890 } 1891 1892 wintab = xor_wins; 1893 rv = 1; 1894 for (i = 0; i < xor_wins_no; i++, wintab++) { 1895 1896 if (wintab->target == 0) { 1897 printf("XOR window#%d: DDR target window is not " 1898 "supposed to be reprogrammed!\n", i); 1899 rv = 0; 1900 } 1901 1902 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1903 printf("XOR window#%d: not capable of remapping, but " 1904 "val 0x%08x defined\n", i, wintab->remap); 1905 rv = 0; 1906 } 1907 1908 s = wintab->size; 1909 b = wintab->base; 1910 e = b + s - 1; 1911 if (s > (0xFFFFFFFF - b + 1)) { 1912 /* 1913 * XXX this boundary check should account for 64bit 1914 * and remapping.. 1915 */ 1916 printf("XOR window#%d: no space for size 0x%08x at " 1917 "0x%08x\n", i, s, b); 1918 rv = 0; 1919 continue; 1920 } 1921 1922 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 1923 if (j >= 0) { 1924 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 1925 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1926 xor_wins[j].base, 1927 xor_wins[j].base + xor_wins[j].size - 1); 1928 rv = 0; 1929 } 1930 } 1931 1932 return (rv); 1933 } 1934 1935 void 1936 decode_win_xor_dump(u_long base) 1937 { 1938 int i, j; 1939 int e = 1; 1940 1941 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1942 return; 1943 1944 for (j = 0; j < xor_max_eng(); j++, e--) { 1945 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1946 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 1947 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 1948 1949 if (win_xor_can_remap(i)) 1950 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 1951 1952 printf("\n"); 1953 } 1954 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 1955 printf("XOR control#%d: 0x%08x\n", i, 1956 win_xor_ctrl_read(base, i, e)); 1957 } 1958 } 1959 1960 #else 1961 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 1962 static int 1963 decode_win_xor_valid(void) 1964 { 1965 1966 return (1); 1967 } 1968 1969 static void 1970 decode_win_xor_setup(u_long base) 1971 { 1972 } 1973 1974 static void 1975 decode_win_xor_dump(u_long base) 1976 { 1977 } 1978 #endif 1979 1980 /************************************************************************** 1981 * SATA windows routines 1982 **************************************************************************/ 1983 static void 1984 decode_win_sata_setup(u_long base) 1985 { 1986 uint32_t cr, br; 1987 int i, j; 1988 1989 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 1990 return; 1991 1992 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 1993 win_sata_cr_write(base, i, 0); 1994 win_sata_br_write(base, i, 0); 1995 } 1996 1997 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1998 if (ddr_is_active(i)) { 1999 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2000 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2001 br = ddr_base(i); 2002 2003 /* Use the first available SATA window */ 2004 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2005 if ((win_sata_cr_read(base, j) & 1) != 0) 2006 continue; 2007 2008 win_sata_br_write(base, j, br); 2009 win_sata_cr_write(base, j, cr); 2010 break; 2011 } 2012 } 2013 } 2014 2015 #ifdef SOC_MV_ARMADA38X 2016 /* 2017 * Configure AHCI decoding windows 2018 */ 2019 static void 2020 decode_win_ahci_setup(u_long base) 2021 { 2022 uint32_t br, cr, sz; 2023 int i, j; 2024 2025 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2026 win_sata_cr_write(base, i, 0); 2027 win_sata_br_write(base, i, 0); 2028 win_sata_sz_write(base, i, 0); 2029 } 2030 2031 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2032 if (ddr_is_active(i)) { 2033 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2034 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2035 IO_WIN_ENA_MASK; 2036 br = ddr_base(i); 2037 sz = (ddr_size(i) - 1) & 2038 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2039 2040 /* Use first available SATA window */ 2041 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2042 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2043 continue; 2044 2045 /* BASE is set to DRAM base (0x00000000) */ 2046 win_sata_br_write(base, j, br); 2047 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2048 win_sata_cr_write(base, j, cr); 2049 /* SIZE is set to 16MB - max value */ 2050 win_sata_sz_write(base, j, sz); 2051 break; 2052 } 2053 } 2054 } 2055 } 2056 2057 static void 2058 decode_win_ahci_dump(u_long base) 2059 { 2060 int i; 2061 2062 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2063 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2064 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2065 win_sata_sz_read(base,i)); 2066 } 2067 2068 #else 2069 /* 2070 * Provide dummy functions to satisfy the build 2071 * for SoC's not equipped with AHCI controller 2072 */ 2073 static void 2074 decode_win_ahci_setup(u_long base) 2075 { 2076 } 2077 2078 static void 2079 decode_win_ahci_dump(u_long base) 2080 { 2081 } 2082 #endif 2083 2084 static int 2085 decode_win_sata_valid(void) 2086 { 2087 uint32_t dev, rev; 2088 2089 soc_id(&dev, &rev); 2090 if (dev == MV_DEV_88F5281) 2091 return (1); 2092 2093 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2094 } 2095 2096 /************************************************************************** 2097 * FDT parsing routines. 2098 **************************************************************************/ 2099 2100 static int 2101 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2102 int *tuplesize) 2103 { 2104 phandle_t node; 2105 pcell_t addr_cells, par_addr_cells, size_cells; 2106 int len, tuple_size, tuples_count; 2107 2108 node = OF_finddevice(nodename); 2109 if (node == -1) 2110 return (EINVAL); 2111 2112 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2113 return (ENXIO); 2114 2115 par_addr_cells = fdt_parent_addr_cells(node); 2116 if (par_addr_cells > 2) 2117 return (ERANGE); 2118 2119 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2120 size_cells); 2121 2122 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2123 len = OF_getprop(node, "ranges", buf, size); 2124 2125 /* 2126 * XXX this does not handle the empty 'ranges;' case, which is 2127 * legitimate and should be allowed. 2128 */ 2129 tuples_count = len / tuple_size; 2130 if (tuples_count <= 0) 2131 return (ERANGE); 2132 2133 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2134 return (ERANGE); 2135 2136 *tuples = tuples_count; 2137 *tuplesize = tuple_size; 2138 return (0); 2139 } 2140 2141 static int 2142 win_cpu_from_dt(void) 2143 { 2144 pcell_t ranges[48]; 2145 phandle_t node; 2146 int i, entry_size, err, t, tuple_size, tuples; 2147 u_long sram_base, sram_size; 2148 2149 t = 0; 2150 /* Retrieve 'ranges' property of '/localbus' node. */ 2151 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2152 &tuples, &tuple_size)) == 0) { 2153 /* 2154 * Fill CPU decode windows table. 2155 */ 2156 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2157 2158 entry_size = tuple_size / sizeof(pcell_t); 2159 cpu_wins_no = tuples; 2160 2161 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2162 cpu_win_tbl[t].target = 1; 2163 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2164 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2165 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2166 cpu_win_tbl[t].remap = ~0; 2167 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2168 "size = 0x%0x remap = 0x%0x\n", 2169 cpu_win_tbl[t].target, 2170 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2171 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2172 } 2173 } 2174 2175 /* 2176 * Retrieve CESA SRAM data. 2177 */ 2178 if ((node = OF_finddevice("sram")) != -1) 2179 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2180 goto moveon; 2181 2182 if ((node = OF_finddevice("/")) == 0) 2183 return (ENXIO); 2184 2185 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2186 /* SRAM block is not always present. */ 2187 return (0); 2188 moveon: 2189 sram_base = sram_size = 0; 2190 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2191 return (EINVAL); 2192 2193 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2194 #ifdef SOC_MV_ARMADA38X 2195 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2196 #else 2197 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2198 #endif 2199 cpu_win_tbl[t].base = sram_base; 2200 cpu_win_tbl[t].size = sram_size; 2201 cpu_win_tbl[t].remap = ~0; 2202 cpu_wins_no++; 2203 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2204 2205 /* Check if there is a second CESA node */ 2206 while ((node = OF_peer(node)) != 0) { 2207 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2208 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2209 return (EINVAL); 2210 break; 2211 } 2212 } 2213 2214 if (node == 0) 2215 return (0); 2216 2217 t++; 2218 if (t >= nitems(cpu_win_tbl)) { 2219 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2220 return (ENOMEM); 2221 } 2222 2223 /* Configure window for CESA1 */ 2224 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2225 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2226 cpu_win_tbl[t].base = sram_base; 2227 cpu_win_tbl[t].size = sram_size; 2228 cpu_win_tbl[t].remap = ~0; 2229 cpu_wins_no++; 2230 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2231 2232 return (0); 2233 } 2234 2235 static int 2236 fdt_win_setup(void) 2237 { 2238 phandle_t node, child; 2239 struct soc_node_spec *soc_node; 2240 u_long size, base; 2241 int err, i; 2242 2243 node = OF_finddevice("/"); 2244 if (node == -1) 2245 panic("fdt_win_setup: no root node"); 2246 2247 /* 2248 * Traverse through all children of root and simple-bus nodes. 2249 * For each found device retrieve decode windows data (if applicable). 2250 */ 2251 child = OF_child(node); 2252 while (child != 0) { 2253 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2254 2255 soc_node = &soc_nodes[i]; 2256 2257 /* Setup only for enabled devices */ 2258 if (ofw_bus_node_status_okay(child) == 0) 2259 continue; 2260 2261 if (!ofw_bus_node_is_compatible(child,soc_node->compat)) 2262 continue; 2263 2264 err = fdt_regsize(child, &base, &size); 2265 if (err != 0) 2266 return (err); 2267 2268 base = (base & 0x000fffff) | fdt_immr_va; 2269 if (soc_node->decode_handler != NULL) 2270 soc_node->decode_handler(base); 2271 else 2272 return (ENXIO); 2273 2274 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2275 soc_node->dump_handler(base); 2276 } 2277 2278 /* 2279 * Once done with root-level children let's move down to 2280 * simple-bus and its children. 2281 */ 2282 child = OF_peer(child); 2283 if ((child == 0) && (node == OF_finddevice("/"))) { 2284 node = fdt_find_compatible(node, "simple-bus", 0); 2285 if (node == 0) 2286 return (ENXIO); 2287 child = OF_child(node); 2288 } 2289 /* 2290 * Next, move one more level down to internal-regs node (if 2291 * it is present) and its children. This node also have 2292 * "simple-bus" compatible. 2293 */ 2294 if ((child == 0) && (node == OF_finddevice("simple-bus"))) { 2295 node = fdt_find_compatible(node, "simple-bus", 0); 2296 if (node == 0) 2297 return (0); 2298 child = OF_child(node); 2299 } 2300 } 2301 2302 return (0); 2303 } 2304 2305 static void 2306 fdt_fixup_busfreq(phandle_t root) 2307 { 2308 phandle_t sb; 2309 pcell_t freq; 2310 2311 freq = cpu_to_fdt32(get_tclk()); 2312 2313 /* 2314 * Fix bus speed in cpu node 2315 */ 2316 if ((sb = OF_finddevice("cpu")) != 0) 2317 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2318 OF_setprop(sb, "bus-frequency", (void *)&freq, 2319 sizeof(freq)); 2320 2321 /* 2322 * This fixup sets the simple-bus bus-frequency property. 2323 */ 2324 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2325 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2326 } 2327 2328 static void 2329 fdt_fixup_ranges(phandle_t root) 2330 { 2331 phandle_t node; 2332 pcell_t par_addr_cells, addr_cells, size_cells; 2333 pcell_t ranges[3], reg[2], *rangesptr; 2334 int len, tuple_size, tuples_count; 2335 uint32_t base; 2336 2337 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2338 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2339 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2340 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2341 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2342 addr_cells + size_cells); 2343 len = OF_getprop(node, "ranges", ranges, 2344 sizeof(ranges)); 2345 tuples_count = len / tuple_size; 2346 /* Unexpected settings are not supported */ 2347 if (tuples_count != 1) 2348 goto fixup_failed; 2349 2350 rangesptr = &ranges[0]; 2351 rangesptr += par_addr_cells; 2352 base = fdt_data_get((void *)rangesptr, addr_cells); 2353 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2354 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2355 sizeof(ranges)) < 0) 2356 goto fixup_failed; 2357 } 2358 } 2359 2360 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2361 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2362 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2363 &size_cells) == 0) { 2364 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2365 size_cells); 2366 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2367 tuples_count = len / tuple_size; 2368 /* Unexpected settings are not supported */ 2369 if (tuples_count != 1) 2370 goto fixup_failed; 2371 2372 base = fdt_data_get((void *)®[0], par_addr_cells); 2373 base &= ~0xFF000000; 2374 base |= fdt_immr_pa; 2375 reg[0] = cpu_to_fdt32(base); 2376 if (OF_setprop(node, "reg", (void *)®[0], 2377 sizeof(reg)) < 0) 2378 goto fixup_failed; 2379 } 2380 } 2381 /* Fix-up succeeded. May return and continue */ 2382 return; 2383 2384 fixup_failed: 2385 while (1) { 2386 /* 2387 * In case of any error while fixing ranges just hang. 2388 * 1. No message can be displayed yet since console 2389 * is not initialized. 2390 * 2. Going further will cause failure on bus_space_map() 2391 * relying on the wrong ranges or data abort when 2392 * accessing PCIe registers. 2393 */ 2394 } 2395 } 2396 2397 struct fdt_fixup_entry fdt_fixup_table[] = { 2398 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2399 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2400 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2401 { NULL, NULL } 2402 }; 2403 2404 #ifndef INTRNG 2405 static int 2406 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2407 int *pol) 2408 { 2409 2410 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2411 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2412 return (ENXIO); 2413 2414 *interrupt = fdt32_to_cpu(intr[0]); 2415 *trig = INTR_TRIGGER_CONFORM; 2416 *pol = INTR_POLARITY_CONFORM; 2417 2418 return (0); 2419 } 2420 2421 fdt_pic_decode_t fdt_pic_table[] = { 2422 #ifdef SOC_MV_ARMADA38X 2423 &gic_decode_fdt, 2424 #endif 2425 &fdt_pic_decode_ic, 2426 NULL 2427 }; 2428 #endif 2429 2430 uint64_t 2431 get_sar_value(void) 2432 { 2433 uint32_t sar_low, sar_high; 2434 2435 #if defined(SOC_MV_ARMADAXP) 2436 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2437 SAMPLE_AT_RESET_HI); 2438 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2439 SAMPLE_AT_RESET_LO); 2440 #elif defined(SOC_MV_ARMADA38X) 2441 sar_high = 0; 2442 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2443 SAMPLE_AT_RESET); 2444 #else 2445 /* 2446 * TODO: Add getting proper values for other SoC configurations 2447 */ 2448 sar_high = 0; 2449 sar_low = 0; 2450 #endif 2451 2452 return (((uint64_t)sar_high << 32) | sar_low); 2453 } 2454