1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cesa_valid(void); 80 static int decode_win_cpu_valid(void); 81 static int decode_win_usb_valid(void); 82 static int decode_win_usb3_valid(void); 83 static int decode_win_eth_valid(void); 84 static int decode_win_pcie_valid(void); 85 static int decode_win_sata_valid(void); 86 static int decode_win_sdhci_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 static void decode_win_cpu_setup(void); 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_cesa_setup(u_long); 96 static void decode_win_usb_setup(u_long); 97 static void decode_win_usb3_setup(u_long); 98 static void decode_win_eth_setup(u_long); 99 static void decode_win_neta_setup(u_long); 100 static void decode_win_sata_setup(u_long); 101 static void decode_win_ahci_setup(u_long); 102 static void decode_win_sdhci_setup(u_long); 103 104 static void decode_win_idma_setup(u_long); 105 static void decode_win_xor_setup(u_long); 106 107 static void decode_win_cesa_dump(u_long); 108 static void decode_win_usb_dump(u_long); 109 static void decode_win_usb3_dump(u_long); 110 static void decode_win_eth_dump(u_long base); 111 static void decode_win_neta_dump(u_long base); 112 static void decode_win_idma_dump(u_long base); 113 static void decode_win_xor_dump(u_long base); 114 static void decode_win_ahci_dump(u_long base); 115 static void decode_win_sdhci_dump(u_long); 116 static void decode_win_pcie_dump(u_long); 117 118 static int fdt_get_ranges(const char *, void *, int, int *, int *); 119 #ifdef SOC_MV_ARMADA38X 120 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 121 int *trig, int *pol); 122 #endif 123 124 static int win_cpu_from_dt(void); 125 static int fdt_win_setup(void); 126 127 static uint32_t dev_mask = 0; 128 static int cpu_wins_no = 0; 129 static int eth_port = 0; 130 static int usb_port = 0; 131 132 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 133 134 const struct decode_win *cpu_wins = cpu_win_tbl; 135 136 typedef void (*decode_win_setup_t)(u_long); 137 typedef void (*dump_win_t)(u_long); 138 139 /* 140 * The power status of device feature is only supported on 141 * Kirkwood and Discovery SoCs. 142 */ 143 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 144 #define SOC_MV_POWER_STAT_SUPPORTED 1 145 #else 146 #define SOC_MV_POWER_STAT_SUPPORTED 0 147 #endif 148 149 struct soc_node_spec { 150 const char *compat; 151 decode_win_setup_t decode_handler; 152 dump_win_t dump_handler; 153 }; 154 155 static struct soc_node_spec soc_nodes[] = { 156 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 157 { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump }, 158 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 159 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 160 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 161 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 162 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, 163 { "mrvl,sata", &decode_win_sata_setup, NULL }, 164 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 165 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 166 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, 167 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump }, 168 { NULL, NULL, NULL }, 169 }; 170 171 struct fdt_pm_mask_entry { 172 char *compat; 173 uint32_t mask; 174 }; 175 176 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 177 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 178 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 179 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 180 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 181 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 182 { "mrvl,xor", CPU_PM_CTRL_XOR }, 183 { "mrvl,sata", CPU_PM_CTRL_SATA }, 184 185 { NULL, 0 } 186 }; 187 188 static __inline int 189 pm_is_disabled(uint32_t mask) 190 { 191 #if SOC_MV_POWER_STAT_SUPPORTED 192 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 193 #else 194 return (0); 195 #endif 196 } 197 198 /* 199 * Disable device using power management register. 200 * 1 - Device Power On 201 * 0 - Device Power Off 202 * Mask can be set in loader. 203 * EXAMPLE: 204 * loader> set hw.pm-disable-mask=0x2 205 * 206 * Common mask: 207 * |-------------------------------| 208 * | Device | Kirkwood | Discovery | 209 * |-------------------------------| 210 * | USB0 | 0x00008 | 0x020000 | 211 * |-------------------------------| 212 * | USB1 | - | 0x040000 | 213 * |-------------------------------| 214 * | USB2 | - | 0x080000 | 215 * |-------------------------------| 216 * | GE0 | 0x00001 | 0x000002 | 217 * |-------------------------------| 218 * | GE1 | - | 0x000004 | 219 * |-------------------------------| 220 * | IDMA | - | 0x100000 | 221 * |-------------------------------| 222 * | XOR | 0x10000 | 0x200000 | 223 * |-------------------------------| 224 * | CESA | 0x20000 | 0x400000 | 225 * |-------------------------------| 226 * | SATA | 0x04000 | 0x004000 | 227 * --------------------------------| 228 * This feature can be used only on Kirkwood and Discovery 229 * machines. 230 */ 231 static __inline void 232 pm_disable_device(int mask) 233 { 234 #ifdef DIAGNOSTIC 235 uint32_t reg; 236 237 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 238 printf("Power Management Register: 0%x\n", reg); 239 240 reg &= ~mask; 241 soc_power_ctrl_set(reg); 242 printf("Device %x is disabled\n", mask); 243 244 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 245 printf("Power Management Register: 0%x\n", reg); 246 #endif 247 } 248 249 int 250 fdt_pm(phandle_t node) 251 { 252 uint32_t cpu_pm_ctrl; 253 int i, ena, compat; 254 255 ena = 1; 256 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 257 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 258 if (dev_mask & (1 << i)) 259 continue; 260 261 compat = ofw_bus_node_is_compatible(node, 262 fdt_pm_mask_table[i].compat); 263 #if defined(SOC_MV_KIRKWOOD) 264 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 265 dev_mask |= (1 << i); 266 ena = 0; 267 break; 268 } else if (compat) { 269 dev_mask |= (1 << i); 270 break; 271 } 272 #else 273 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 274 dev_mask |= (1 << i); 275 ena = 0; 276 break; 277 } else if (compat) { 278 dev_mask |= (1 << i); 279 break; 280 } 281 #endif 282 } 283 284 return (ena); 285 } 286 287 uint32_t 288 read_cpu_ctrl(uint32_t reg) 289 { 290 291 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 292 } 293 294 void 295 write_cpu_ctrl(uint32_t reg, uint32_t val) 296 { 297 298 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 299 } 300 301 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 302 uint32_t 303 read_cpu_mp_clocks(uint32_t reg) 304 { 305 306 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 307 } 308 309 void 310 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 311 { 312 313 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 314 } 315 316 uint32_t 317 read_cpu_misc(uint32_t reg) 318 { 319 320 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 321 } 322 323 void 324 write_cpu_misc(uint32_t reg, uint32_t val) 325 { 326 327 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 328 } 329 #endif 330 331 void 332 cpu_reset(void) 333 { 334 335 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 336 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 337 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 338 #else 339 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 340 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 341 #endif 342 while (1); 343 } 344 345 uint32_t 346 cpu_extra_feat(void) 347 { 348 uint32_t dev, rev; 349 uint32_t ef = 0; 350 351 soc_id(&dev, &rev); 352 353 switch (dev) { 354 case MV_DEV_88F6281: 355 case MV_DEV_88F6282: 356 case MV_DEV_88RC8180: 357 case MV_DEV_MV78100_Z0: 358 case MV_DEV_MV78100: 359 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 360 break; 361 case MV_DEV_88F5182: 362 case MV_DEV_88F5281: 363 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 364 break; 365 default: 366 if (bootverbose) 367 printf("This ARM Core does not support any extra features\n"); 368 } 369 370 return (ef); 371 } 372 373 /* 374 * Get the power status of device. This feature is only supported on 375 * Kirkwood and Discovery SoCs. 376 */ 377 uint32_t 378 soc_power_ctrl_get(uint32_t mask) 379 { 380 381 #if SOC_MV_POWER_STAT_SUPPORTED 382 if (mask != CPU_PM_CTRL_NONE) 383 mask &= read_cpu_ctrl(CPU_PM_CTRL); 384 385 return (mask); 386 #else 387 return (mask); 388 #endif 389 } 390 391 /* 392 * Set the power status of device. This feature is only supported on 393 * Kirkwood and Discovery SoCs. 394 */ 395 void 396 soc_power_ctrl_set(uint32_t mask) 397 { 398 399 #if !defined(SOC_MV_ORION) 400 if (mask != CPU_PM_CTRL_NONE) 401 write_cpu_ctrl(CPU_PM_CTRL, mask); 402 #endif 403 } 404 405 void 406 soc_id(uint32_t *dev, uint32_t *rev) 407 { 408 409 /* 410 * Notice: system identifiers are available in the registers range of 411 * PCIE controller, so using this function is only allowed (and 412 * possible) after the internal registers range has been mapped in via 413 * devmap_bootstrap(). 414 */ 415 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 416 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 417 } 418 419 static void 420 soc_identify(void) 421 { 422 uint32_t d, r, size, mode, freq; 423 const char *dev; 424 const char *rev; 425 426 soc_id(&d, &r); 427 428 printf("SOC: "); 429 if (bootverbose) 430 printf("(0x%4x:0x%02x) ", d, r); 431 432 rev = ""; 433 switch (d) { 434 case MV_DEV_88F5181: 435 dev = "Marvell 88F5181"; 436 if (r == 3) 437 rev = "B1"; 438 break; 439 case MV_DEV_88F5182: 440 dev = "Marvell 88F5182"; 441 if (r == 2) 442 rev = "A2"; 443 break; 444 case MV_DEV_88F5281: 445 dev = "Marvell 88F5281"; 446 if (r == 4) 447 rev = "D0"; 448 else if (r == 5) 449 rev = "D1"; 450 else if (r == 6) 451 rev = "D2"; 452 break; 453 case MV_DEV_88F6281: 454 dev = "Marvell 88F6281"; 455 if (r == 0) 456 rev = "Z0"; 457 else if (r == 2) 458 rev = "A0"; 459 else if (r == 3) 460 rev = "A1"; 461 break; 462 case MV_DEV_88RC8180: 463 dev = "Marvell 88RC8180"; 464 break; 465 case MV_DEV_88RC9480: 466 dev = "Marvell 88RC9480"; 467 break; 468 case MV_DEV_88RC9580: 469 dev = "Marvell 88RC9580"; 470 break; 471 case MV_DEV_88F6781: 472 dev = "Marvell 88F6781"; 473 if (r == 2) 474 rev = "Y0"; 475 break; 476 case MV_DEV_88F6282: 477 dev = "Marvell 88F6282"; 478 if (r == 0) 479 rev = "A0"; 480 else if (r == 1) 481 rev = "A1"; 482 break; 483 case MV_DEV_88F6828: 484 dev = "Marvell 88F6828"; 485 break; 486 case MV_DEV_88F6820: 487 dev = "Marvell 88F6820"; 488 break; 489 case MV_DEV_88F6810: 490 dev = "Marvell 88F6810"; 491 break; 492 case MV_DEV_MV78100_Z0: 493 dev = "Marvell MV78100 Z0"; 494 break; 495 case MV_DEV_MV78100: 496 dev = "Marvell MV78100"; 497 break; 498 case MV_DEV_MV78160: 499 dev = "Marvell MV78160"; 500 break; 501 case MV_DEV_MV78260: 502 dev = "Marvell MV78260"; 503 break; 504 case MV_DEV_MV78460: 505 dev = "Marvell MV78460"; 506 break; 507 default: 508 dev = "UNKNOWN"; 509 break; 510 } 511 512 printf("%s", dev); 513 if (*rev != '\0') 514 printf(" rev %s", rev); 515 printf(", TClock %dMHz", get_tclk() / 1000 / 1000); 516 freq = get_cpu_freq(); 517 if (freq != 0) 518 printf(", Frequency %dMHz", freq / 1000 / 1000); 519 printf("\n"); 520 521 mode = read_cpu_ctrl(CPU_CONFIG); 522 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 523 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 524 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 525 526 switch (d) { 527 case MV_DEV_88F6281: 528 case MV_DEV_88F6282: 529 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 530 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 531 mode ? "write-through" : "write-back"); 532 break; 533 case MV_DEV_MV78100: 534 mode = read_cpu_ctrl(CPU_CONTROL); 535 size = mode & CPU_CONTROL_L2_SIZE; 536 mode = mode & CPU_CONTROL_L2_MODE; 537 printf(" %s set-associative %s unified L2 cache\n", 538 size ? "256KB 4-way" : "512KB 8-way", 539 mode ? "write-through" : "write-back"); 540 break; 541 default: 542 break; 543 } 544 } 545 546 static void 547 platform_identify(void *dummy) 548 { 549 550 soc_identify(); 551 552 /* 553 * XXX Board identification e.g. read out from FPGA or similar should 554 * go here 555 */ 556 } 557 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 558 NULL); 559 560 #ifdef KDB 561 static void 562 mv_enter_debugger(void *dummy) 563 { 564 565 if (boothowto & RB_KDB) 566 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 567 } 568 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 569 #endif 570 571 int 572 soc_decode_win(void) 573 { 574 uint32_t dev, rev; 575 int mask, err; 576 577 mask = 0; 578 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 579 580 if (mask != 0) 581 pm_disable_device(mask); 582 583 /* Retrieve data about physical addresses from device tree. */ 584 if ((err = win_cpu_from_dt()) != 0) 585 return (err); 586 587 /* Retrieve our ID: some windows facilities vary between SoC models */ 588 soc_id(&dev, &rev); 589 590 #ifdef SOC_MV_ARMADAXP 591 if ((err = decode_win_sdram_fixup()) != 0) 592 return(err); 593 #endif 594 595 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 596 !decode_win_eth_valid() || !decode_win_idma_valid() || 597 !decode_win_pcie_valid() || !decode_win_sata_valid() || 598 !decode_win_xor_valid() || !decode_win_usb3_valid() || 599 !decode_win_sdhci_valid() || !decode_win_cesa_valid()) 600 return (EINVAL); 601 602 decode_win_cpu_setup(); 603 if (MV_DUMP_WIN) 604 soc_dump_decode_win(); 605 606 eth_port = 0; 607 usb_port = 0; 608 if ((err = fdt_win_setup()) != 0) 609 return (err); 610 611 return (0); 612 } 613 614 /************************************************************************** 615 * Decode windows registers accessors 616 **************************************************************************/ 617 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 618 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 619 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 620 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 621 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 622 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 623 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 624 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 625 626 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 627 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 628 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 629 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 630 631 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 632 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 633 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 634 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 635 636 #ifdef SOC_MV_ARMADA38X 637 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 638 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 639 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 640 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 641 #endif 642 643 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 644 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 645 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 646 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 647 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 648 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 649 650 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 651 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 652 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 653 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 654 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 655 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 656 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 657 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 658 659 WIN_REG_BASE_RD(win_eth, bare, 0x290) 660 WIN_REG_BASE_RD(win_eth, epap, 0x294) 661 WIN_REG_BASE_WR(win_eth, bare, 0x290) 662 WIN_REG_BASE_WR(win_eth, epap, 0x294) 663 664 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 665 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 666 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 667 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 668 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 669 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 670 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 671 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 672 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); 673 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 674 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 675 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 676 677 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 678 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 679 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 680 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 681 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 682 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 683 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 684 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 685 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 686 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 687 688 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 689 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 690 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 691 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 692 #if defined(SOC_MV_ARMADA38X) 693 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 694 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 695 #endif 696 697 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 698 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 699 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 700 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 701 702 #ifndef SOC_MV_DOVE 703 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 704 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 705 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 706 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 707 #else 708 /* 709 * On 88F6781 (Dove) SoC DDR Controller is accessed through 710 * single MBUS <-> AXI bridge. In this case we provide emulated 711 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 712 * with common decoding windows setup code. 713 */ 714 715 static inline uint32_t ddr_br_read(int i) 716 { 717 uint32_t mmap; 718 719 /* Read Memory Address Map Register for CS i */ 720 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 721 722 /* Return CS i base address */ 723 return (mmap & 0xFF000000); 724 } 725 726 static inline uint32_t ddr_sz_read(int i) 727 { 728 uint32_t mmap, size; 729 730 /* Read Memory Address Map Register for CS i */ 731 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 732 733 /* Extract size of CS space in 64kB units */ 734 size = (1 << ((mmap >> 16) & 0x0F)); 735 736 /* Return CS size and enable/disable status */ 737 return (((size - 1) << 16) | (mmap & 0x01)); 738 } 739 #endif 740 741 /************************************************************************** 742 * Decode windows helper routines 743 **************************************************************************/ 744 void 745 soc_dump_decode_win(void) 746 { 747 uint32_t dev, rev; 748 int i; 749 750 soc_id(&dev, &rev); 751 752 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 753 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 754 win_cpu_cr_read(i), 755 win_cpu_br_read(i)); 756 757 if (win_cpu_can_remap(i)) 758 printf(", rl 0x%08x, rh 0x%08x", 759 win_cpu_remap_l_read(i), 760 win_cpu_remap_h_read(i)); 761 762 printf("\n"); 763 } 764 printf("Internal regs base: 0x%08x\n", 765 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 766 767 for (i = 0; i < MV_WIN_DDR_MAX; i++) 768 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 769 ddr_br_read(i), ddr_sz_read(i)); 770 } 771 772 /************************************************************************** 773 * CPU windows routines 774 **************************************************************************/ 775 int 776 win_cpu_can_remap(int i) 777 { 778 uint32_t dev, rev; 779 780 soc_id(&dev, &rev); 781 782 /* Depending on the SoC certain windows have remap capability */ 783 if ((dev == MV_DEV_88F5182 && i < 2) || 784 (dev == MV_DEV_88F5281 && i < 4) || 785 (dev == MV_DEV_88F6281 && i < 4) || 786 (dev == MV_DEV_88F6282 && i < 4) || 787 (dev == MV_DEV_88F6828 && i < 20) || 788 (dev == MV_DEV_88F6820 && i < 20) || 789 (dev == MV_DEV_88F6810 && i < 20) || 790 (dev == MV_DEV_88RC8180 && i < 2) || 791 (dev == MV_DEV_88F6781 && i < 4) || 792 (dev == MV_DEV_MV78100_Z0 && i < 8) || 793 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 794 return (1); 795 796 return (0); 797 } 798 799 /* XXX This should check for overlapping remap fields too.. */ 800 int 801 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 802 { 803 const struct decode_win *tab; 804 int i; 805 806 tab = wintab; 807 808 for (i = 0; i < win_no; i++, tab++) { 809 if (i == win) 810 /* Skip self */ 811 continue; 812 813 if ((tab->base + tab->size - 1) < (wintab + win)->base) 814 continue; 815 816 else if (((wintab + win)->base + (wintab + win)->size - 1) < 817 tab->base) 818 continue; 819 else 820 return (i); 821 } 822 823 return (-1); 824 } 825 826 static int 827 decode_win_cpu_valid(void) 828 { 829 int i, j, rv; 830 uint32_t b, e, s; 831 832 if (cpu_wins_no > MV_WIN_CPU_MAX) { 833 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 834 return (0); 835 } 836 837 rv = 1; 838 for (i = 0; i < cpu_wins_no; i++) { 839 840 if (cpu_wins[i].target == 0) { 841 printf("CPU window#%d: DDR target window is not " 842 "supposed to be reprogrammed!\n", i); 843 rv = 0; 844 } 845 846 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 847 printf("CPU window#%d: not capable of remapping, but " 848 "val 0x%08x defined\n", i, cpu_wins[i].remap); 849 rv = 0; 850 } 851 852 s = cpu_wins[i].size; 853 b = cpu_wins[i].base; 854 e = b + s - 1; 855 if (s > (0xFFFFFFFF - b + 1)) { 856 /* 857 * XXX this boundary check should account for 64bit 858 * and remapping.. 859 */ 860 printf("CPU window#%d: no space for size 0x%08x at " 861 "0x%08x\n", i, s, b); 862 rv = 0; 863 continue; 864 } 865 866 if (b != rounddown2(b, s)) { 867 printf("CPU window#%d: address 0x%08x is not aligned " 868 "to 0x%08x\n", i, b, s); 869 rv = 0; 870 continue; 871 } 872 873 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 874 if (j >= 0) { 875 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 876 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 877 cpu_wins[j].base, 878 cpu_wins[j].base + cpu_wins[j].size - 1); 879 rv = 0; 880 } 881 } 882 883 return (rv); 884 } 885 886 int 887 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 888 vm_paddr_t remap) 889 { 890 uint32_t br, cr; 891 int win, i; 892 893 if (remap == ~0) { 894 win = MV_WIN_CPU_MAX - 1; 895 i = -1; 896 } else { 897 win = 0; 898 i = 1; 899 } 900 901 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 902 cr = win_cpu_cr_read(win); 903 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 904 break; 905 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 906 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 907 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 908 (target << MV_WIN_CPU_TARGET_SHIFT))) 909 break; 910 win += i; 911 } 912 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 913 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 914 return (-1); 915 916 br = base & 0xffff0000; 917 win_cpu_br_write(win, br); 918 919 if (win_cpu_can_remap(win)) { 920 if (remap != ~0) { 921 win_cpu_remap_l_write(win, remap & 0xffff0000); 922 win_cpu_remap_h_write(win, 0); 923 } else { 924 /* 925 * Remap function is not used for a given window 926 * (capable of remapping) - set remap field with the 927 * same value as base. 928 */ 929 win_cpu_remap_l_write(win, base & 0xffff0000); 930 win_cpu_remap_h_write(win, 0); 931 } 932 } 933 934 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 935 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 936 win_cpu_cr_write(win, cr); 937 938 return (0); 939 } 940 941 static void 942 decode_win_cpu_setup(void) 943 { 944 int i; 945 946 /* Disable all CPU windows */ 947 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 948 win_cpu_cr_write(i, 0); 949 win_cpu_br_write(i, 0); 950 if (win_cpu_can_remap(i)) { 951 win_cpu_remap_l_write(i, 0); 952 win_cpu_remap_h_write(i, 0); 953 } 954 } 955 956 for (i = 0; i < cpu_wins_no; i++) 957 if (cpu_wins[i].target > 0) 958 decode_win_cpu_set(cpu_wins[i].target, 959 cpu_wins[i].attr, cpu_wins[i].base, 960 cpu_wins[i].size, cpu_wins[i].remap); 961 962 } 963 964 #ifdef SOC_MV_ARMADAXP 965 static int 966 decode_win_sdram_fixup(void) 967 { 968 struct mem_region mr[FDT_MEM_REGIONS]; 969 uint8_t window_valid[MV_WIN_DDR_MAX]; 970 int mr_cnt, err, i, j; 971 uint32_t valid_win_num = 0; 972 973 /* Grab physical memory regions information from device tree. */ 974 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 975 if (err != 0) 976 return (err); 977 978 for (i = 0; i < MV_WIN_DDR_MAX; i++) 979 window_valid[i] = 0; 980 981 /* Try to match entries from device tree with settings from u-boot */ 982 for (i = 0; i < mr_cnt; i++) { 983 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 984 if (ddr_is_active(j) && 985 (ddr_base(j) == mr[i].mr_start) && 986 (ddr_size(j) == mr[i].mr_size)) { 987 window_valid[j] = 1; 988 valid_win_num++; 989 } 990 } 991 } 992 993 if (mr_cnt != valid_win_num) 994 return (EINVAL); 995 996 /* Destroy windows without corresponding device tree entry */ 997 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 998 if (ddr_is_active(j) && (window_valid[j] != 1)) { 999 printf("Disabling SDRAM decoding window: %d\n", j); 1000 ddr_disable(j); 1001 } 1002 } 1003 1004 return (0); 1005 } 1006 #endif 1007 /* 1008 * Check if we're able to cover all active DDR banks. 1009 */ 1010 static int 1011 decode_win_can_cover_ddr(int max) 1012 { 1013 int i, c; 1014 1015 c = 0; 1016 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1017 if (ddr_is_active(i)) 1018 c++; 1019 1020 if (c > max) { 1021 printf("Unable to cover all active DDR banks: " 1022 "%d, available windows: %d\n", c, max); 1023 return (0); 1024 } 1025 1026 return (1); 1027 } 1028 1029 /************************************************************************** 1030 * DDR windows routines 1031 **************************************************************************/ 1032 int 1033 ddr_is_active(int i) 1034 { 1035 1036 if (ddr_sz_read(i) & 0x1) 1037 return (1); 1038 1039 return (0); 1040 } 1041 1042 void 1043 ddr_disable(int i) 1044 { 1045 1046 ddr_sz_write(i, 0); 1047 ddr_br_write(i, 0); 1048 } 1049 1050 uint32_t 1051 ddr_base(int i) 1052 { 1053 1054 return (ddr_br_read(i) & 0xff000000); 1055 } 1056 1057 uint32_t 1058 ddr_size(int i) 1059 { 1060 1061 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1062 } 1063 1064 uint32_t 1065 ddr_attr(int i) 1066 { 1067 uint32_t dev, rev; 1068 1069 soc_id(&dev, &rev); 1070 if (dev == MV_DEV_88RC8180) 1071 return ((ddr_sz_read(i) & 0xf0) >> 4); 1072 if (dev == MV_DEV_88F6781) 1073 return (0); 1074 1075 return (i == 0 ? 0xe : 1076 (i == 1 ? 0xd : 1077 (i == 2 ? 0xb : 1078 (i == 3 ? 0x7 : 0xff)))); 1079 } 1080 1081 uint32_t 1082 ddr_target(int i) 1083 { 1084 uint32_t dev, rev; 1085 1086 soc_id(&dev, &rev); 1087 if (dev == MV_DEV_88RC8180) { 1088 i = (ddr_sz_read(i) & 0xf0) >> 4; 1089 return (i == 0xe ? 0xc : 1090 (i == 0xd ? 0xd : 1091 (i == 0xb ? 0xe : 1092 (i == 0x7 ? 0xf : 0xc)))); 1093 } 1094 1095 /* 1096 * On SOCs other than 88RC8180 Mbus unit ID for 1097 * DDR SDRAM controller is always 0x0. 1098 */ 1099 return (0); 1100 } 1101 1102 /************************************************************************** 1103 * CESA windows routines 1104 **************************************************************************/ 1105 static int 1106 decode_win_cesa_valid(void) 1107 { 1108 1109 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1110 } 1111 1112 static void 1113 decode_win_cesa_dump(u_long base) 1114 { 1115 int i; 1116 1117 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1118 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1119 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1120 } 1121 1122 /* 1123 * Set CESA decode windows. 1124 */ 1125 static void 1126 decode_win_cesa_setup(u_long base) 1127 { 1128 uint32_t br, cr; 1129 uint64_t size; 1130 int i, j; 1131 1132 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1133 win_cesa_cr_write(base, i, 0); 1134 win_cesa_br_write(base, i, 0); 1135 } 1136 1137 /* Only access to active DRAM banks is required */ 1138 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1139 if (ddr_is_active(i)) { 1140 br = ddr_base(i); 1141 1142 size = ddr_size(i); 1143 #ifdef SOC_MV_ARMADA38X 1144 /* 1145 * Armada 38x SoC's equipped with 4GB DRAM 1146 * suffer freeze during CESA operation, if 1147 * MBUS window opened at given DRAM CS reaches 1148 * end of the address space. Apply a workaround 1149 * by setting the window size to the closest possible 1150 * value, i.e. divide it by 2. 1151 */ 1152 if (size + ddr_base(i) == 0x100000000ULL) 1153 size /= 2; 1154 #endif 1155 1156 cr = (((size - 1) & 0xffff0000) | 1157 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1158 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1159 IO_WIN_ENA_MASK); 1160 1161 /* Set the first free CESA window */ 1162 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1163 if (win_cesa_cr_read(base, j) & 0x1) 1164 continue; 1165 1166 win_cesa_br_write(base, j, br); 1167 win_cesa_cr_write(base, j, cr); 1168 break; 1169 } 1170 } 1171 } 1172 } 1173 1174 /************************************************************************** 1175 * USB windows routines 1176 **************************************************************************/ 1177 static int 1178 decode_win_usb_valid(void) 1179 { 1180 1181 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1182 } 1183 1184 static void 1185 decode_win_usb_dump(u_long base) 1186 { 1187 int i; 1188 1189 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1190 return; 1191 1192 for (i = 0; i < MV_WIN_USB_MAX; i++) 1193 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1194 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1195 } 1196 1197 /* 1198 * Set USB decode windows. 1199 */ 1200 static void 1201 decode_win_usb_setup(u_long base) 1202 { 1203 uint32_t br, cr; 1204 int i, j; 1205 1206 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1207 return; 1208 1209 usb_port++; 1210 1211 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1212 win_usb_cr_write(base, i, 0); 1213 win_usb_br_write(base, i, 0); 1214 } 1215 1216 /* Only access to active DRAM banks is required */ 1217 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1218 if (ddr_is_active(i)) { 1219 br = ddr_base(i); 1220 /* 1221 * XXX for 6281 we should handle Mbus write 1222 * burst limit field in the ctrl reg 1223 */ 1224 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1225 (ddr_attr(i) << 8) | 1226 (ddr_target(i) << 4) | 1); 1227 1228 /* Set the first free USB window */ 1229 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1230 if (win_usb_cr_read(base, j) & 0x1) 1231 continue; 1232 1233 win_usb_br_write(base, j, br); 1234 win_usb_cr_write(base, j, cr); 1235 break; 1236 } 1237 } 1238 } 1239 } 1240 1241 /************************************************************************** 1242 * USB3 windows routines 1243 **************************************************************************/ 1244 #ifdef SOC_MV_ARMADA38X 1245 static int 1246 decode_win_usb3_valid(void) 1247 { 1248 1249 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1250 } 1251 1252 static void 1253 decode_win_usb3_dump(u_long base) 1254 { 1255 int i; 1256 1257 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1258 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1259 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1260 } 1261 1262 /* 1263 * Set USB3 decode windows 1264 */ 1265 static void 1266 decode_win_usb3_setup(u_long base) 1267 { 1268 uint32_t br, cr; 1269 int i, j; 1270 1271 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1272 win_usb3_cr_write(base, i, 0); 1273 win_usb3_br_write(base, i, 0); 1274 } 1275 1276 /* Only access to active DRAM banks is required */ 1277 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1278 if (ddr_is_active(i)) { 1279 br = ddr_base(i); 1280 cr = (((ddr_size(i) - 1) & 1281 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1282 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1283 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1284 IO_WIN_ENA_MASK); 1285 1286 /* Set the first free USB3.0 window */ 1287 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1288 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1289 continue; 1290 1291 win_usb3_br_write(base, j, br); 1292 win_usb3_cr_write(base, j, cr); 1293 break; 1294 } 1295 } 1296 } 1297 } 1298 #else 1299 /* 1300 * Provide dummy functions to satisfy the build 1301 * for SoCs not equipped with USB3 1302 */ 1303 static int 1304 decode_win_usb3_valid(void) 1305 { 1306 1307 return (1); 1308 } 1309 1310 static void 1311 decode_win_usb3_setup(u_long base) 1312 { 1313 } 1314 1315 static void 1316 decode_win_usb3_dump(u_long base) 1317 { 1318 } 1319 #endif 1320 /************************************************************************** 1321 * ETH windows routines 1322 **************************************************************************/ 1323 1324 static int 1325 win_eth_can_remap(int i) 1326 { 1327 1328 /* ETH encode windows 0-3 have remap capability */ 1329 if (i < 4) 1330 return (1); 1331 1332 return (0); 1333 } 1334 1335 static int 1336 eth_bare_read(uint32_t base, int i) 1337 { 1338 uint32_t v; 1339 1340 v = win_eth_bare_read(base); 1341 v &= (1 << i); 1342 1343 return (v >> i); 1344 } 1345 1346 static void 1347 eth_bare_write(uint32_t base, int i, int val) 1348 { 1349 uint32_t v; 1350 1351 v = win_eth_bare_read(base); 1352 v &= ~(1 << i); 1353 v |= (val << i); 1354 win_eth_bare_write(base, v); 1355 } 1356 1357 static void 1358 eth_epap_write(uint32_t base, int i, int val) 1359 { 1360 uint32_t v; 1361 1362 v = win_eth_epap_read(base); 1363 v &= ~(0x3 << (i * 2)); 1364 v |= (val << (i * 2)); 1365 win_eth_epap_write(base, v); 1366 } 1367 1368 static void 1369 decode_win_eth_dump(u_long base) 1370 { 1371 int i; 1372 1373 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1374 return; 1375 1376 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1377 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1378 win_eth_br_read(base, i), 1379 win_eth_sz_read(base, i)); 1380 1381 if (win_eth_can_remap(i)) 1382 printf(", ha 0x%08x", 1383 win_eth_har_read(base, i)); 1384 1385 printf("\n"); 1386 } 1387 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1388 win_eth_bare_read(base), 1389 win_eth_epap_read(base)); 1390 } 1391 1392 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1393 1394 static void 1395 decode_win_eth_setup(u_long base) 1396 { 1397 uint32_t br, sz; 1398 int i, j; 1399 1400 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1401 return; 1402 1403 eth_port++; 1404 1405 /* Disable, clear and revoke protection for all ETH windows */ 1406 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1407 1408 eth_bare_write(base, i, 1); 1409 eth_epap_write(base, i, 0); 1410 win_eth_br_write(base, i, 0); 1411 win_eth_sz_write(base, i, 0); 1412 if (win_eth_can_remap(i)) 1413 win_eth_har_write(base, i, 0); 1414 } 1415 1416 /* Only access to active DRAM banks is required */ 1417 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1418 if (ddr_is_active(i)) { 1419 1420 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1421 sz = ((ddr_size(i) - 1) & 0xffff0000); 1422 1423 /* Set the first free ETH window */ 1424 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1425 if (eth_bare_read(base, j) == 0) 1426 continue; 1427 1428 win_eth_br_write(base, j, br); 1429 win_eth_sz_write(base, j, sz); 1430 1431 /* XXX remapping ETH windows not supported */ 1432 1433 /* Set protection RW */ 1434 eth_epap_write(base, j, 0x3); 1435 1436 /* Enable window */ 1437 eth_bare_write(base, j, 0); 1438 break; 1439 } 1440 } 1441 } 1442 1443 static void 1444 decode_win_neta_dump(u_long base) 1445 { 1446 1447 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); 1448 } 1449 1450 static void 1451 decode_win_neta_setup(u_long base) 1452 { 1453 1454 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); 1455 } 1456 1457 static int 1458 decode_win_eth_valid(void) 1459 { 1460 1461 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1462 } 1463 1464 /************************************************************************** 1465 * PCIE windows routines 1466 **************************************************************************/ 1467 static void 1468 decode_win_pcie_dump(u_long base) 1469 { 1470 int i; 1471 1472 printf("PCIE windows base 0x%08lx\n", base); 1473 for (i = 0; i < MV_WIN_PCIE_MAX; i++) 1474 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", 1475 i, win_pcie_cr_read(base, i), 1476 win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); 1477 1478 for (i = 0; i < MV_PCIE_BAR_MAX; i++) 1479 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", 1480 i, pcie_bar_cr_read(base, i), 1481 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); 1482 } 1483 1484 void 1485 decode_win_pcie_setup(u_long base) 1486 { 1487 uint32_t size = 0, ddrbase = ~0; 1488 uint32_t cr, br; 1489 int i, j; 1490 1491 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1492 pcie_bar_br_write(base, i, 1493 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1494 if (i < 3) 1495 pcie_bar_brh_write(base, i, 0); 1496 if (i > 0) 1497 pcie_bar_cr_write(base, i, 0); 1498 } 1499 1500 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1501 win_pcie_cr_write(base, i, 0); 1502 win_pcie_br_write(base, i, 0); 1503 win_pcie_remap_write(base, i, 0); 1504 } 1505 1506 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1507 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1508 & MV_PCIE_ROOT_CMPLX) == 0) { 1509 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1510 return; 1511 } 1512 1513 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1514 if (ddr_is_active(i)) { 1515 /* Map DDR to BAR 1 */ 1516 cr = (ddr_size(i) - 1) & 0xffff0000; 1517 size += ddr_size(i) & 0xffff0000; 1518 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1519 br = ddr_base(i); 1520 if (br < ddrbase) 1521 ddrbase = br; 1522 1523 /* Use the first available PCIE window */ 1524 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1525 if (win_pcie_cr_read(base, j) != 0) 1526 continue; 1527 1528 win_pcie_br_write(base, j, br); 1529 win_pcie_cr_write(base, j, cr); 1530 break; 1531 } 1532 } 1533 } 1534 1535 /* 1536 * Upper 16 bits in BAR register is interpreted as BAR size 1537 * (in 64 kB units) plus 64kB, so subtract 0x10000 1538 * form value passed to register to get correct value. 1539 */ 1540 size -= 0x10000; 1541 pcie_bar_cr_write(base, 1, size | 1); 1542 pcie_bar_br_write(base, 1, ddrbase | 1543 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1544 pcie_bar_br_write(base, 0, fdt_immr_pa | 1545 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1546 } 1547 1548 static int 1549 decode_win_pcie_valid(void) 1550 { 1551 1552 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1553 } 1554 1555 /************************************************************************** 1556 * IDMA windows routines 1557 **************************************************************************/ 1558 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1559 static int 1560 idma_bare_read(u_long base, int i) 1561 { 1562 uint32_t v; 1563 1564 v = win_idma_bare_read(base); 1565 v &= (1 << i); 1566 1567 return (v >> i); 1568 } 1569 1570 static void 1571 idma_bare_write(u_long base, int i, int val) 1572 { 1573 uint32_t v; 1574 1575 v = win_idma_bare_read(base); 1576 v &= ~(1 << i); 1577 v |= (val << i); 1578 win_idma_bare_write(base, v); 1579 } 1580 1581 /* 1582 * Sets channel protection 'val' for window 'w' on channel 'c' 1583 */ 1584 static void 1585 idma_cap_write(u_long base, int c, int w, int val) 1586 { 1587 uint32_t v; 1588 1589 v = win_idma_cap_read(base, c); 1590 v &= ~(0x3 << (w * 2)); 1591 v |= (val << (w * 2)); 1592 win_idma_cap_write(base, c, v); 1593 } 1594 1595 /* 1596 * Set protection 'val' on all channels for window 'w' 1597 */ 1598 static void 1599 idma_set_prot(u_long base, int w, int val) 1600 { 1601 int c; 1602 1603 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1604 idma_cap_write(base, c, w, val); 1605 } 1606 1607 static int 1608 win_idma_can_remap(int i) 1609 { 1610 1611 /* IDMA decode windows 0-3 have remap capability */ 1612 if (i < 4) 1613 return (1); 1614 1615 return (0); 1616 } 1617 1618 void 1619 decode_win_idma_setup(u_long base) 1620 { 1621 uint32_t br, sz; 1622 int i, j; 1623 1624 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1625 return; 1626 /* 1627 * Disable and clear all IDMA windows, revoke protection for all channels 1628 */ 1629 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1630 1631 idma_bare_write(base, i, 1); 1632 win_idma_br_write(base, i, 0); 1633 win_idma_sz_write(base, i, 0); 1634 if (win_idma_can_remap(i) == 1) 1635 win_idma_har_write(base, i, 0); 1636 } 1637 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1638 win_idma_cap_write(base, i, 0); 1639 1640 /* 1641 * Set up access to all active DRAM banks 1642 */ 1643 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1644 if (ddr_is_active(i)) { 1645 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1646 sz = ((ddr_size(i) - 1) & 0xffff0000); 1647 1648 /* Place DDR entries in non-remapped windows */ 1649 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1650 if (win_idma_can_remap(j) != 1 && 1651 idma_bare_read(base, j) == 1) { 1652 1653 /* Configure window */ 1654 win_idma_br_write(base, j, br); 1655 win_idma_sz_write(base, j, sz); 1656 1657 /* Set protection RW on all channels */ 1658 idma_set_prot(base, j, 0x3); 1659 1660 /* Enable window */ 1661 idma_bare_write(base, j, 0); 1662 break; 1663 } 1664 } 1665 1666 /* 1667 * Remaining targets -- from statically defined table 1668 */ 1669 for (i = 0; i < idma_wins_no; i++) 1670 if (idma_wins[i].target > 0) { 1671 br = (idma_wins[i].base & 0xffff0000) | 1672 (idma_wins[i].attr << 8) | idma_wins[i].target; 1673 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1674 1675 /* Set the first free IDMA window */ 1676 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1677 if (idma_bare_read(base, j) == 0) 1678 continue; 1679 1680 /* Configure window */ 1681 win_idma_br_write(base, j, br); 1682 win_idma_sz_write(base, j, sz); 1683 if (win_idma_can_remap(j) && 1684 idma_wins[j].remap >= 0) 1685 win_idma_har_write(base, j, 1686 idma_wins[j].remap); 1687 1688 /* Set protection RW on all channels */ 1689 idma_set_prot(base, j, 0x3); 1690 1691 /* Enable window */ 1692 idma_bare_write(base, j, 0); 1693 break; 1694 } 1695 } 1696 } 1697 1698 int 1699 decode_win_idma_valid(void) 1700 { 1701 const struct decode_win *wintab; 1702 int c, i, j, rv; 1703 uint32_t b, e, s; 1704 1705 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1706 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1707 return (0); 1708 } 1709 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1710 if (ddr_is_active(i)) 1711 c++; 1712 1713 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1714 printf("IDMA windows: too many entries: %d, available: %d\n", 1715 idma_wins_no, MV_WIN_IDMA_MAX - c); 1716 return (0); 1717 } 1718 1719 wintab = idma_wins; 1720 rv = 1; 1721 for (i = 0; i < idma_wins_no; i++, wintab++) { 1722 1723 if (wintab->target == 0) { 1724 printf("IDMA window#%d: DDR target window is not " 1725 "supposed to be reprogrammed!\n", i); 1726 rv = 0; 1727 } 1728 1729 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1730 printf("IDMA window#%d: not capable of remapping, but " 1731 "val 0x%08x defined\n", i, wintab->remap); 1732 rv = 0; 1733 } 1734 1735 s = wintab->size; 1736 b = wintab->base; 1737 e = b + s - 1; 1738 if (s > (0xFFFFFFFF - b + 1)) { 1739 /* XXX this boundary check should account for 64bit and 1740 * remapping.. */ 1741 printf("IDMA window#%d: no space for size 0x%08x at " 1742 "0x%08x\n", i, s, b); 1743 rv = 0; 1744 continue; 1745 } 1746 1747 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1748 if (j >= 0) { 1749 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1750 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1751 idma_wins[j].base, 1752 idma_wins[j].base + idma_wins[j].size - 1); 1753 rv = 0; 1754 } 1755 } 1756 1757 return (rv); 1758 } 1759 1760 void 1761 decode_win_idma_dump(u_long base) 1762 { 1763 int i; 1764 1765 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1766 return; 1767 1768 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1769 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1770 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1771 1772 if (win_idma_can_remap(i)) 1773 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1774 1775 printf("\n"); 1776 } 1777 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1778 printf("IDMA channel#%d: ap 0x%08x\n", i, 1779 win_idma_cap_read(base, i)); 1780 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1781 } 1782 #else 1783 1784 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1785 int 1786 decode_win_idma_valid(void) 1787 { 1788 1789 return (1); 1790 } 1791 1792 void 1793 decode_win_idma_setup(u_long base) 1794 { 1795 } 1796 1797 void 1798 decode_win_idma_dump(u_long base) 1799 { 1800 } 1801 #endif 1802 1803 /************************************************************************** 1804 * XOR windows routines 1805 **************************************************************************/ 1806 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1807 static int 1808 xor_ctrl_read(u_long base, int i, int c, int e) 1809 { 1810 uint32_t v; 1811 v = win_xor_ctrl_read(base, c, e); 1812 v &= (1 << i); 1813 1814 return (v >> i); 1815 } 1816 1817 static void 1818 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1819 { 1820 uint32_t v; 1821 1822 v = win_xor_ctrl_read(base, c, e); 1823 v &= ~(1 << i); 1824 v |= (val << i); 1825 win_xor_ctrl_write(base, c, e, v); 1826 } 1827 1828 /* 1829 * Set channel protection 'val' for window 'w' on channel 'c' 1830 */ 1831 static void 1832 xor_chan_write(u_long base, int c, int e, int w, int val) 1833 { 1834 uint32_t v; 1835 1836 v = win_xor_ctrl_read(base, c, e); 1837 v &= ~(0x3 << (w * 2 + 16)); 1838 v |= (val << (w * 2 + 16)); 1839 win_xor_ctrl_write(base, c, e, v); 1840 } 1841 1842 /* 1843 * Set protection 'val' on all channels for window 'w' on engine 'e' 1844 */ 1845 static void 1846 xor_set_prot(u_long base, int w, int e, int val) 1847 { 1848 int c; 1849 1850 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1851 xor_chan_write(base, c, e, w, val); 1852 } 1853 1854 static int 1855 win_xor_can_remap(int i) 1856 { 1857 1858 /* XOR decode windows 0-3 have remap capability */ 1859 if (i < 4) 1860 return (1); 1861 1862 return (0); 1863 } 1864 1865 static int 1866 xor_max_eng(void) 1867 { 1868 uint32_t dev, rev; 1869 1870 soc_id(&dev, &rev); 1871 switch (dev) { 1872 case MV_DEV_88F6281: 1873 case MV_DEV_88F6282: 1874 case MV_DEV_MV78130: 1875 case MV_DEV_MV78160: 1876 case MV_DEV_MV78230: 1877 case MV_DEV_MV78260: 1878 case MV_DEV_MV78460: 1879 return (2); 1880 case MV_DEV_MV78100: 1881 case MV_DEV_MV78100_Z0: 1882 return (1); 1883 default: 1884 return (0); 1885 } 1886 } 1887 1888 static void 1889 xor_active_dram(u_long base, int c, int e, int *window) 1890 { 1891 uint32_t br, sz; 1892 int i, m, w; 1893 1894 /* 1895 * Set up access to all active DRAM banks 1896 */ 1897 m = xor_max_eng(); 1898 for (i = 0; i < m; i++) 1899 if (ddr_is_active(i)) { 1900 br = ddr_base(i) | (ddr_attr(i) << 8) | 1901 ddr_target(i); 1902 sz = ((ddr_size(i) - 1) & 0xffff0000); 1903 1904 /* Place DDR entries in non-remapped windows */ 1905 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1906 if (win_xor_can_remap(w) != 1 && 1907 (xor_ctrl_read(base, w, c, e) == 0) && 1908 w > *window) { 1909 /* Configure window */ 1910 win_xor_br_write(base, w, e, br); 1911 win_xor_sz_write(base, w, e, sz); 1912 1913 /* Set protection RW on all channels */ 1914 xor_set_prot(base, w, e, 0x3); 1915 1916 /* Enable window */ 1917 xor_ctrl_write(base, w, c, e, 1); 1918 (*window)++; 1919 break; 1920 } 1921 } 1922 } 1923 1924 void 1925 decode_win_xor_setup(u_long base) 1926 { 1927 uint32_t br, sz; 1928 int i, j, z, e = 1, m, window; 1929 1930 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1931 return; 1932 1933 /* 1934 * Disable and clear all XOR windows, revoke protection for all 1935 * channels 1936 */ 1937 m = xor_max_eng(); 1938 for (j = 0; j < m; j++, e--) { 1939 1940 /* Number of non-remaped windows */ 1941 window = MV_XOR_NON_REMAP - 1; 1942 1943 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1944 win_xor_br_write(base, i, e, 0); 1945 win_xor_sz_write(base, i, e, 0); 1946 } 1947 1948 if (win_xor_can_remap(i) == 1) 1949 win_xor_har_write(base, i, e, 0); 1950 1951 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1952 win_xor_ctrl_write(base, i, e, 0); 1953 xor_active_dram(base, i, e, &window); 1954 } 1955 1956 /* 1957 * Remaining targets -- from a statically defined table 1958 */ 1959 for (i = 0; i < xor_wins_no; i++) 1960 if (xor_wins[i].target > 0) { 1961 br = (xor_wins[i].base & 0xffff0000) | 1962 (xor_wins[i].attr << 8) | 1963 xor_wins[i].target; 1964 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1965 1966 /* Set the first free XOR window */ 1967 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1968 if (xor_ctrl_read(base, z, 0, e) && 1969 xor_ctrl_read(base, z, 1, e)) 1970 continue; 1971 1972 /* Configure window */ 1973 win_xor_br_write(base, z, e, br); 1974 win_xor_sz_write(base, z, e, sz); 1975 if (win_xor_can_remap(z) && 1976 xor_wins[z].remap >= 0) 1977 win_xor_har_write(base, z, e, 1978 xor_wins[z].remap); 1979 1980 /* Set protection RW on all channels */ 1981 xor_set_prot(base, z, e, 0x3); 1982 1983 /* Enable window */ 1984 xor_ctrl_write(base, z, 0, e, 1); 1985 xor_ctrl_write(base, z, 1, e, 1); 1986 break; 1987 } 1988 } 1989 } 1990 } 1991 1992 int 1993 decode_win_xor_valid(void) 1994 { 1995 const struct decode_win *wintab; 1996 int c, i, j, rv; 1997 uint32_t b, e, s; 1998 1999 if (xor_wins_no > MV_WIN_XOR_MAX) { 2000 printf("XOR windows: too many entries: %d\n", xor_wins_no); 2001 return (0); 2002 } 2003 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 2004 if (ddr_is_active(i)) 2005 c++; 2006 2007 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 2008 printf("XOR windows: too many entries: %d, available: %d\n", 2009 xor_wins_no, MV_WIN_IDMA_MAX - c); 2010 return (0); 2011 } 2012 2013 wintab = xor_wins; 2014 rv = 1; 2015 for (i = 0; i < xor_wins_no; i++, wintab++) { 2016 2017 if (wintab->target == 0) { 2018 printf("XOR window#%d: DDR target window is not " 2019 "supposed to be reprogrammed!\n", i); 2020 rv = 0; 2021 } 2022 2023 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 2024 printf("XOR window#%d: not capable of remapping, but " 2025 "val 0x%08x defined\n", i, wintab->remap); 2026 rv = 0; 2027 } 2028 2029 s = wintab->size; 2030 b = wintab->base; 2031 e = b + s - 1; 2032 if (s > (0xFFFFFFFF - b + 1)) { 2033 /* 2034 * XXX this boundary check should account for 64bit 2035 * and remapping.. 2036 */ 2037 printf("XOR window#%d: no space for size 0x%08x at " 2038 "0x%08x\n", i, s, b); 2039 rv = 0; 2040 continue; 2041 } 2042 2043 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 2044 if (j >= 0) { 2045 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 2046 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2047 xor_wins[j].base, 2048 xor_wins[j].base + xor_wins[j].size - 1); 2049 rv = 0; 2050 } 2051 } 2052 2053 return (rv); 2054 } 2055 2056 void 2057 decode_win_xor_dump(u_long base) 2058 { 2059 int i, j; 2060 int e = 1; 2061 2062 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2063 return; 2064 2065 for (j = 0; j < xor_max_eng(); j++, e--) { 2066 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2067 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2068 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2069 2070 if (win_xor_can_remap(i)) 2071 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2072 2073 printf("\n"); 2074 } 2075 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2076 printf("XOR control#%d: 0x%08x\n", i, 2077 win_xor_ctrl_read(base, i, e)); 2078 } 2079 } 2080 2081 #else 2082 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2083 static int 2084 decode_win_xor_valid(void) 2085 { 2086 2087 return (1); 2088 } 2089 2090 static void 2091 decode_win_xor_setup(u_long base) 2092 { 2093 } 2094 2095 static void 2096 decode_win_xor_dump(u_long base) 2097 { 2098 } 2099 #endif 2100 2101 /************************************************************************** 2102 * SATA windows routines 2103 **************************************************************************/ 2104 static void 2105 decode_win_sata_setup(u_long base) 2106 { 2107 uint32_t cr, br; 2108 int i, j; 2109 2110 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2111 return; 2112 2113 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2114 win_sata_cr_write(base, i, 0); 2115 win_sata_br_write(base, i, 0); 2116 } 2117 2118 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2119 if (ddr_is_active(i)) { 2120 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2121 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2122 br = ddr_base(i); 2123 2124 /* Use the first available SATA window */ 2125 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2126 if ((win_sata_cr_read(base, j) & 1) != 0) 2127 continue; 2128 2129 win_sata_br_write(base, j, br); 2130 win_sata_cr_write(base, j, cr); 2131 break; 2132 } 2133 } 2134 } 2135 2136 #ifdef SOC_MV_ARMADA38X 2137 /* 2138 * Configure AHCI decoding windows 2139 */ 2140 static void 2141 decode_win_ahci_setup(u_long base) 2142 { 2143 uint32_t br, cr, sz; 2144 int i, j; 2145 2146 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2147 win_sata_cr_write(base, i, 0); 2148 win_sata_br_write(base, i, 0); 2149 win_sata_sz_write(base, i, 0); 2150 } 2151 2152 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2153 if (ddr_is_active(i)) { 2154 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2155 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2156 IO_WIN_ENA_MASK; 2157 br = ddr_base(i); 2158 sz = (ddr_size(i) - 1) & 2159 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2160 2161 /* Use first available SATA window */ 2162 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2163 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2164 continue; 2165 2166 /* BASE is set to DRAM base (0x00000000) */ 2167 win_sata_br_write(base, j, br); 2168 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2169 win_sata_cr_write(base, j, cr); 2170 /* SIZE is set to 16MB - max value */ 2171 win_sata_sz_write(base, j, sz); 2172 break; 2173 } 2174 } 2175 } 2176 } 2177 2178 static void 2179 decode_win_ahci_dump(u_long base) 2180 { 2181 int i; 2182 2183 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2184 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2185 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2186 win_sata_sz_read(base,i)); 2187 } 2188 2189 #else 2190 /* 2191 * Provide dummy functions to satisfy the build 2192 * for SoC's not equipped with AHCI controller 2193 */ 2194 static void 2195 decode_win_ahci_setup(u_long base) 2196 { 2197 } 2198 2199 static void 2200 decode_win_ahci_dump(u_long base) 2201 { 2202 } 2203 #endif 2204 2205 static int 2206 decode_win_sata_valid(void) 2207 { 2208 uint32_t dev, rev; 2209 2210 soc_id(&dev, &rev); 2211 if (dev == MV_DEV_88F5281) 2212 return (1); 2213 2214 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2215 } 2216 2217 static void 2218 decode_win_sdhci_setup(u_long base) 2219 { 2220 uint32_t cr, br; 2221 int i, j; 2222 2223 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2224 win_sdhci_cr_write(base, i, 0); 2225 win_sdhci_br_write(base, i, 0); 2226 } 2227 2228 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2229 if (ddr_is_active(i)) { 2230 br = ddr_base(i); 2231 cr = (((ddr_size(i) - 1) & 2232 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2233 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2234 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2235 IO_WIN_ENA_MASK); 2236 2237 /* Use the first available SDHCI window */ 2238 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2239 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2240 continue; 2241 2242 win_sdhci_cr_write(base, j, cr); 2243 win_sdhci_br_write(base, j, br); 2244 break; 2245 } 2246 } 2247 } 2248 2249 static void 2250 decode_win_sdhci_dump(u_long base) 2251 { 2252 int i; 2253 2254 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2255 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2256 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2257 } 2258 2259 static int 2260 decode_win_sdhci_valid(void) 2261 { 2262 2263 #ifdef SOC_MV_ARMADA38X 2264 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2265 #endif 2266 2267 /* Satisfy platforms not equipped with this controller. */ 2268 return (1); 2269 } 2270 2271 /************************************************************************** 2272 * FDT parsing routines. 2273 **************************************************************************/ 2274 2275 static int 2276 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2277 int *tuplesize) 2278 { 2279 phandle_t node; 2280 pcell_t addr_cells, par_addr_cells, size_cells; 2281 int len, tuple_size, tuples_count; 2282 2283 node = OF_finddevice(nodename); 2284 if (node == -1) 2285 return (EINVAL); 2286 2287 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2288 return (ENXIO); 2289 2290 par_addr_cells = fdt_parent_addr_cells(node); 2291 if (par_addr_cells > 2) 2292 return (ERANGE); 2293 2294 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2295 size_cells); 2296 2297 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2298 len = OF_getprop(node, "ranges", buf, size); 2299 2300 /* 2301 * XXX this does not handle the empty 'ranges;' case, which is 2302 * legitimate and should be allowed. 2303 */ 2304 tuples_count = len / tuple_size; 2305 if (tuples_count <= 0) 2306 return (ERANGE); 2307 2308 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2309 return (ERANGE); 2310 2311 *tuples = tuples_count; 2312 *tuplesize = tuple_size; 2313 return (0); 2314 } 2315 2316 static int 2317 win_cpu_from_dt(void) 2318 { 2319 pcell_t ranges[48]; 2320 phandle_t node; 2321 int i, entry_size, err, t, tuple_size, tuples; 2322 u_long sram_base, sram_size; 2323 2324 t = 0; 2325 /* Retrieve 'ranges' property of '/localbus' node. */ 2326 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2327 &tuples, &tuple_size)) == 0) { 2328 /* 2329 * Fill CPU decode windows table. 2330 */ 2331 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2332 2333 entry_size = tuple_size / sizeof(pcell_t); 2334 cpu_wins_no = tuples; 2335 2336 /* Check range */ 2337 if (tuples > nitems(cpu_win_tbl)) { 2338 debugf("too many tuples to fit into cpu_win_tbl\n"); 2339 return (ENOMEM); 2340 } 2341 2342 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2343 cpu_win_tbl[t].target = 1; 2344 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2345 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2346 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2347 cpu_win_tbl[t].remap = ~0; 2348 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2349 "size = 0x%0x remap = 0x%0x\n", 2350 cpu_win_tbl[t].target, 2351 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2352 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2353 } 2354 } 2355 2356 /* 2357 * Retrieve CESA SRAM data. 2358 */ 2359 if ((node = OF_finddevice("sram")) != -1) 2360 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2361 goto moveon; 2362 2363 if ((node = OF_finddevice("/")) == 0) 2364 return (ENXIO); 2365 2366 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2367 /* SRAM block is not always present. */ 2368 return (0); 2369 moveon: 2370 sram_base = sram_size = 0; 2371 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2372 return (EINVAL); 2373 2374 /* Check range */ 2375 if (t >= nitems(cpu_win_tbl)) { 2376 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2377 return (ENOMEM); 2378 } 2379 2380 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2381 #ifdef SOC_MV_ARMADA38X 2382 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2383 #else 2384 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2385 #endif 2386 cpu_win_tbl[t].base = sram_base; 2387 cpu_win_tbl[t].size = sram_size; 2388 cpu_win_tbl[t].remap = ~0; 2389 cpu_wins_no++; 2390 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2391 2392 /* Check if there is a second CESA node */ 2393 while ((node = OF_peer(node)) != 0) { 2394 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2395 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2396 return (EINVAL); 2397 break; 2398 } 2399 } 2400 2401 if (node == 0) 2402 return (0); 2403 2404 t++; 2405 if (t >= nitems(cpu_win_tbl)) { 2406 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2407 return (ENOMEM); 2408 } 2409 2410 /* Configure window for CESA1 */ 2411 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2412 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2413 cpu_win_tbl[t].base = sram_base; 2414 cpu_win_tbl[t].size = sram_size; 2415 cpu_win_tbl[t].remap = ~0; 2416 cpu_wins_no++; 2417 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2418 2419 return (0); 2420 } 2421 2422 static int 2423 fdt_win_process(phandle_t child) 2424 { 2425 int i; 2426 struct soc_node_spec *soc_node; 2427 int addr_cells, size_cells; 2428 pcell_t reg[8]; 2429 u_long size, base; 2430 2431 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2432 2433 soc_node = &soc_nodes[i]; 2434 2435 /* Setup only for enabled devices */ 2436 if (ofw_bus_node_status_okay(child) == 0) 2437 continue; 2438 2439 if (!ofw_bus_node_is_compatible(child, soc_node->compat)) 2440 continue; 2441 2442 if (fdt_addrsize_cells(OF_parent(child), &addr_cells, 2443 &size_cells)) 2444 return (ENXIO); 2445 2446 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) 2447 return (ENOMEM); 2448 2449 if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) 2450 return (EINVAL); 2451 2452 if (addr_cells <= 2) 2453 base = fdt_data_get(®[0], addr_cells); 2454 else 2455 base = fdt_data_get(®[addr_cells - 2], 2); 2456 size = fdt_data_get(®[addr_cells], size_cells); 2457 2458 base = (base & 0x000fffff) | fdt_immr_va; 2459 if (soc_node->decode_handler != NULL) 2460 soc_node->decode_handler(base); 2461 else 2462 return (ENXIO); 2463 2464 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2465 soc_node->dump_handler(base); 2466 } 2467 2468 return (0); 2469 } 2470 static int 2471 fdt_win_setup(void) 2472 { 2473 phandle_t node, child, sb; 2474 phandle_t child_pci; 2475 int err; 2476 2477 sb = 0; 2478 node = OF_finddevice("/"); 2479 if (node == -1) 2480 panic("fdt_win_setup: no root node"); 2481 2482 /* 2483 * Traverse through all children of root and simple-bus nodes. 2484 * For each found device retrieve decode windows data (if applicable). 2485 */ 2486 child = OF_child(node); 2487 while (child != 0) { 2488 /* Lookup for callback and run */ 2489 err = fdt_win_process(child); 2490 if (err != 0) 2491 return (err); 2492 2493 /* Process Marvell Armada-XP/38x PCIe controllers */ 2494 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { 2495 child_pci = OF_child(child); 2496 while (child_pci != 0) { 2497 err = fdt_win_process(child_pci); 2498 if (err != 0) 2499 return (err); 2500 2501 child_pci = OF_peer(child_pci); 2502 } 2503 } 2504 2505 /* 2506 * Once done with root-level children let's move down to 2507 * simple-bus and its children. 2508 */ 2509 child = OF_peer(child); 2510 if ((child == 0) && (node == OF_finddevice("/"))) { 2511 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2512 if (node == 0) 2513 return (ENXIO); 2514 child = OF_child(node); 2515 } 2516 /* 2517 * Next, move one more level down to internal-regs node (if 2518 * it is present) and its children. This node also have 2519 * "simple-bus" compatible. 2520 */ 2521 if ((child == 0) && (node == sb)) { 2522 node = fdt_find_compatible(node, "simple-bus", 0); 2523 if (node == 0) 2524 return (0); 2525 child = OF_child(node); 2526 } 2527 } 2528 2529 return (0); 2530 } 2531 2532 static void 2533 fdt_fixup_busfreq(phandle_t root) 2534 { 2535 phandle_t sb; 2536 pcell_t freq; 2537 2538 freq = cpu_to_fdt32(get_tclk()); 2539 2540 /* 2541 * Fix bus speed in cpu node 2542 */ 2543 if ((sb = OF_finddevice("cpu")) != 0) 2544 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2545 OF_setprop(sb, "bus-frequency", (void *)&freq, 2546 sizeof(freq)); 2547 2548 /* 2549 * This fixup sets the simple-bus bus-frequency property. 2550 */ 2551 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2552 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2553 } 2554 2555 static void 2556 fdt_fixup_ranges(phandle_t root) 2557 { 2558 phandle_t node; 2559 pcell_t par_addr_cells, addr_cells, size_cells; 2560 pcell_t ranges[3], reg[2], *rangesptr; 2561 int len, tuple_size, tuples_count; 2562 uint32_t base; 2563 2564 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2565 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2566 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2567 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2568 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2569 addr_cells + size_cells); 2570 len = OF_getprop(node, "ranges", ranges, 2571 sizeof(ranges)); 2572 tuples_count = len / tuple_size; 2573 /* Unexpected settings are not supported */ 2574 if (tuples_count != 1) 2575 goto fixup_failed; 2576 2577 rangesptr = &ranges[0]; 2578 rangesptr += par_addr_cells; 2579 base = fdt_data_get((void *)rangesptr, addr_cells); 2580 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2581 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2582 sizeof(ranges)) < 0) 2583 goto fixup_failed; 2584 } 2585 } 2586 2587 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2588 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2589 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2590 &size_cells) == 0) { 2591 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2592 size_cells); 2593 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2594 tuples_count = len / tuple_size; 2595 /* Unexpected settings are not supported */ 2596 if (tuples_count != 1) 2597 goto fixup_failed; 2598 2599 base = fdt_data_get((void *)®[0], par_addr_cells); 2600 base &= ~0xFF000000; 2601 base |= fdt_immr_pa; 2602 reg[0] = cpu_to_fdt32(base); 2603 if (OF_setprop(node, "reg", (void *)®[0], 2604 sizeof(reg)) < 0) 2605 goto fixup_failed; 2606 } 2607 } 2608 /* Fix-up succeeded. May return and continue */ 2609 return; 2610 2611 fixup_failed: 2612 while (1) { 2613 /* 2614 * In case of any error while fixing ranges just hang. 2615 * 1. No message can be displayed yet since console 2616 * is not initialized. 2617 * 2. Going further will cause failure on bus_space_map() 2618 * relying on the wrong ranges or data abort when 2619 * accessing PCIe registers. 2620 */ 2621 } 2622 } 2623 2624 struct fdt_fixup_entry fdt_fixup_table[] = { 2625 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2626 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2627 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2628 { NULL, NULL } 2629 }; 2630 2631 #ifndef INTRNG 2632 static int 2633 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2634 int *pol) 2635 { 2636 2637 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2638 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2639 return (ENXIO); 2640 2641 *interrupt = fdt32_to_cpu(intr[0]); 2642 *trig = INTR_TRIGGER_CONFORM; 2643 *pol = INTR_POLARITY_CONFORM; 2644 2645 return (0); 2646 } 2647 2648 fdt_pic_decode_t fdt_pic_table[] = { 2649 #ifdef SOC_MV_ARMADA38X 2650 &gic_decode_fdt, 2651 #endif 2652 &fdt_pic_decode_ic, 2653 NULL 2654 }; 2655 #endif 2656 2657 uint64_t 2658 get_sar_value(void) 2659 { 2660 uint32_t sar_low, sar_high; 2661 2662 #if defined(SOC_MV_ARMADAXP) 2663 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2664 SAMPLE_AT_RESET_HI); 2665 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2666 SAMPLE_AT_RESET_LO); 2667 #elif defined(SOC_MV_ARMADA38X) 2668 sar_high = 0; 2669 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2670 SAMPLE_AT_RESET); 2671 #else 2672 /* 2673 * TODO: Add getting proper values for other SoC configurations 2674 */ 2675 sar_high = 0; 2676 sar_low = 0; 2677 #endif 2678 2679 return (((uint64_t)sar_high << 32) | sar_low); 2680 } 2681