1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cesa_valid(void); 80 static int decode_win_cpu_valid(void); 81 static int decode_win_usb_valid(void); 82 static int decode_win_usb3_valid(void); 83 static int decode_win_eth_valid(void); 84 static int decode_win_pcie_valid(void); 85 static int decode_win_sata_valid(void); 86 static int decode_win_sdhci_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 static void decode_win_cpu_setup(void); 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_cesa_setup(u_long); 96 static void decode_win_usb_setup(u_long); 97 static void decode_win_usb3_setup(u_long); 98 static void decode_win_eth_setup(u_long); 99 static void decode_win_sata_setup(u_long); 100 static void decode_win_ahci_setup(u_long); 101 static void decode_win_sdhci_setup(u_long); 102 103 static void decode_win_idma_setup(u_long); 104 static void decode_win_xor_setup(u_long); 105 106 static void decode_win_cesa_dump(u_long); 107 static void decode_win_usb_dump(u_long); 108 static void decode_win_usb3_dump(u_long); 109 static void decode_win_eth_dump(u_long base); 110 static void decode_win_idma_dump(u_long base); 111 static void decode_win_xor_dump(u_long base); 112 static void decode_win_ahci_dump(u_long base); 113 static void decode_win_sdhci_dump(u_long); 114 115 static int fdt_get_ranges(const char *, void *, int, int *, int *); 116 #ifdef SOC_MV_ARMADA38X 117 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 118 int *trig, int *pol); 119 #endif 120 121 static int win_cpu_from_dt(void); 122 static int fdt_win_setup(void); 123 124 static uint32_t dev_mask = 0; 125 static int cpu_wins_no = 0; 126 static int eth_port = 0; 127 static int usb_port = 0; 128 129 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 130 131 const struct decode_win *cpu_wins = cpu_win_tbl; 132 133 typedef void (*decode_win_setup_t)(u_long); 134 typedef void (*dump_win_t)(u_long); 135 136 /* 137 * The power status of device feature is only supported on 138 * Kirkwood and Discovery SoCs. 139 */ 140 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 141 #define SOC_MV_POWER_STAT_SUPPORTED 1 142 #else 143 #define SOC_MV_POWER_STAT_SUPPORTED 0 144 #endif 145 146 struct soc_node_spec { 147 const char *compat; 148 decode_win_setup_t decode_handler; 149 dump_win_t dump_handler; 150 }; 151 152 static struct soc_node_spec soc_nodes[] = { 153 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 154 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 155 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 156 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 157 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 158 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, 159 { "mrvl,sata", &decode_win_sata_setup, NULL }, 160 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 161 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 162 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, 163 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 164 { NULL, NULL, NULL }, 165 }; 166 167 struct fdt_pm_mask_entry { 168 char *compat; 169 uint32_t mask; 170 }; 171 172 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 173 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 174 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 175 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 176 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 177 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 178 { "mrvl,xor", CPU_PM_CTRL_XOR }, 179 { "mrvl,sata", CPU_PM_CTRL_SATA }, 180 181 { NULL, 0 } 182 }; 183 184 static __inline int 185 pm_is_disabled(uint32_t mask) 186 { 187 #if SOC_MV_POWER_STAT_SUPPORTED 188 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 189 #else 190 return (0); 191 #endif 192 } 193 194 /* 195 * Disable device using power management register. 196 * 1 - Device Power On 197 * 0 - Device Power Off 198 * Mask can be set in loader. 199 * EXAMPLE: 200 * loader> set hw.pm-disable-mask=0x2 201 * 202 * Common mask: 203 * |-------------------------------| 204 * | Device | Kirkwood | Discovery | 205 * |-------------------------------| 206 * | USB0 | 0x00008 | 0x020000 | 207 * |-------------------------------| 208 * | USB1 | - | 0x040000 | 209 * |-------------------------------| 210 * | USB2 | - | 0x080000 | 211 * |-------------------------------| 212 * | GE0 | 0x00001 | 0x000002 | 213 * |-------------------------------| 214 * | GE1 | - | 0x000004 | 215 * |-------------------------------| 216 * | IDMA | - | 0x100000 | 217 * |-------------------------------| 218 * | XOR | 0x10000 | 0x200000 | 219 * |-------------------------------| 220 * | CESA | 0x20000 | 0x400000 | 221 * |-------------------------------| 222 * | SATA | 0x04000 | 0x004000 | 223 * --------------------------------| 224 * This feature can be used only on Kirkwood and Discovery 225 * machines. 226 */ 227 static __inline void 228 pm_disable_device(int mask) 229 { 230 #ifdef DIAGNOSTIC 231 uint32_t reg; 232 233 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 234 printf("Power Management Register: 0%x\n", reg); 235 236 reg &= ~mask; 237 soc_power_ctrl_set(reg); 238 printf("Device %x is disabled\n", mask); 239 240 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 241 printf("Power Management Register: 0%x\n", reg); 242 #endif 243 } 244 245 int 246 fdt_pm(phandle_t node) 247 { 248 uint32_t cpu_pm_ctrl; 249 int i, ena, compat; 250 251 ena = 1; 252 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 253 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 254 if (dev_mask & (1 << i)) 255 continue; 256 257 compat = ofw_bus_node_is_compatible(node, 258 fdt_pm_mask_table[i].compat); 259 #if defined(SOC_MV_KIRKWOOD) 260 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 261 dev_mask |= (1 << i); 262 ena = 0; 263 break; 264 } else if (compat) { 265 dev_mask |= (1 << i); 266 break; 267 } 268 #else 269 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 270 dev_mask |= (1 << i); 271 ena = 0; 272 break; 273 } else if (compat) { 274 dev_mask |= (1 << i); 275 break; 276 } 277 #endif 278 } 279 280 return (ena); 281 } 282 283 uint32_t 284 read_cpu_ctrl(uint32_t reg) 285 { 286 287 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 288 } 289 290 void 291 write_cpu_ctrl(uint32_t reg, uint32_t val) 292 { 293 294 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 295 } 296 297 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 298 uint32_t 299 read_cpu_mp_clocks(uint32_t reg) 300 { 301 302 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 303 } 304 305 void 306 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 307 { 308 309 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 310 } 311 312 uint32_t 313 read_cpu_misc(uint32_t reg) 314 { 315 316 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 317 } 318 319 void 320 write_cpu_misc(uint32_t reg, uint32_t val) 321 { 322 323 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 324 } 325 #endif 326 327 void 328 cpu_reset(void) 329 { 330 331 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 332 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 333 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 334 #else 335 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 336 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 337 #endif 338 while (1); 339 } 340 341 uint32_t 342 cpu_extra_feat(void) 343 { 344 uint32_t dev, rev; 345 uint32_t ef = 0; 346 347 soc_id(&dev, &rev); 348 349 switch (dev) { 350 case MV_DEV_88F6281: 351 case MV_DEV_88F6282: 352 case MV_DEV_88RC8180: 353 case MV_DEV_MV78100_Z0: 354 case MV_DEV_MV78100: 355 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 356 break; 357 case MV_DEV_88F5182: 358 case MV_DEV_88F5281: 359 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 360 break; 361 default: 362 if (bootverbose) 363 printf("This ARM Core does not support any extra features\n"); 364 } 365 366 return (ef); 367 } 368 369 /* 370 * Get the power status of device. This feature is only supported on 371 * Kirkwood and Discovery SoCs. 372 */ 373 uint32_t 374 soc_power_ctrl_get(uint32_t mask) 375 { 376 377 #if SOC_MV_POWER_STAT_SUPPORTED 378 if (mask != CPU_PM_CTRL_NONE) 379 mask &= read_cpu_ctrl(CPU_PM_CTRL); 380 381 return (mask); 382 #else 383 return (mask); 384 #endif 385 } 386 387 /* 388 * Set the power status of device. This feature is only supported on 389 * Kirkwood and Discovery SoCs. 390 */ 391 void 392 soc_power_ctrl_set(uint32_t mask) 393 { 394 395 #if !defined(SOC_MV_ORION) 396 if (mask != CPU_PM_CTRL_NONE) 397 write_cpu_ctrl(CPU_PM_CTRL, mask); 398 #endif 399 } 400 401 void 402 soc_id(uint32_t *dev, uint32_t *rev) 403 { 404 405 /* 406 * Notice: system identifiers are available in the registers range of 407 * PCIE controller, so using this function is only allowed (and 408 * possible) after the internal registers range has been mapped in via 409 * devmap_bootstrap(). 410 */ 411 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 412 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 413 } 414 415 static void 416 soc_identify(void) 417 { 418 uint32_t d, r, size, mode; 419 const char *dev; 420 const char *rev; 421 422 soc_id(&d, &r); 423 424 printf("SOC: "); 425 if (bootverbose) 426 printf("(0x%4x:0x%02x) ", d, r); 427 428 rev = ""; 429 switch (d) { 430 case MV_DEV_88F5181: 431 dev = "Marvell 88F5181"; 432 if (r == 3) 433 rev = "B1"; 434 break; 435 case MV_DEV_88F5182: 436 dev = "Marvell 88F5182"; 437 if (r == 2) 438 rev = "A2"; 439 break; 440 case MV_DEV_88F5281: 441 dev = "Marvell 88F5281"; 442 if (r == 4) 443 rev = "D0"; 444 else if (r == 5) 445 rev = "D1"; 446 else if (r == 6) 447 rev = "D2"; 448 break; 449 case MV_DEV_88F6281: 450 dev = "Marvell 88F6281"; 451 if (r == 0) 452 rev = "Z0"; 453 else if (r == 2) 454 rev = "A0"; 455 else if (r == 3) 456 rev = "A1"; 457 break; 458 case MV_DEV_88RC8180: 459 dev = "Marvell 88RC8180"; 460 break; 461 case MV_DEV_88RC9480: 462 dev = "Marvell 88RC9480"; 463 break; 464 case MV_DEV_88RC9580: 465 dev = "Marvell 88RC9580"; 466 break; 467 case MV_DEV_88F6781: 468 dev = "Marvell 88F6781"; 469 if (r == 2) 470 rev = "Y0"; 471 break; 472 case MV_DEV_88F6282: 473 dev = "Marvell 88F6282"; 474 if (r == 0) 475 rev = "A0"; 476 else if (r == 1) 477 rev = "A1"; 478 break; 479 case MV_DEV_88F6828: 480 dev = "Marvell 88F6828"; 481 break; 482 case MV_DEV_88F6820: 483 dev = "Marvell 88F6820"; 484 break; 485 case MV_DEV_88F6810: 486 dev = "Marvell 88F6810"; 487 break; 488 case MV_DEV_MV78100_Z0: 489 dev = "Marvell MV78100 Z0"; 490 break; 491 case MV_DEV_MV78100: 492 dev = "Marvell MV78100"; 493 break; 494 case MV_DEV_MV78160: 495 dev = "Marvell MV78160"; 496 break; 497 case MV_DEV_MV78260: 498 dev = "Marvell MV78260"; 499 break; 500 case MV_DEV_MV78460: 501 dev = "Marvell MV78460"; 502 break; 503 default: 504 dev = "UNKNOWN"; 505 break; 506 } 507 508 printf("%s", dev); 509 if (*rev != '\0') 510 printf(" rev %s", rev); 511 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 512 513 mode = read_cpu_ctrl(CPU_CONFIG); 514 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 515 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 516 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 517 518 switch (d) { 519 case MV_DEV_88F6281: 520 case MV_DEV_88F6282: 521 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 522 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 523 mode ? "write-through" : "write-back"); 524 break; 525 case MV_DEV_MV78100: 526 mode = read_cpu_ctrl(CPU_CONTROL); 527 size = mode & CPU_CONTROL_L2_SIZE; 528 mode = mode & CPU_CONTROL_L2_MODE; 529 printf(" %s set-associative %s unified L2 cache\n", 530 size ? "256KB 4-way" : "512KB 8-way", 531 mode ? "write-through" : "write-back"); 532 break; 533 default: 534 break; 535 } 536 } 537 538 static void 539 platform_identify(void *dummy) 540 { 541 542 soc_identify(); 543 544 /* 545 * XXX Board identification e.g. read out from FPGA or similar should 546 * go here 547 */ 548 } 549 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 550 NULL); 551 552 #ifdef KDB 553 static void 554 mv_enter_debugger(void *dummy) 555 { 556 557 if (boothowto & RB_KDB) 558 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 559 } 560 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 561 #endif 562 563 int 564 soc_decode_win(void) 565 { 566 uint32_t dev, rev; 567 int mask, err; 568 569 mask = 0; 570 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 571 572 if (mask != 0) 573 pm_disable_device(mask); 574 575 /* Retrieve data about physical addresses from device tree. */ 576 if ((err = win_cpu_from_dt()) != 0) 577 return (err); 578 579 /* Retrieve our ID: some windows facilities vary between SoC models */ 580 soc_id(&dev, &rev); 581 582 #ifdef SOC_MV_ARMADAXP 583 if ((err = decode_win_sdram_fixup()) != 0) 584 return(err); 585 #endif 586 587 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 588 !decode_win_eth_valid() || !decode_win_idma_valid() || 589 !decode_win_pcie_valid() || !decode_win_sata_valid() || 590 !decode_win_xor_valid() || !decode_win_usb3_valid() || 591 !decode_win_sdhci_valid() || !decode_win_cesa_valid()) 592 return (EINVAL); 593 594 decode_win_cpu_setup(); 595 if (MV_DUMP_WIN) 596 soc_dump_decode_win(); 597 598 eth_port = 0; 599 usb_port = 0; 600 if ((err = fdt_win_setup()) != 0) 601 return (err); 602 603 return (0); 604 } 605 606 /************************************************************************** 607 * Decode windows registers accessors 608 **************************************************************************/ 609 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 610 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 611 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 612 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 613 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 614 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 615 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 616 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 617 618 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 619 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 620 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 621 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 622 623 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 624 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 625 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 626 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 627 628 #ifdef SOC_MV_ARMADA38X 629 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 630 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 631 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 632 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 633 #endif 634 635 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 636 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 637 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 638 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 639 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 640 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 641 642 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 643 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 644 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 645 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 646 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 647 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 648 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 649 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 650 651 WIN_REG_BASE_RD(win_eth, bare, 0x290) 652 WIN_REG_BASE_RD(win_eth, epap, 0x294) 653 WIN_REG_BASE_WR(win_eth, bare, 0x290) 654 WIN_REG_BASE_WR(win_eth, epap, 0x294) 655 656 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 657 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 658 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 659 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 660 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 661 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 662 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 663 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 664 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 665 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 666 667 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 668 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 669 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 670 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 671 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 672 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 673 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 674 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 675 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 676 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 677 678 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 679 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 680 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 681 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 682 #if defined(SOC_MV_ARMADA38X) 683 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 684 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 685 #endif 686 687 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 688 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 689 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 690 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 691 692 #ifndef SOC_MV_DOVE 693 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 694 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 695 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 696 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 697 #else 698 /* 699 * On 88F6781 (Dove) SoC DDR Controller is accessed through 700 * single MBUS <-> AXI bridge. In this case we provide emulated 701 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 702 * with common decoding windows setup code. 703 */ 704 705 static inline uint32_t ddr_br_read(int i) 706 { 707 uint32_t mmap; 708 709 /* Read Memory Address Map Register for CS i */ 710 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 711 712 /* Return CS i base address */ 713 return (mmap & 0xFF000000); 714 } 715 716 static inline uint32_t ddr_sz_read(int i) 717 { 718 uint32_t mmap, size; 719 720 /* Read Memory Address Map Register for CS i */ 721 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 722 723 /* Extract size of CS space in 64kB units */ 724 size = (1 << ((mmap >> 16) & 0x0F)); 725 726 /* Return CS size and enable/disable status */ 727 return (((size - 1) << 16) | (mmap & 0x01)); 728 } 729 #endif 730 731 /************************************************************************** 732 * Decode windows helper routines 733 **************************************************************************/ 734 void 735 soc_dump_decode_win(void) 736 { 737 uint32_t dev, rev; 738 int i; 739 740 soc_id(&dev, &rev); 741 742 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 743 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 744 win_cpu_cr_read(i), 745 win_cpu_br_read(i)); 746 747 if (win_cpu_can_remap(i)) 748 printf(", rl 0x%08x, rh 0x%08x", 749 win_cpu_remap_l_read(i), 750 win_cpu_remap_h_read(i)); 751 752 printf("\n"); 753 } 754 printf("Internal regs base: 0x%08x\n", 755 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 756 757 for (i = 0; i < MV_WIN_DDR_MAX; i++) 758 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 759 ddr_br_read(i), ddr_sz_read(i)); 760 } 761 762 /************************************************************************** 763 * CPU windows routines 764 **************************************************************************/ 765 int 766 win_cpu_can_remap(int i) 767 { 768 uint32_t dev, rev; 769 770 soc_id(&dev, &rev); 771 772 /* Depending on the SoC certain windows have remap capability */ 773 if ((dev == MV_DEV_88F5182 && i < 2) || 774 (dev == MV_DEV_88F5281 && i < 4) || 775 (dev == MV_DEV_88F6281 && i < 4) || 776 (dev == MV_DEV_88F6282 && i < 4) || 777 (dev == MV_DEV_88F6828 && i < 20) || 778 (dev == MV_DEV_88F6820 && i < 20) || 779 (dev == MV_DEV_88F6810 && i < 20) || 780 (dev == MV_DEV_88RC8180 && i < 2) || 781 (dev == MV_DEV_88F6781 && i < 4) || 782 (dev == MV_DEV_MV78100_Z0 && i < 8) || 783 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 784 return (1); 785 786 return (0); 787 } 788 789 /* XXX This should check for overlapping remap fields too.. */ 790 int 791 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 792 { 793 const struct decode_win *tab; 794 int i; 795 796 tab = wintab; 797 798 for (i = 0; i < win_no; i++, tab++) { 799 if (i == win) 800 /* Skip self */ 801 continue; 802 803 if ((tab->base + tab->size - 1) < (wintab + win)->base) 804 continue; 805 806 else if (((wintab + win)->base + (wintab + win)->size - 1) < 807 tab->base) 808 continue; 809 else 810 return (i); 811 } 812 813 return (-1); 814 } 815 816 static int 817 decode_win_cpu_valid(void) 818 { 819 int i, j, rv; 820 uint32_t b, e, s; 821 822 if (cpu_wins_no > MV_WIN_CPU_MAX) { 823 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 824 return (0); 825 } 826 827 rv = 1; 828 for (i = 0; i < cpu_wins_no; i++) { 829 830 if (cpu_wins[i].target == 0) { 831 printf("CPU window#%d: DDR target window is not " 832 "supposed to be reprogrammed!\n", i); 833 rv = 0; 834 } 835 836 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 837 printf("CPU window#%d: not capable of remapping, but " 838 "val 0x%08x defined\n", i, cpu_wins[i].remap); 839 rv = 0; 840 } 841 842 s = cpu_wins[i].size; 843 b = cpu_wins[i].base; 844 e = b + s - 1; 845 if (s > (0xFFFFFFFF - b + 1)) { 846 /* 847 * XXX this boundary check should account for 64bit 848 * and remapping.. 849 */ 850 printf("CPU window#%d: no space for size 0x%08x at " 851 "0x%08x\n", i, s, b); 852 rv = 0; 853 continue; 854 } 855 856 if (b != rounddown2(b, s)) { 857 printf("CPU window#%d: address 0x%08x is not aligned " 858 "to 0x%08x\n", i, b, s); 859 rv = 0; 860 continue; 861 } 862 863 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 864 if (j >= 0) { 865 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 866 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 867 cpu_wins[j].base, 868 cpu_wins[j].base + cpu_wins[j].size - 1); 869 rv = 0; 870 } 871 } 872 873 return (rv); 874 } 875 876 int 877 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 878 vm_paddr_t remap) 879 { 880 uint32_t br, cr; 881 int win, i; 882 883 if (remap == ~0) { 884 win = MV_WIN_CPU_MAX - 1; 885 i = -1; 886 } else { 887 win = 0; 888 i = 1; 889 } 890 891 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 892 cr = win_cpu_cr_read(win); 893 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 894 break; 895 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 896 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 897 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 898 (target << MV_WIN_CPU_TARGET_SHIFT))) 899 break; 900 win += i; 901 } 902 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 903 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 904 return (-1); 905 906 br = base & 0xffff0000; 907 win_cpu_br_write(win, br); 908 909 if (win_cpu_can_remap(win)) { 910 if (remap != ~0) { 911 win_cpu_remap_l_write(win, remap & 0xffff0000); 912 win_cpu_remap_h_write(win, 0); 913 } else { 914 /* 915 * Remap function is not used for a given window 916 * (capable of remapping) - set remap field with the 917 * same value as base. 918 */ 919 win_cpu_remap_l_write(win, base & 0xffff0000); 920 win_cpu_remap_h_write(win, 0); 921 } 922 } 923 924 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 925 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 926 win_cpu_cr_write(win, cr); 927 928 return (0); 929 } 930 931 static void 932 decode_win_cpu_setup(void) 933 { 934 int i; 935 936 /* Disable all CPU windows */ 937 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 938 win_cpu_cr_write(i, 0); 939 win_cpu_br_write(i, 0); 940 if (win_cpu_can_remap(i)) { 941 win_cpu_remap_l_write(i, 0); 942 win_cpu_remap_h_write(i, 0); 943 } 944 } 945 946 for (i = 0; i < cpu_wins_no; i++) 947 if (cpu_wins[i].target > 0) 948 decode_win_cpu_set(cpu_wins[i].target, 949 cpu_wins[i].attr, cpu_wins[i].base, 950 cpu_wins[i].size, cpu_wins[i].remap); 951 952 } 953 954 #ifdef SOC_MV_ARMADAXP 955 static int 956 decode_win_sdram_fixup(void) 957 { 958 struct mem_region mr[FDT_MEM_REGIONS]; 959 uint8_t window_valid[MV_WIN_DDR_MAX]; 960 int mr_cnt, err, i, j; 961 uint32_t valid_win_num = 0; 962 963 /* Grab physical memory regions information from device tree. */ 964 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 965 if (err != 0) 966 return (err); 967 968 for (i = 0; i < MV_WIN_DDR_MAX; i++) 969 window_valid[i] = 0; 970 971 /* Try to match entries from device tree with settings from u-boot */ 972 for (i = 0; i < mr_cnt; i++) { 973 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 974 if (ddr_is_active(j) && 975 (ddr_base(j) == mr[i].mr_start) && 976 (ddr_size(j) == mr[i].mr_size)) { 977 window_valid[j] = 1; 978 valid_win_num++; 979 } 980 } 981 } 982 983 if (mr_cnt != valid_win_num) 984 return (EINVAL); 985 986 /* Destroy windows without corresponding device tree entry */ 987 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 988 if (ddr_is_active(j) && (window_valid[j] != 1)) { 989 printf("Disabling SDRAM decoding window: %d\n", j); 990 ddr_disable(j); 991 } 992 } 993 994 return (0); 995 } 996 #endif 997 /* 998 * Check if we're able to cover all active DDR banks. 999 */ 1000 static int 1001 decode_win_can_cover_ddr(int max) 1002 { 1003 int i, c; 1004 1005 c = 0; 1006 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1007 if (ddr_is_active(i)) 1008 c++; 1009 1010 if (c > max) { 1011 printf("Unable to cover all active DDR banks: " 1012 "%d, available windows: %d\n", c, max); 1013 return (0); 1014 } 1015 1016 return (1); 1017 } 1018 1019 /************************************************************************** 1020 * DDR windows routines 1021 **************************************************************************/ 1022 int 1023 ddr_is_active(int i) 1024 { 1025 1026 if (ddr_sz_read(i) & 0x1) 1027 return (1); 1028 1029 return (0); 1030 } 1031 1032 void 1033 ddr_disable(int i) 1034 { 1035 1036 ddr_sz_write(i, 0); 1037 ddr_br_write(i, 0); 1038 } 1039 1040 uint32_t 1041 ddr_base(int i) 1042 { 1043 1044 return (ddr_br_read(i) & 0xff000000); 1045 } 1046 1047 uint32_t 1048 ddr_size(int i) 1049 { 1050 1051 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1052 } 1053 1054 uint32_t 1055 ddr_attr(int i) 1056 { 1057 uint32_t dev, rev; 1058 1059 soc_id(&dev, &rev); 1060 if (dev == MV_DEV_88RC8180) 1061 return ((ddr_sz_read(i) & 0xf0) >> 4); 1062 if (dev == MV_DEV_88F6781) 1063 return (0); 1064 1065 return (i == 0 ? 0xe : 1066 (i == 1 ? 0xd : 1067 (i == 2 ? 0xb : 1068 (i == 3 ? 0x7 : 0xff)))); 1069 } 1070 1071 uint32_t 1072 ddr_target(int i) 1073 { 1074 uint32_t dev, rev; 1075 1076 soc_id(&dev, &rev); 1077 if (dev == MV_DEV_88RC8180) { 1078 i = (ddr_sz_read(i) & 0xf0) >> 4; 1079 return (i == 0xe ? 0xc : 1080 (i == 0xd ? 0xd : 1081 (i == 0xb ? 0xe : 1082 (i == 0x7 ? 0xf : 0xc)))); 1083 } 1084 1085 /* 1086 * On SOCs other than 88RC8180 Mbus unit ID for 1087 * DDR SDRAM controller is always 0x0. 1088 */ 1089 return (0); 1090 } 1091 1092 /************************************************************************** 1093 * CESA windows routines 1094 **************************************************************************/ 1095 static int 1096 decode_win_cesa_valid(void) 1097 { 1098 1099 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1100 } 1101 1102 static void 1103 decode_win_cesa_dump(u_long base) 1104 { 1105 int i; 1106 1107 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1108 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1109 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1110 } 1111 1112 /* 1113 * Set CESA decode windows. 1114 */ 1115 static void 1116 decode_win_cesa_setup(u_long base) 1117 { 1118 uint32_t br, cr; 1119 uint64_t size; 1120 int i, j; 1121 1122 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1123 win_cesa_cr_write(base, i, 0); 1124 win_cesa_br_write(base, i, 0); 1125 } 1126 1127 /* Only access to active DRAM banks is required */ 1128 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1129 if (ddr_is_active(i)) { 1130 br = ddr_base(i); 1131 1132 size = ddr_size(i); 1133 #ifdef SOC_MV_ARMADA38X 1134 /* 1135 * Armada 38x SoC's equipped with 4GB DRAM 1136 * suffer freeze during CESA operation, if 1137 * MBUS window opened at given DRAM CS reaches 1138 * end of the address space. Apply a workaround 1139 * by setting the window size to the closest possible 1140 * value, i.e. divide it by 2. 1141 */ 1142 if (size + ddr_base(i) == 0x100000000ULL) 1143 size /= 2; 1144 #endif 1145 1146 cr = (((size - 1) & 0xffff0000) | 1147 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1148 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1149 IO_WIN_ENA_MASK); 1150 1151 /* Set the first free CESA window */ 1152 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1153 if (win_cesa_cr_read(base, j) & 0x1) 1154 continue; 1155 1156 win_cesa_br_write(base, j, br); 1157 win_cesa_cr_write(base, j, cr); 1158 break; 1159 } 1160 } 1161 } 1162 } 1163 1164 /************************************************************************** 1165 * USB windows routines 1166 **************************************************************************/ 1167 static int 1168 decode_win_usb_valid(void) 1169 { 1170 1171 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1172 } 1173 1174 static void 1175 decode_win_usb_dump(u_long base) 1176 { 1177 int i; 1178 1179 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1180 return; 1181 1182 for (i = 0; i < MV_WIN_USB_MAX; i++) 1183 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1184 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1185 } 1186 1187 /* 1188 * Set USB decode windows. 1189 */ 1190 static void 1191 decode_win_usb_setup(u_long base) 1192 { 1193 uint32_t br, cr; 1194 int i, j; 1195 1196 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1197 return; 1198 1199 usb_port++; 1200 1201 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1202 win_usb_cr_write(base, i, 0); 1203 win_usb_br_write(base, i, 0); 1204 } 1205 1206 /* Only access to active DRAM banks is required */ 1207 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1208 if (ddr_is_active(i)) { 1209 br = ddr_base(i); 1210 /* 1211 * XXX for 6281 we should handle Mbus write 1212 * burst limit field in the ctrl reg 1213 */ 1214 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1215 (ddr_attr(i) << 8) | 1216 (ddr_target(i) << 4) | 1); 1217 1218 /* Set the first free USB window */ 1219 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1220 if (win_usb_cr_read(base, j) & 0x1) 1221 continue; 1222 1223 win_usb_br_write(base, j, br); 1224 win_usb_cr_write(base, j, cr); 1225 break; 1226 } 1227 } 1228 } 1229 } 1230 1231 /************************************************************************** 1232 * USB3 windows routines 1233 **************************************************************************/ 1234 #ifdef SOC_MV_ARMADA38X 1235 static int 1236 decode_win_usb3_valid(void) 1237 { 1238 1239 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1240 } 1241 1242 static void 1243 decode_win_usb3_dump(u_long base) 1244 { 1245 int i; 1246 1247 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1248 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1249 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1250 } 1251 1252 /* 1253 * Set USB3 decode windows 1254 */ 1255 static void 1256 decode_win_usb3_setup(u_long base) 1257 { 1258 uint32_t br, cr; 1259 int i, j; 1260 1261 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1262 win_usb3_cr_write(base, i, 0); 1263 win_usb3_br_write(base, i, 0); 1264 } 1265 1266 /* Only access to active DRAM banks is required */ 1267 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1268 if (ddr_is_active(i)) { 1269 br = ddr_base(i); 1270 cr = (((ddr_size(i) - 1) & 1271 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1272 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1273 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1274 IO_WIN_ENA_MASK); 1275 1276 /* Set the first free USB3.0 window */ 1277 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1278 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1279 continue; 1280 1281 win_usb3_br_write(base, j, br); 1282 win_usb3_cr_write(base, j, cr); 1283 break; 1284 } 1285 } 1286 } 1287 } 1288 #else 1289 /* 1290 * Provide dummy functions to satisfy the build 1291 * for SoCs not equipped with USB3 1292 */ 1293 static int 1294 decode_win_usb3_valid(void) 1295 { 1296 1297 return (1); 1298 } 1299 1300 static void 1301 decode_win_usb3_setup(u_long base) 1302 { 1303 } 1304 1305 static void 1306 decode_win_usb3_dump(u_long base) 1307 { 1308 } 1309 #endif 1310 /************************************************************************** 1311 * ETH windows routines 1312 **************************************************************************/ 1313 1314 static int 1315 win_eth_can_remap(int i) 1316 { 1317 1318 /* ETH encode windows 0-3 have remap capability */ 1319 if (i < 4) 1320 return (1); 1321 1322 return (0); 1323 } 1324 1325 static int 1326 eth_bare_read(uint32_t base, int i) 1327 { 1328 uint32_t v; 1329 1330 v = win_eth_bare_read(base); 1331 v &= (1 << i); 1332 1333 return (v >> i); 1334 } 1335 1336 static void 1337 eth_bare_write(uint32_t base, int i, int val) 1338 { 1339 uint32_t v; 1340 1341 v = win_eth_bare_read(base); 1342 v &= ~(1 << i); 1343 v |= (val << i); 1344 win_eth_bare_write(base, v); 1345 } 1346 1347 static void 1348 eth_epap_write(uint32_t base, int i, int val) 1349 { 1350 uint32_t v; 1351 1352 v = win_eth_epap_read(base); 1353 v &= ~(0x3 << (i * 2)); 1354 v |= (val << (i * 2)); 1355 win_eth_epap_write(base, v); 1356 } 1357 1358 static void 1359 decode_win_eth_dump(u_long base) 1360 { 1361 int i; 1362 1363 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1364 return; 1365 1366 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1367 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1368 win_eth_br_read(base, i), 1369 win_eth_sz_read(base, i)); 1370 1371 if (win_eth_can_remap(i)) 1372 printf(", ha 0x%08x", 1373 win_eth_har_read(base, i)); 1374 1375 printf("\n"); 1376 } 1377 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1378 win_eth_bare_read(base), 1379 win_eth_epap_read(base)); 1380 } 1381 1382 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1383 1384 static void 1385 decode_win_eth_setup(u_long base) 1386 { 1387 uint32_t br, sz; 1388 int i, j; 1389 1390 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1391 return; 1392 1393 eth_port++; 1394 1395 /* Disable, clear and revoke protection for all ETH windows */ 1396 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1397 1398 eth_bare_write(base, i, 1); 1399 eth_epap_write(base, i, 0); 1400 win_eth_br_write(base, i, 0); 1401 win_eth_sz_write(base, i, 0); 1402 if (win_eth_can_remap(i)) 1403 win_eth_har_write(base, i, 0); 1404 } 1405 1406 /* Only access to active DRAM banks is required */ 1407 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1408 if (ddr_is_active(i)) { 1409 1410 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1411 sz = ((ddr_size(i) - 1) & 0xffff0000); 1412 1413 /* Set the first free ETH window */ 1414 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1415 if (eth_bare_read(base, j) == 0) 1416 continue; 1417 1418 win_eth_br_write(base, j, br); 1419 win_eth_sz_write(base, j, sz); 1420 1421 /* XXX remapping ETH windows not supported */ 1422 1423 /* Set protection RW */ 1424 eth_epap_write(base, j, 0x3); 1425 1426 /* Enable window */ 1427 eth_bare_write(base, j, 0); 1428 break; 1429 } 1430 } 1431 } 1432 1433 static int 1434 decode_win_eth_valid(void) 1435 { 1436 1437 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1438 } 1439 1440 /************************************************************************** 1441 * PCIE windows routines 1442 **************************************************************************/ 1443 1444 void 1445 decode_win_pcie_setup(u_long base) 1446 { 1447 uint32_t size = 0, ddrbase = ~0; 1448 uint32_t cr, br; 1449 int i, j; 1450 1451 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1452 pcie_bar_br_write(base, i, 1453 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1454 if (i < 3) 1455 pcie_bar_brh_write(base, i, 0); 1456 if (i > 0) 1457 pcie_bar_cr_write(base, i, 0); 1458 } 1459 1460 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1461 win_pcie_cr_write(base, i, 0); 1462 win_pcie_br_write(base, i, 0); 1463 win_pcie_remap_write(base, i, 0); 1464 } 1465 1466 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1467 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1468 & MV_PCIE_ROOT_CMPLX) == 0) { 1469 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1470 return; 1471 } 1472 1473 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1474 if (ddr_is_active(i)) { 1475 /* Map DDR to BAR 1 */ 1476 cr = (ddr_size(i) - 1) & 0xffff0000; 1477 size += ddr_size(i) & 0xffff0000; 1478 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1479 br = ddr_base(i); 1480 if (br < ddrbase) 1481 ddrbase = br; 1482 1483 /* Use the first available PCIE window */ 1484 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1485 if (win_pcie_cr_read(base, j) != 0) 1486 continue; 1487 1488 win_pcie_br_write(base, j, br); 1489 win_pcie_cr_write(base, j, cr); 1490 break; 1491 } 1492 } 1493 } 1494 1495 /* 1496 * Upper 16 bits in BAR register is interpreted as BAR size 1497 * (in 64 kB units) plus 64kB, so subtract 0x10000 1498 * form value passed to register to get correct value. 1499 */ 1500 size -= 0x10000; 1501 pcie_bar_cr_write(base, 1, size | 1); 1502 pcie_bar_br_write(base, 1, ddrbase | 1503 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1504 pcie_bar_br_write(base, 0, fdt_immr_pa | 1505 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1506 } 1507 1508 static int 1509 decode_win_pcie_valid(void) 1510 { 1511 1512 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1513 } 1514 1515 /************************************************************************** 1516 * IDMA windows routines 1517 **************************************************************************/ 1518 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1519 static int 1520 idma_bare_read(u_long base, int i) 1521 { 1522 uint32_t v; 1523 1524 v = win_idma_bare_read(base); 1525 v &= (1 << i); 1526 1527 return (v >> i); 1528 } 1529 1530 static void 1531 idma_bare_write(u_long base, int i, int val) 1532 { 1533 uint32_t v; 1534 1535 v = win_idma_bare_read(base); 1536 v &= ~(1 << i); 1537 v |= (val << i); 1538 win_idma_bare_write(base, v); 1539 } 1540 1541 /* 1542 * Sets channel protection 'val' for window 'w' on channel 'c' 1543 */ 1544 static void 1545 idma_cap_write(u_long base, int c, int w, int val) 1546 { 1547 uint32_t v; 1548 1549 v = win_idma_cap_read(base, c); 1550 v &= ~(0x3 << (w * 2)); 1551 v |= (val << (w * 2)); 1552 win_idma_cap_write(base, c, v); 1553 } 1554 1555 /* 1556 * Set protection 'val' on all channels for window 'w' 1557 */ 1558 static void 1559 idma_set_prot(u_long base, int w, int val) 1560 { 1561 int c; 1562 1563 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1564 idma_cap_write(base, c, w, val); 1565 } 1566 1567 static int 1568 win_idma_can_remap(int i) 1569 { 1570 1571 /* IDMA decode windows 0-3 have remap capability */ 1572 if (i < 4) 1573 return (1); 1574 1575 return (0); 1576 } 1577 1578 void 1579 decode_win_idma_setup(u_long base) 1580 { 1581 uint32_t br, sz; 1582 int i, j; 1583 1584 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1585 return; 1586 /* 1587 * Disable and clear all IDMA windows, revoke protection for all channels 1588 */ 1589 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1590 1591 idma_bare_write(base, i, 1); 1592 win_idma_br_write(base, i, 0); 1593 win_idma_sz_write(base, i, 0); 1594 if (win_idma_can_remap(i) == 1) 1595 win_idma_har_write(base, i, 0); 1596 } 1597 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1598 win_idma_cap_write(base, i, 0); 1599 1600 /* 1601 * Set up access to all active DRAM banks 1602 */ 1603 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1604 if (ddr_is_active(i)) { 1605 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1606 sz = ((ddr_size(i) - 1) & 0xffff0000); 1607 1608 /* Place DDR entries in non-remapped windows */ 1609 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1610 if (win_idma_can_remap(j) != 1 && 1611 idma_bare_read(base, j) == 1) { 1612 1613 /* Configure window */ 1614 win_idma_br_write(base, j, br); 1615 win_idma_sz_write(base, j, sz); 1616 1617 /* Set protection RW on all channels */ 1618 idma_set_prot(base, j, 0x3); 1619 1620 /* Enable window */ 1621 idma_bare_write(base, j, 0); 1622 break; 1623 } 1624 } 1625 1626 /* 1627 * Remaining targets -- from statically defined table 1628 */ 1629 for (i = 0; i < idma_wins_no; i++) 1630 if (idma_wins[i].target > 0) { 1631 br = (idma_wins[i].base & 0xffff0000) | 1632 (idma_wins[i].attr << 8) | idma_wins[i].target; 1633 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1634 1635 /* Set the first free IDMA window */ 1636 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1637 if (idma_bare_read(base, j) == 0) 1638 continue; 1639 1640 /* Configure window */ 1641 win_idma_br_write(base, j, br); 1642 win_idma_sz_write(base, j, sz); 1643 if (win_idma_can_remap(j) && 1644 idma_wins[j].remap >= 0) 1645 win_idma_har_write(base, j, 1646 idma_wins[j].remap); 1647 1648 /* Set protection RW on all channels */ 1649 idma_set_prot(base, j, 0x3); 1650 1651 /* Enable window */ 1652 idma_bare_write(base, j, 0); 1653 break; 1654 } 1655 } 1656 } 1657 1658 int 1659 decode_win_idma_valid(void) 1660 { 1661 const struct decode_win *wintab; 1662 int c, i, j, rv; 1663 uint32_t b, e, s; 1664 1665 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1666 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1667 return (0); 1668 } 1669 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1670 if (ddr_is_active(i)) 1671 c++; 1672 1673 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1674 printf("IDMA windows: too many entries: %d, available: %d\n", 1675 idma_wins_no, MV_WIN_IDMA_MAX - c); 1676 return (0); 1677 } 1678 1679 wintab = idma_wins; 1680 rv = 1; 1681 for (i = 0; i < idma_wins_no; i++, wintab++) { 1682 1683 if (wintab->target == 0) { 1684 printf("IDMA window#%d: DDR target window is not " 1685 "supposed to be reprogrammed!\n", i); 1686 rv = 0; 1687 } 1688 1689 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1690 printf("IDMA window#%d: not capable of remapping, but " 1691 "val 0x%08x defined\n", i, wintab->remap); 1692 rv = 0; 1693 } 1694 1695 s = wintab->size; 1696 b = wintab->base; 1697 e = b + s - 1; 1698 if (s > (0xFFFFFFFF - b + 1)) { 1699 /* XXX this boundary check should account for 64bit and 1700 * remapping.. */ 1701 printf("IDMA window#%d: no space for size 0x%08x at " 1702 "0x%08x\n", i, s, b); 1703 rv = 0; 1704 continue; 1705 } 1706 1707 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1708 if (j >= 0) { 1709 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1710 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1711 idma_wins[j].base, 1712 idma_wins[j].base + idma_wins[j].size - 1); 1713 rv = 0; 1714 } 1715 } 1716 1717 return (rv); 1718 } 1719 1720 void 1721 decode_win_idma_dump(u_long base) 1722 { 1723 int i; 1724 1725 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1726 return; 1727 1728 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1729 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1730 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1731 1732 if (win_idma_can_remap(i)) 1733 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1734 1735 printf("\n"); 1736 } 1737 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1738 printf("IDMA channel#%d: ap 0x%08x\n", i, 1739 win_idma_cap_read(base, i)); 1740 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1741 } 1742 #else 1743 1744 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1745 int 1746 decode_win_idma_valid(void) 1747 { 1748 1749 return (1); 1750 } 1751 1752 void 1753 decode_win_idma_setup(u_long base) 1754 { 1755 } 1756 1757 void 1758 decode_win_idma_dump(u_long base) 1759 { 1760 } 1761 #endif 1762 1763 /************************************************************************** 1764 * XOR windows routines 1765 **************************************************************************/ 1766 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1767 static int 1768 xor_ctrl_read(u_long base, int i, int c, int e) 1769 { 1770 uint32_t v; 1771 v = win_xor_ctrl_read(base, c, e); 1772 v &= (1 << i); 1773 1774 return (v >> i); 1775 } 1776 1777 static void 1778 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1779 { 1780 uint32_t v; 1781 1782 v = win_xor_ctrl_read(base, c, e); 1783 v &= ~(1 << i); 1784 v |= (val << i); 1785 win_xor_ctrl_write(base, c, e, v); 1786 } 1787 1788 /* 1789 * Set channel protection 'val' for window 'w' on channel 'c' 1790 */ 1791 static void 1792 xor_chan_write(u_long base, int c, int e, int w, int val) 1793 { 1794 uint32_t v; 1795 1796 v = win_xor_ctrl_read(base, c, e); 1797 v &= ~(0x3 << (w * 2 + 16)); 1798 v |= (val << (w * 2 + 16)); 1799 win_xor_ctrl_write(base, c, e, v); 1800 } 1801 1802 /* 1803 * Set protection 'val' on all channels for window 'w' on engine 'e' 1804 */ 1805 static void 1806 xor_set_prot(u_long base, int w, int e, int val) 1807 { 1808 int c; 1809 1810 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1811 xor_chan_write(base, c, e, w, val); 1812 } 1813 1814 static int 1815 win_xor_can_remap(int i) 1816 { 1817 1818 /* XOR decode windows 0-3 have remap capability */ 1819 if (i < 4) 1820 return (1); 1821 1822 return (0); 1823 } 1824 1825 static int 1826 xor_max_eng(void) 1827 { 1828 uint32_t dev, rev; 1829 1830 soc_id(&dev, &rev); 1831 switch (dev) { 1832 case MV_DEV_88F6281: 1833 case MV_DEV_88F6282: 1834 case MV_DEV_MV78130: 1835 case MV_DEV_MV78160: 1836 case MV_DEV_MV78230: 1837 case MV_DEV_MV78260: 1838 case MV_DEV_MV78460: 1839 return (2); 1840 case MV_DEV_MV78100: 1841 case MV_DEV_MV78100_Z0: 1842 return (1); 1843 default: 1844 return (0); 1845 } 1846 } 1847 1848 static void 1849 xor_active_dram(u_long base, int c, int e, int *window) 1850 { 1851 uint32_t br, sz; 1852 int i, m, w; 1853 1854 /* 1855 * Set up access to all active DRAM banks 1856 */ 1857 m = xor_max_eng(); 1858 for (i = 0; i < m; i++) 1859 if (ddr_is_active(i)) { 1860 br = ddr_base(i) | (ddr_attr(i) << 8) | 1861 ddr_target(i); 1862 sz = ((ddr_size(i) - 1) & 0xffff0000); 1863 1864 /* Place DDR entries in non-remapped windows */ 1865 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1866 if (win_xor_can_remap(w) != 1 && 1867 (xor_ctrl_read(base, w, c, e) == 0) && 1868 w > *window) { 1869 /* Configure window */ 1870 win_xor_br_write(base, w, e, br); 1871 win_xor_sz_write(base, w, e, sz); 1872 1873 /* Set protection RW on all channels */ 1874 xor_set_prot(base, w, e, 0x3); 1875 1876 /* Enable window */ 1877 xor_ctrl_write(base, w, c, e, 1); 1878 (*window)++; 1879 break; 1880 } 1881 } 1882 } 1883 1884 void 1885 decode_win_xor_setup(u_long base) 1886 { 1887 uint32_t br, sz; 1888 int i, j, z, e = 1, m, window; 1889 1890 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1891 return; 1892 1893 /* 1894 * Disable and clear all XOR windows, revoke protection for all 1895 * channels 1896 */ 1897 m = xor_max_eng(); 1898 for (j = 0; j < m; j++, e--) { 1899 1900 /* Number of non-remaped windows */ 1901 window = MV_XOR_NON_REMAP - 1; 1902 1903 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1904 win_xor_br_write(base, i, e, 0); 1905 win_xor_sz_write(base, i, e, 0); 1906 } 1907 1908 if (win_xor_can_remap(i) == 1) 1909 win_xor_har_write(base, i, e, 0); 1910 1911 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1912 win_xor_ctrl_write(base, i, e, 0); 1913 xor_active_dram(base, i, e, &window); 1914 } 1915 1916 /* 1917 * Remaining targets -- from a statically defined table 1918 */ 1919 for (i = 0; i < xor_wins_no; i++) 1920 if (xor_wins[i].target > 0) { 1921 br = (xor_wins[i].base & 0xffff0000) | 1922 (xor_wins[i].attr << 8) | 1923 xor_wins[i].target; 1924 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1925 1926 /* Set the first free XOR window */ 1927 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1928 if (xor_ctrl_read(base, z, 0, e) && 1929 xor_ctrl_read(base, z, 1, e)) 1930 continue; 1931 1932 /* Configure window */ 1933 win_xor_br_write(base, z, e, br); 1934 win_xor_sz_write(base, z, e, sz); 1935 if (win_xor_can_remap(z) && 1936 xor_wins[z].remap >= 0) 1937 win_xor_har_write(base, z, e, 1938 xor_wins[z].remap); 1939 1940 /* Set protection RW on all channels */ 1941 xor_set_prot(base, z, e, 0x3); 1942 1943 /* Enable window */ 1944 xor_ctrl_write(base, z, 0, e, 1); 1945 xor_ctrl_write(base, z, 1, e, 1); 1946 break; 1947 } 1948 } 1949 } 1950 } 1951 1952 int 1953 decode_win_xor_valid(void) 1954 { 1955 const struct decode_win *wintab; 1956 int c, i, j, rv; 1957 uint32_t b, e, s; 1958 1959 if (xor_wins_no > MV_WIN_XOR_MAX) { 1960 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1961 return (0); 1962 } 1963 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1964 if (ddr_is_active(i)) 1965 c++; 1966 1967 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1968 printf("XOR windows: too many entries: %d, available: %d\n", 1969 xor_wins_no, MV_WIN_IDMA_MAX - c); 1970 return (0); 1971 } 1972 1973 wintab = xor_wins; 1974 rv = 1; 1975 for (i = 0; i < xor_wins_no; i++, wintab++) { 1976 1977 if (wintab->target == 0) { 1978 printf("XOR window#%d: DDR target window is not " 1979 "supposed to be reprogrammed!\n", i); 1980 rv = 0; 1981 } 1982 1983 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1984 printf("XOR window#%d: not capable of remapping, but " 1985 "val 0x%08x defined\n", i, wintab->remap); 1986 rv = 0; 1987 } 1988 1989 s = wintab->size; 1990 b = wintab->base; 1991 e = b + s - 1; 1992 if (s > (0xFFFFFFFF - b + 1)) { 1993 /* 1994 * XXX this boundary check should account for 64bit 1995 * and remapping.. 1996 */ 1997 printf("XOR window#%d: no space for size 0x%08x at " 1998 "0x%08x\n", i, s, b); 1999 rv = 0; 2000 continue; 2001 } 2002 2003 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 2004 if (j >= 0) { 2005 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 2006 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2007 xor_wins[j].base, 2008 xor_wins[j].base + xor_wins[j].size - 1); 2009 rv = 0; 2010 } 2011 } 2012 2013 return (rv); 2014 } 2015 2016 void 2017 decode_win_xor_dump(u_long base) 2018 { 2019 int i, j; 2020 int e = 1; 2021 2022 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2023 return; 2024 2025 for (j = 0; j < xor_max_eng(); j++, e--) { 2026 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2027 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2028 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2029 2030 if (win_xor_can_remap(i)) 2031 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2032 2033 printf("\n"); 2034 } 2035 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2036 printf("XOR control#%d: 0x%08x\n", i, 2037 win_xor_ctrl_read(base, i, e)); 2038 } 2039 } 2040 2041 #else 2042 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2043 static int 2044 decode_win_xor_valid(void) 2045 { 2046 2047 return (1); 2048 } 2049 2050 static void 2051 decode_win_xor_setup(u_long base) 2052 { 2053 } 2054 2055 static void 2056 decode_win_xor_dump(u_long base) 2057 { 2058 } 2059 #endif 2060 2061 /************************************************************************** 2062 * SATA windows routines 2063 **************************************************************************/ 2064 static void 2065 decode_win_sata_setup(u_long base) 2066 { 2067 uint32_t cr, br; 2068 int i, j; 2069 2070 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2071 return; 2072 2073 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2074 win_sata_cr_write(base, i, 0); 2075 win_sata_br_write(base, i, 0); 2076 } 2077 2078 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2079 if (ddr_is_active(i)) { 2080 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2081 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2082 br = ddr_base(i); 2083 2084 /* Use the first available SATA window */ 2085 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2086 if ((win_sata_cr_read(base, j) & 1) != 0) 2087 continue; 2088 2089 win_sata_br_write(base, j, br); 2090 win_sata_cr_write(base, j, cr); 2091 break; 2092 } 2093 } 2094 } 2095 2096 #ifdef SOC_MV_ARMADA38X 2097 /* 2098 * Configure AHCI decoding windows 2099 */ 2100 static void 2101 decode_win_ahci_setup(u_long base) 2102 { 2103 uint32_t br, cr, sz; 2104 int i, j; 2105 2106 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2107 win_sata_cr_write(base, i, 0); 2108 win_sata_br_write(base, i, 0); 2109 win_sata_sz_write(base, i, 0); 2110 } 2111 2112 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2113 if (ddr_is_active(i)) { 2114 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2115 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2116 IO_WIN_ENA_MASK; 2117 br = ddr_base(i); 2118 sz = (ddr_size(i) - 1) & 2119 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2120 2121 /* Use first available SATA window */ 2122 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2123 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2124 continue; 2125 2126 /* BASE is set to DRAM base (0x00000000) */ 2127 win_sata_br_write(base, j, br); 2128 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2129 win_sata_cr_write(base, j, cr); 2130 /* SIZE is set to 16MB - max value */ 2131 win_sata_sz_write(base, j, sz); 2132 break; 2133 } 2134 } 2135 } 2136 } 2137 2138 static void 2139 decode_win_ahci_dump(u_long base) 2140 { 2141 int i; 2142 2143 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2144 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2145 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2146 win_sata_sz_read(base,i)); 2147 } 2148 2149 #else 2150 /* 2151 * Provide dummy functions to satisfy the build 2152 * for SoC's not equipped with AHCI controller 2153 */ 2154 static void 2155 decode_win_ahci_setup(u_long base) 2156 { 2157 } 2158 2159 static void 2160 decode_win_ahci_dump(u_long base) 2161 { 2162 } 2163 #endif 2164 2165 static int 2166 decode_win_sata_valid(void) 2167 { 2168 uint32_t dev, rev; 2169 2170 soc_id(&dev, &rev); 2171 if (dev == MV_DEV_88F5281) 2172 return (1); 2173 2174 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2175 } 2176 2177 static void 2178 decode_win_sdhci_setup(u_long base) 2179 { 2180 uint32_t cr, br; 2181 int i, j; 2182 2183 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2184 win_sdhci_cr_write(base, i, 0); 2185 win_sdhci_br_write(base, i, 0); 2186 } 2187 2188 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2189 if (ddr_is_active(i)) { 2190 br = ddr_base(i); 2191 cr = (((ddr_size(i) - 1) & 2192 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2193 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2194 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2195 IO_WIN_ENA_MASK); 2196 2197 /* Use the first available SDHCI window */ 2198 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2199 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2200 continue; 2201 2202 win_sdhci_cr_write(base, j, cr); 2203 win_sdhci_br_write(base, j, br); 2204 break; 2205 } 2206 } 2207 } 2208 2209 static void 2210 decode_win_sdhci_dump(u_long base) 2211 { 2212 int i; 2213 2214 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2215 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2216 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2217 } 2218 2219 static int 2220 decode_win_sdhci_valid(void) 2221 { 2222 2223 #ifdef SOC_MV_ARMADA38X 2224 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2225 #endif 2226 2227 /* Satisfy platforms not equipped with this controller. */ 2228 return (1); 2229 } 2230 2231 /************************************************************************** 2232 * FDT parsing routines. 2233 **************************************************************************/ 2234 2235 static int 2236 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2237 int *tuplesize) 2238 { 2239 phandle_t node; 2240 pcell_t addr_cells, par_addr_cells, size_cells; 2241 int len, tuple_size, tuples_count; 2242 2243 node = OF_finddevice(nodename); 2244 if (node == -1) 2245 return (EINVAL); 2246 2247 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2248 return (ENXIO); 2249 2250 par_addr_cells = fdt_parent_addr_cells(node); 2251 if (par_addr_cells > 2) 2252 return (ERANGE); 2253 2254 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2255 size_cells); 2256 2257 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2258 len = OF_getprop(node, "ranges", buf, size); 2259 2260 /* 2261 * XXX this does not handle the empty 'ranges;' case, which is 2262 * legitimate and should be allowed. 2263 */ 2264 tuples_count = len / tuple_size; 2265 if (tuples_count <= 0) 2266 return (ERANGE); 2267 2268 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2269 return (ERANGE); 2270 2271 *tuples = tuples_count; 2272 *tuplesize = tuple_size; 2273 return (0); 2274 } 2275 2276 static int 2277 win_cpu_from_dt(void) 2278 { 2279 pcell_t ranges[48]; 2280 phandle_t node; 2281 int i, entry_size, err, t, tuple_size, tuples; 2282 u_long sram_base, sram_size; 2283 2284 t = 0; 2285 /* Retrieve 'ranges' property of '/localbus' node. */ 2286 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2287 &tuples, &tuple_size)) == 0) { 2288 /* 2289 * Fill CPU decode windows table. 2290 */ 2291 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2292 2293 entry_size = tuple_size / sizeof(pcell_t); 2294 cpu_wins_no = tuples; 2295 2296 /* Check range */ 2297 if (tuples > nitems(cpu_win_tbl)) { 2298 debugf("too many tuples to fit into cpu_win_tbl\n"); 2299 return (ENOMEM); 2300 } 2301 2302 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2303 cpu_win_tbl[t].target = 1; 2304 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2305 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2306 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2307 cpu_win_tbl[t].remap = ~0; 2308 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2309 "size = 0x%0x remap = 0x%0x\n", 2310 cpu_win_tbl[t].target, 2311 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2312 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2313 } 2314 } 2315 2316 /* 2317 * Retrieve CESA SRAM data. 2318 */ 2319 if ((node = OF_finddevice("sram")) != -1) 2320 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2321 goto moveon; 2322 2323 if ((node = OF_finddevice("/")) == 0) 2324 return (ENXIO); 2325 2326 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2327 /* SRAM block is not always present. */ 2328 return (0); 2329 moveon: 2330 sram_base = sram_size = 0; 2331 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2332 return (EINVAL); 2333 2334 /* Check range */ 2335 if (t >= nitems(cpu_win_tbl)) { 2336 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2337 return (ENOMEM); 2338 } 2339 2340 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2341 #ifdef SOC_MV_ARMADA38X 2342 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2343 #else 2344 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2345 #endif 2346 cpu_win_tbl[t].base = sram_base; 2347 cpu_win_tbl[t].size = sram_size; 2348 cpu_win_tbl[t].remap = ~0; 2349 cpu_wins_no++; 2350 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2351 2352 /* Check if there is a second CESA node */ 2353 while ((node = OF_peer(node)) != 0) { 2354 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2355 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2356 return (EINVAL); 2357 break; 2358 } 2359 } 2360 2361 if (node == 0) 2362 return (0); 2363 2364 t++; 2365 if (t >= nitems(cpu_win_tbl)) { 2366 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2367 return (ENOMEM); 2368 } 2369 2370 /* Configure window for CESA1 */ 2371 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2372 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2373 cpu_win_tbl[t].base = sram_base; 2374 cpu_win_tbl[t].size = sram_size; 2375 cpu_win_tbl[t].remap = ~0; 2376 cpu_wins_no++; 2377 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2378 2379 return (0); 2380 } 2381 2382 static int 2383 fdt_win_setup(void) 2384 { 2385 phandle_t node, child, sb; 2386 struct soc_node_spec *soc_node; 2387 u_long size, base; 2388 int err, i; 2389 2390 sb = 0; 2391 node = OF_finddevice("/"); 2392 if (node == -1) 2393 panic("fdt_win_setup: no root node"); 2394 2395 /* 2396 * Traverse through all children of root and simple-bus nodes. 2397 * For each found device retrieve decode windows data (if applicable). 2398 */ 2399 child = OF_child(node); 2400 while (child != 0) { 2401 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2402 2403 soc_node = &soc_nodes[i]; 2404 2405 /* Setup only for enabled devices */ 2406 if (ofw_bus_node_status_okay(child) == 0) 2407 continue; 2408 2409 if (!ofw_bus_node_is_compatible(child,soc_node->compat)) 2410 continue; 2411 2412 err = fdt_regsize(child, &base, &size); 2413 if (err != 0) 2414 return (err); 2415 2416 base = (base & 0x000fffff) | fdt_immr_va; 2417 if (soc_node->decode_handler != NULL) 2418 soc_node->decode_handler(base); 2419 else 2420 return (ENXIO); 2421 2422 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2423 soc_node->dump_handler(base); 2424 } 2425 2426 /* 2427 * Once done with root-level children let's move down to 2428 * simple-bus and its children. 2429 */ 2430 child = OF_peer(child); 2431 if ((child == 0) && (node == OF_finddevice("/"))) { 2432 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2433 if (node == 0) 2434 return (ENXIO); 2435 child = OF_child(node); 2436 } 2437 /* 2438 * Next, move one more level down to internal-regs node (if 2439 * it is present) and its children. This node also have 2440 * "simple-bus" compatible. 2441 */ 2442 if ((child == 0) && (node == sb)) { 2443 node = fdt_find_compatible(node, "simple-bus", 0); 2444 if (node == 0) 2445 return (0); 2446 child = OF_child(node); 2447 } 2448 } 2449 2450 return (0); 2451 } 2452 2453 static void 2454 fdt_fixup_busfreq(phandle_t root) 2455 { 2456 phandle_t sb; 2457 pcell_t freq; 2458 2459 freq = cpu_to_fdt32(get_tclk()); 2460 2461 /* 2462 * Fix bus speed in cpu node 2463 */ 2464 if ((sb = OF_finddevice("cpu")) != 0) 2465 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2466 OF_setprop(sb, "bus-frequency", (void *)&freq, 2467 sizeof(freq)); 2468 2469 /* 2470 * This fixup sets the simple-bus bus-frequency property. 2471 */ 2472 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2473 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2474 } 2475 2476 static void 2477 fdt_fixup_ranges(phandle_t root) 2478 { 2479 phandle_t node; 2480 pcell_t par_addr_cells, addr_cells, size_cells; 2481 pcell_t ranges[3], reg[2], *rangesptr; 2482 int len, tuple_size, tuples_count; 2483 uint32_t base; 2484 2485 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2486 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2487 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2488 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2489 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2490 addr_cells + size_cells); 2491 len = OF_getprop(node, "ranges", ranges, 2492 sizeof(ranges)); 2493 tuples_count = len / tuple_size; 2494 /* Unexpected settings are not supported */ 2495 if (tuples_count != 1) 2496 goto fixup_failed; 2497 2498 rangesptr = &ranges[0]; 2499 rangesptr += par_addr_cells; 2500 base = fdt_data_get((void *)rangesptr, addr_cells); 2501 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2502 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2503 sizeof(ranges)) < 0) 2504 goto fixup_failed; 2505 } 2506 } 2507 2508 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2509 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2510 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2511 &size_cells) == 0) { 2512 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2513 size_cells); 2514 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2515 tuples_count = len / tuple_size; 2516 /* Unexpected settings are not supported */ 2517 if (tuples_count != 1) 2518 goto fixup_failed; 2519 2520 base = fdt_data_get((void *)®[0], par_addr_cells); 2521 base &= ~0xFF000000; 2522 base |= fdt_immr_pa; 2523 reg[0] = cpu_to_fdt32(base); 2524 if (OF_setprop(node, "reg", (void *)®[0], 2525 sizeof(reg)) < 0) 2526 goto fixup_failed; 2527 } 2528 } 2529 /* Fix-up succeeded. May return and continue */ 2530 return; 2531 2532 fixup_failed: 2533 while (1) { 2534 /* 2535 * In case of any error while fixing ranges just hang. 2536 * 1. No message can be displayed yet since console 2537 * is not initialized. 2538 * 2. Going further will cause failure on bus_space_map() 2539 * relying on the wrong ranges or data abort when 2540 * accessing PCIe registers. 2541 */ 2542 } 2543 } 2544 2545 struct fdt_fixup_entry fdt_fixup_table[] = { 2546 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2547 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2548 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2549 { NULL, NULL } 2550 }; 2551 2552 #ifndef INTRNG 2553 static int 2554 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2555 int *pol) 2556 { 2557 2558 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2559 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2560 return (ENXIO); 2561 2562 *interrupt = fdt32_to_cpu(intr[0]); 2563 *trig = INTR_TRIGGER_CONFORM; 2564 *pol = INTR_POLARITY_CONFORM; 2565 2566 return (0); 2567 } 2568 2569 fdt_pic_decode_t fdt_pic_table[] = { 2570 #ifdef SOC_MV_ARMADA38X 2571 &gic_decode_fdt, 2572 #endif 2573 &fdt_pic_decode_ic, 2574 NULL 2575 }; 2576 #endif 2577 2578 uint64_t 2579 get_sar_value(void) 2580 { 2581 uint32_t sar_low, sar_high; 2582 2583 #if defined(SOC_MV_ARMADAXP) 2584 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2585 SAMPLE_AT_RESET_HI); 2586 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2587 SAMPLE_AT_RESET_LO); 2588 #elif defined(SOC_MV_ARMADA38X) 2589 sar_high = 0; 2590 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2591 SAMPLE_AT_RESET); 2592 #else 2593 /* 2594 * TODO: Add getting proper values for other SoC configurations 2595 */ 2596 sar_high = 0; 2597 sar_low = 0; 2598 #endif 2599 2600 return (((uint64_t)sar_high << 32) | sar_low); 2601 } 2602