1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cesa_valid(void); 80 static int decode_win_cpu_valid(void); 81 static int decode_win_usb_valid(void); 82 static int decode_win_usb3_valid(void); 83 static int decode_win_eth_valid(void); 84 static int decode_win_pcie_valid(void); 85 static int decode_win_sata_valid(void); 86 static int decode_win_sdhci_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 static void decode_win_cpu_setup(void); 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_cesa_setup(u_long); 96 static void decode_win_usb_setup(u_long); 97 static void decode_win_usb3_setup(u_long); 98 static void decode_win_eth_setup(u_long); 99 static void decode_win_sata_setup(u_long); 100 static void decode_win_ahci_setup(u_long); 101 static void decode_win_sdhci_setup(u_long); 102 103 static void decode_win_idma_setup(u_long); 104 static void decode_win_xor_setup(u_long); 105 106 static void decode_win_cesa_dump(u_long); 107 static void decode_win_usb_dump(u_long); 108 static void decode_win_usb3_dump(u_long); 109 static void decode_win_eth_dump(u_long base); 110 static void decode_win_idma_dump(u_long base); 111 static void decode_win_xor_dump(u_long base); 112 static void decode_win_ahci_dump(u_long base); 113 static void decode_win_sdhci_dump(u_long); 114 115 static int fdt_get_ranges(const char *, void *, int, int *, int *); 116 #ifdef SOC_MV_ARMADA38X 117 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 118 int *trig, int *pol); 119 #endif 120 121 static int win_cpu_from_dt(void); 122 static int fdt_win_setup(void); 123 124 static uint32_t dev_mask = 0; 125 static int cpu_wins_no = 0; 126 static int eth_port = 0; 127 static int usb_port = 0; 128 129 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 130 131 const struct decode_win *cpu_wins = cpu_win_tbl; 132 133 typedef void (*decode_win_setup_t)(u_long); 134 typedef void (*dump_win_t)(u_long); 135 136 struct soc_node_spec { 137 const char *compat; 138 decode_win_setup_t decode_handler; 139 dump_win_t dump_handler; 140 }; 141 142 static struct soc_node_spec soc_nodes[] = { 143 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 144 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 145 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 146 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 147 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 148 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, 149 { "mrvl,sata", &decode_win_sata_setup, NULL }, 150 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 151 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 152 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, 153 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 154 { NULL, NULL, NULL }, 155 }; 156 157 struct fdt_pm_mask_entry { 158 char *compat; 159 uint32_t mask; 160 }; 161 162 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 163 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 164 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 165 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 166 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 167 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 168 { "mrvl,xor", CPU_PM_CTRL_XOR }, 169 { "mrvl,sata", CPU_PM_CTRL_SATA }, 170 171 { NULL, 0 } 172 }; 173 174 static __inline int 175 pm_is_disabled(uint32_t mask) 176 { 177 #if defined(SOC_MV_KIRKWOOD) 178 return (soc_power_ctrl_get(mask) == mask); 179 #else 180 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 181 #endif 182 } 183 184 /* 185 * Disable device using power management register. 186 * 1 - Device Power On 187 * 0 - Device Power Off 188 * Mask can be set in loader. 189 * EXAMPLE: 190 * loader> set hw.pm-disable-mask=0x2 191 * 192 * Common mask: 193 * |-------------------------------| 194 * | Device | Kirkwood | Discovery | 195 * |-------------------------------| 196 * | USB0 | 0x00008 | 0x020000 | 197 * |-------------------------------| 198 * | USB1 | - | 0x040000 | 199 * |-------------------------------| 200 * | USB2 | - | 0x080000 | 201 * |-------------------------------| 202 * | GE0 | 0x00001 | 0x000002 | 203 * |-------------------------------| 204 * | GE1 | - | 0x000004 | 205 * |-------------------------------| 206 * | IDMA | - | 0x100000 | 207 * |-------------------------------| 208 * | XOR | 0x10000 | 0x200000 | 209 * |-------------------------------| 210 * | CESA | 0x20000 | 0x400000 | 211 * |-------------------------------| 212 * | SATA | 0x04000 | 0x004000 | 213 * --------------------------------| 214 * This feature can be used only on Kirkwood and Discovery 215 * machines. 216 */ 217 static __inline void 218 pm_disable_device(int mask) 219 { 220 #ifdef DIAGNOSTIC 221 uint32_t reg; 222 223 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 224 printf("Power Management Register: 0%x\n", reg); 225 226 reg &= ~mask; 227 soc_power_ctrl_set(reg); 228 printf("Device %x is disabled\n", mask); 229 230 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 231 printf("Power Management Register: 0%x\n", reg); 232 #endif 233 } 234 235 int 236 fdt_pm(phandle_t node) 237 { 238 uint32_t cpu_pm_ctrl; 239 int i, ena, compat; 240 241 ena = 1; 242 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 243 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 244 if (dev_mask & (1 << i)) 245 continue; 246 247 compat = ofw_bus_node_is_compatible(node, 248 fdt_pm_mask_table[i].compat); 249 #if defined(SOC_MV_KIRKWOOD) 250 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 251 dev_mask |= (1 << i); 252 ena = 0; 253 break; 254 } else if (compat) { 255 dev_mask |= (1 << i); 256 break; 257 } 258 #else 259 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 260 dev_mask |= (1 << i); 261 ena = 0; 262 break; 263 } else if (compat) { 264 dev_mask |= (1 << i); 265 break; 266 } 267 #endif 268 } 269 270 return (ena); 271 } 272 273 uint32_t 274 read_cpu_ctrl(uint32_t reg) 275 { 276 277 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 278 } 279 280 void 281 write_cpu_ctrl(uint32_t reg, uint32_t val) 282 { 283 284 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 285 } 286 287 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 288 uint32_t 289 read_cpu_mp_clocks(uint32_t reg) 290 { 291 292 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 293 } 294 295 void 296 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 297 { 298 299 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 300 } 301 302 uint32_t 303 read_cpu_misc(uint32_t reg) 304 { 305 306 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 307 } 308 309 void 310 write_cpu_misc(uint32_t reg, uint32_t val) 311 { 312 313 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 314 } 315 #endif 316 317 void 318 cpu_reset(void) 319 { 320 321 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 322 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 323 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 324 #else 325 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 326 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 327 #endif 328 while (1); 329 } 330 331 uint32_t 332 cpu_extra_feat(void) 333 { 334 uint32_t dev, rev; 335 uint32_t ef = 0; 336 337 soc_id(&dev, &rev); 338 339 switch (dev) { 340 case MV_DEV_88F6281: 341 case MV_DEV_88F6282: 342 case MV_DEV_88RC8180: 343 case MV_DEV_MV78100_Z0: 344 case MV_DEV_MV78100: 345 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 346 break; 347 case MV_DEV_88F5182: 348 case MV_DEV_88F5281: 349 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 350 break; 351 default: 352 if (bootverbose) 353 printf("This ARM Core does not support any extra features\n"); 354 } 355 356 return (ef); 357 } 358 359 /* 360 * Get the power status of device. This feature is only supported on 361 * Kirkwood and Discovery SoCs. 362 */ 363 uint32_t 364 soc_power_ctrl_get(uint32_t mask) 365 { 366 367 #if !defined(SOC_MV_ORION) 368 if (mask != CPU_PM_CTRL_NONE) 369 mask &= read_cpu_ctrl(CPU_PM_CTRL); 370 371 return (mask); 372 #else 373 return (mask); 374 #endif 375 } 376 377 /* 378 * Set the power status of device. This feature is only supported on 379 * Kirkwood and Discovery SoCs. 380 */ 381 void 382 soc_power_ctrl_set(uint32_t mask) 383 { 384 385 #if !defined(SOC_MV_ORION) 386 if (mask != CPU_PM_CTRL_NONE) 387 write_cpu_ctrl(CPU_PM_CTRL, mask); 388 #endif 389 } 390 391 void 392 soc_id(uint32_t *dev, uint32_t *rev) 393 { 394 395 /* 396 * Notice: system identifiers are available in the registers range of 397 * PCIE controller, so using this function is only allowed (and 398 * possible) after the internal registers range has been mapped in via 399 * devmap_bootstrap(). 400 */ 401 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 402 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 403 } 404 405 static void 406 soc_identify(void) 407 { 408 uint32_t d, r, size, mode; 409 const char *dev; 410 const char *rev; 411 412 soc_id(&d, &r); 413 414 printf("SOC: "); 415 if (bootverbose) 416 printf("(0x%4x:0x%02x) ", d, r); 417 418 rev = ""; 419 switch (d) { 420 case MV_DEV_88F5181: 421 dev = "Marvell 88F5181"; 422 if (r == 3) 423 rev = "B1"; 424 break; 425 case MV_DEV_88F5182: 426 dev = "Marvell 88F5182"; 427 if (r == 2) 428 rev = "A2"; 429 break; 430 case MV_DEV_88F5281: 431 dev = "Marvell 88F5281"; 432 if (r == 4) 433 rev = "D0"; 434 else if (r == 5) 435 rev = "D1"; 436 else if (r == 6) 437 rev = "D2"; 438 break; 439 case MV_DEV_88F6281: 440 dev = "Marvell 88F6281"; 441 if (r == 0) 442 rev = "Z0"; 443 else if (r == 2) 444 rev = "A0"; 445 else if (r == 3) 446 rev = "A1"; 447 break; 448 case MV_DEV_88RC8180: 449 dev = "Marvell 88RC8180"; 450 break; 451 case MV_DEV_88RC9480: 452 dev = "Marvell 88RC9480"; 453 break; 454 case MV_DEV_88RC9580: 455 dev = "Marvell 88RC9580"; 456 break; 457 case MV_DEV_88F6781: 458 dev = "Marvell 88F6781"; 459 if (r == 2) 460 rev = "Y0"; 461 break; 462 case MV_DEV_88F6282: 463 dev = "Marvell 88F6282"; 464 if (r == 0) 465 rev = "A0"; 466 else if (r == 1) 467 rev = "A1"; 468 break; 469 case MV_DEV_88F6828: 470 dev = "Marvell 88F6828"; 471 break; 472 case MV_DEV_88F6820: 473 dev = "Marvell 88F6820"; 474 break; 475 case MV_DEV_88F6810: 476 dev = "Marvell 88F6810"; 477 break; 478 case MV_DEV_MV78100_Z0: 479 dev = "Marvell MV78100 Z0"; 480 break; 481 case MV_DEV_MV78100: 482 dev = "Marvell MV78100"; 483 break; 484 case MV_DEV_MV78160: 485 dev = "Marvell MV78160"; 486 break; 487 case MV_DEV_MV78260: 488 dev = "Marvell MV78260"; 489 break; 490 case MV_DEV_MV78460: 491 dev = "Marvell MV78460"; 492 break; 493 default: 494 dev = "UNKNOWN"; 495 break; 496 } 497 498 printf("%s", dev); 499 if (*rev != '\0') 500 printf(" rev %s", rev); 501 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 502 503 mode = read_cpu_ctrl(CPU_CONFIG); 504 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 505 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 506 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 507 508 switch (d) { 509 case MV_DEV_88F6281: 510 case MV_DEV_88F6282: 511 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 512 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 513 mode ? "write-through" : "write-back"); 514 break; 515 case MV_DEV_MV78100: 516 mode = read_cpu_ctrl(CPU_CONTROL); 517 size = mode & CPU_CONTROL_L2_SIZE; 518 mode = mode & CPU_CONTROL_L2_MODE; 519 printf(" %s set-associative %s unified L2 cache\n", 520 size ? "256KB 4-way" : "512KB 8-way", 521 mode ? "write-through" : "write-back"); 522 break; 523 default: 524 break; 525 } 526 } 527 528 static void 529 platform_identify(void *dummy) 530 { 531 532 soc_identify(); 533 534 /* 535 * XXX Board identification e.g. read out from FPGA or similar should 536 * go here 537 */ 538 } 539 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 540 NULL); 541 542 #ifdef KDB 543 static void 544 mv_enter_debugger(void *dummy) 545 { 546 547 if (boothowto & RB_KDB) 548 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 549 } 550 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 551 #endif 552 553 int 554 soc_decode_win(void) 555 { 556 uint32_t dev, rev; 557 int mask, err; 558 559 mask = 0; 560 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 561 562 if (mask != 0) 563 pm_disable_device(mask); 564 565 /* Retrieve data about physical addresses from device tree. */ 566 if ((err = win_cpu_from_dt()) != 0) 567 return (err); 568 569 /* Retrieve our ID: some windows facilities vary between SoC models */ 570 soc_id(&dev, &rev); 571 572 #ifdef SOC_MV_ARMADAXP 573 if ((err = decode_win_sdram_fixup()) != 0) 574 return(err); 575 #endif 576 577 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 578 !decode_win_eth_valid() || !decode_win_idma_valid() || 579 !decode_win_pcie_valid() || !decode_win_sata_valid() || 580 !decode_win_xor_valid() || !decode_win_usb3_valid() || 581 !decode_win_sdhci_valid() || !decode_win_cesa_valid()) 582 return (EINVAL); 583 584 decode_win_cpu_setup(); 585 if (MV_DUMP_WIN) 586 soc_dump_decode_win(); 587 588 eth_port = 0; 589 usb_port = 0; 590 if ((err = fdt_win_setup()) != 0) 591 return (err); 592 593 return (0); 594 } 595 596 /************************************************************************** 597 * Decode windows registers accessors 598 **************************************************************************/ 599 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 600 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 601 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 602 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 603 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 604 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 605 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 606 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 607 608 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 609 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 610 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 611 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 612 613 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 614 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 615 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 616 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 617 618 #ifdef SOC_MV_ARMADA38X 619 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 620 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 621 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 622 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 623 #endif 624 625 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 626 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 627 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 628 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 629 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 630 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 631 632 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 633 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 634 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 635 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 636 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 637 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 638 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 639 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 640 641 WIN_REG_BASE_RD(win_eth, bare, 0x290) 642 WIN_REG_BASE_RD(win_eth, epap, 0x294) 643 WIN_REG_BASE_WR(win_eth, bare, 0x290) 644 WIN_REG_BASE_WR(win_eth, epap, 0x294) 645 646 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 647 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 648 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 649 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 650 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 651 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 652 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 653 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 654 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 655 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 656 657 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 658 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 659 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 660 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 661 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 662 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 663 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 664 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 665 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 666 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 667 668 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 669 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 670 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 671 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 672 #if defined(SOC_MV_ARMADA38X) 673 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 674 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 675 #endif 676 677 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 678 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 679 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 680 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 681 682 #ifndef SOC_MV_DOVE 683 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 684 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 685 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 686 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 687 #else 688 /* 689 * On 88F6781 (Dove) SoC DDR Controller is accessed through 690 * single MBUS <-> AXI bridge. In this case we provide emulated 691 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 692 * with common decoding windows setup code. 693 */ 694 695 static inline uint32_t ddr_br_read(int i) 696 { 697 uint32_t mmap; 698 699 /* Read Memory Address Map Register for CS i */ 700 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 701 702 /* Return CS i base address */ 703 return (mmap & 0xFF000000); 704 } 705 706 static inline uint32_t ddr_sz_read(int i) 707 { 708 uint32_t mmap, size; 709 710 /* Read Memory Address Map Register for CS i */ 711 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 712 713 /* Extract size of CS space in 64kB units */ 714 size = (1 << ((mmap >> 16) & 0x0F)); 715 716 /* Return CS size and enable/disable status */ 717 return (((size - 1) << 16) | (mmap & 0x01)); 718 } 719 #endif 720 721 /************************************************************************** 722 * Decode windows helper routines 723 **************************************************************************/ 724 void 725 soc_dump_decode_win(void) 726 { 727 uint32_t dev, rev; 728 int i; 729 730 soc_id(&dev, &rev); 731 732 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 733 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 734 win_cpu_cr_read(i), 735 win_cpu_br_read(i)); 736 737 if (win_cpu_can_remap(i)) 738 printf(", rl 0x%08x, rh 0x%08x", 739 win_cpu_remap_l_read(i), 740 win_cpu_remap_h_read(i)); 741 742 printf("\n"); 743 } 744 printf("Internal regs base: 0x%08x\n", 745 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 746 747 for (i = 0; i < MV_WIN_DDR_MAX; i++) 748 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 749 ddr_br_read(i), ddr_sz_read(i)); 750 } 751 752 /************************************************************************** 753 * CPU windows routines 754 **************************************************************************/ 755 int 756 win_cpu_can_remap(int i) 757 { 758 uint32_t dev, rev; 759 760 soc_id(&dev, &rev); 761 762 /* Depending on the SoC certain windows have remap capability */ 763 if ((dev == MV_DEV_88F5182 && i < 2) || 764 (dev == MV_DEV_88F5281 && i < 4) || 765 (dev == MV_DEV_88F6281 && i < 4) || 766 (dev == MV_DEV_88F6282 && i < 4) || 767 (dev == MV_DEV_88F6828 && i < 20) || 768 (dev == MV_DEV_88F6820 && i < 20) || 769 (dev == MV_DEV_88F6810 && i < 20) || 770 (dev == MV_DEV_88RC8180 && i < 2) || 771 (dev == MV_DEV_88F6781 && i < 4) || 772 (dev == MV_DEV_MV78100_Z0 && i < 8) || 773 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 774 return (1); 775 776 return (0); 777 } 778 779 /* XXX This should check for overlapping remap fields too.. */ 780 int 781 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 782 { 783 const struct decode_win *tab; 784 int i; 785 786 tab = wintab; 787 788 for (i = 0; i < win_no; i++, tab++) { 789 if (i == win) 790 /* Skip self */ 791 continue; 792 793 if ((tab->base + tab->size - 1) < (wintab + win)->base) 794 continue; 795 796 else if (((wintab + win)->base + (wintab + win)->size - 1) < 797 tab->base) 798 continue; 799 else 800 return (i); 801 } 802 803 return (-1); 804 } 805 806 static int 807 decode_win_cpu_valid(void) 808 { 809 int i, j, rv; 810 uint32_t b, e, s; 811 812 if (cpu_wins_no > MV_WIN_CPU_MAX) { 813 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 814 return (0); 815 } 816 817 rv = 1; 818 for (i = 0; i < cpu_wins_no; i++) { 819 820 if (cpu_wins[i].target == 0) { 821 printf("CPU window#%d: DDR target window is not " 822 "supposed to be reprogrammed!\n", i); 823 rv = 0; 824 } 825 826 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 827 printf("CPU window#%d: not capable of remapping, but " 828 "val 0x%08x defined\n", i, cpu_wins[i].remap); 829 rv = 0; 830 } 831 832 s = cpu_wins[i].size; 833 b = cpu_wins[i].base; 834 e = b + s - 1; 835 if (s > (0xFFFFFFFF - b + 1)) { 836 /* 837 * XXX this boundary check should account for 64bit 838 * and remapping.. 839 */ 840 printf("CPU window#%d: no space for size 0x%08x at " 841 "0x%08x\n", i, s, b); 842 rv = 0; 843 continue; 844 } 845 846 if (b != rounddown2(b, s)) { 847 printf("CPU window#%d: address 0x%08x is not aligned " 848 "to 0x%08x\n", i, b, s); 849 rv = 0; 850 continue; 851 } 852 853 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 854 if (j >= 0) { 855 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 856 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 857 cpu_wins[j].base, 858 cpu_wins[j].base + cpu_wins[j].size - 1); 859 rv = 0; 860 } 861 } 862 863 return (rv); 864 } 865 866 int 867 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 868 vm_paddr_t remap) 869 { 870 uint32_t br, cr; 871 int win, i; 872 873 if (remap == ~0) { 874 win = MV_WIN_CPU_MAX - 1; 875 i = -1; 876 } else { 877 win = 0; 878 i = 1; 879 } 880 881 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 882 cr = win_cpu_cr_read(win); 883 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 884 break; 885 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 886 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 887 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 888 (target << MV_WIN_CPU_TARGET_SHIFT))) 889 break; 890 win += i; 891 } 892 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 893 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 894 return (-1); 895 896 br = base & 0xffff0000; 897 win_cpu_br_write(win, br); 898 899 if (win_cpu_can_remap(win)) { 900 if (remap != ~0) { 901 win_cpu_remap_l_write(win, remap & 0xffff0000); 902 win_cpu_remap_h_write(win, 0); 903 } else { 904 /* 905 * Remap function is not used for a given window 906 * (capable of remapping) - set remap field with the 907 * same value as base. 908 */ 909 win_cpu_remap_l_write(win, base & 0xffff0000); 910 win_cpu_remap_h_write(win, 0); 911 } 912 } 913 914 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 915 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 916 win_cpu_cr_write(win, cr); 917 918 return (0); 919 } 920 921 static void 922 decode_win_cpu_setup(void) 923 { 924 int i; 925 926 /* Disable all CPU windows */ 927 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 928 win_cpu_cr_write(i, 0); 929 win_cpu_br_write(i, 0); 930 if (win_cpu_can_remap(i)) { 931 win_cpu_remap_l_write(i, 0); 932 win_cpu_remap_h_write(i, 0); 933 } 934 } 935 936 for (i = 0; i < cpu_wins_no; i++) 937 if (cpu_wins[i].target > 0) 938 decode_win_cpu_set(cpu_wins[i].target, 939 cpu_wins[i].attr, cpu_wins[i].base, 940 cpu_wins[i].size, cpu_wins[i].remap); 941 942 } 943 944 #ifdef SOC_MV_ARMADAXP 945 static int 946 decode_win_sdram_fixup(void) 947 { 948 struct mem_region mr[FDT_MEM_REGIONS]; 949 uint8_t window_valid[MV_WIN_DDR_MAX]; 950 int mr_cnt, err, i, j; 951 uint32_t valid_win_num = 0; 952 953 /* Grab physical memory regions information from device tree. */ 954 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 955 if (err != 0) 956 return (err); 957 958 for (i = 0; i < MV_WIN_DDR_MAX; i++) 959 window_valid[i] = 0; 960 961 /* Try to match entries from device tree with settings from u-boot */ 962 for (i = 0; i < mr_cnt; i++) { 963 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 964 if (ddr_is_active(j) && 965 (ddr_base(j) == mr[i].mr_start) && 966 (ddr_size(j) == mr[i].mr_size)) { 967 window_valid[j] = 1; 968 valid_win_num++; 969 } 970 } 971 } 972 973 if (mr_cnt != valid_win_num) 974 return (EINVAL); 975 976 /* Destroy windows without corresponding device tree entry */ 977 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 978 if (ddr_is_active(j) && (window_valid[j] != 1)) { 979 printf("Disabling SDRAM decoding window: %d\n", j); 980 ddr_disable(j); 981 } 982 } 983 984 return (0); 985 } 986 #endif 987 /* 988 * Check if we're able to cover all active DDR banks. 989 */ 990 static int 991 decode_win_can_cover_ddr(int max) 992 { 993 int i, c; 994 995 c = 0; 996 for (i = 0; i < MV_WIN_DDR_MAX; i++) 997 if (ddr_is_active(i)) 998 c++; 999 1000 if (c > max) { 1001 printf("Unable to cover all active DDR banks: " 1002 "%d, available windows: %d\n", c, max); 1003 return (0); 1004 } 1005 1006 return (1); 1007 } 1008 1009 /************************************************************************** 1010 * DDR windows routines 1011 **************************************************************************/ 1012 int 1013 ddr_is_active(int i) 1014 { 1015 1016 if (ddr_sz_read(i) & 0x1) 1017 return (1); 1018 1019 return (0); 1020 } 1021 1022 void 1023 ddr_disable(int i) 1024 { 1025 1026 ddr_sz_write(i, 0); 1027 ddr_br_write(i, 0); 1028 } 1029 1030 uint32_t 1031 ddr_base(int i) 1032 { 1033 1034 return (ddr_br_read(i) & 0xff000000); 1035 } 1036 1037 uint32_t 1038 ddr_size(int i) 1039 { 1040 1041 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1042 } 1043 1044 uint32_t 1045 ddr_attr(int i) 1046 { 1047 uint32_t dev, rev; 1048 1049 soc_id(&dev, &rev); 1050 if (dev == MV_DEV_88RC8180) 1051 return ((ddr_sz_read(i) & 0xf0) >> 4); 1052 if (dev == MV_DEV_88F6781) 1053 return (0); 1054 1055 return (i == 0 ? 0xe : 1056 (i == 1 ? 0xd : 1057 (i == 2 ? 0xb : 1058 (i == 3 ? 0x7 : 0xff)))); 1059 } 1060 1061 uint32_t 1062 ddr_target(int i) 1063 { 1064 uint32_t dev, rev; 1065 1066 soc_id(&dev, &rev); 1067 if (dev == MV_DEV_88RC8180) { 1068 i = (ddr_sz_read(i) & 0xf0) >> 4; 1069 return (i == 0xe ? 0xc : 1070 (i == 0xd ? 0xd : 1071 (i == 0xb ? 0xe : 1072 (i == 0x7 ? 0xf : 0xc)))); 1073 } 1074 1075 /* 1076 * On SOCs other than 88RC8180 Mbus unit ID for 1077 * DDR SDRAM controller is always 0x0. 1078 */ 1079 return (0); 1080 } 1081 1082 /************************************************************************** 1083 * CESA windows routines 1084 **************************************************************************/ 1085 static int 1086 decode_win_cesa_valid(void) 1087 { 1088 1089 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1090 } 1091 1092 static void 1093 decode_win_cesa_dump(u_long base) 1094 { 1095 int i; 1096 1097 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1098 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1099 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1100 } 1101 1102 /* 1103 * Set CESA decode windows. 1104 */ 1105 static void 1106 decode_win_cesa_setup(u_long base) 1107 { 1108 uint32_t br, cr; 1109 int i, j; 1110 1111 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1112 win_cesa_cr_write(base, i, 0); 1113 win_cesa_br_write(base, i, 0); 1114 } 1115 1116 /* Only access to active DRAM banks is required */ 1117 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1118 if (ddr_is_active(i)) { 1119 br = ddr_base(i); 1120 1121 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1122 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1123 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1124 IO_WIN_ENA_MASK); 1125 1126 /* Set the first free CESA window */ 1127 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1128 if (win_cesa_cr_read(base, j) & 0x1) 1129 continue; 1130 1131 win_cesa_br_write(base, j, br); 1132 win_cesa_cr_write(base, j, cr); 1133 break; 1134 } 1135 } 1136 } 1137 } 1138 1139 /************************************************************************** 1140 * USB windows routines 1141 **************************************************************************/ 1142 static int 1143 decode_win_usb_valid(void) 1144 { 1145 1146 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1147 } 1148 1149 static void 1150 decode_win_usb_dump(u_long base) 1151 { 1152 int i; 1153 1154 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1155 return; 1156 1157 for (i = 0; i < MV_WIN_USB_MAX; i++) 1158 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1159 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1160 } 1161 1162 /* 1163 * Set USB decode windows. 1164 */ 1165 static void 1166 decode_win_usb_setup(u_long base) 1167 { 1168 uint32_t br, cr; 1169 int i, j; 1170 1171 1172 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1173 return; 1174 1175 usb_port++; 1176 1177 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1178 win_usb_cr_write(base, i, 0); 1179 win_usb_br_write(base, i, 0); 1180 } 1181 1182 /* Only access to active DRAM banks is required */ 1183 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1184 if (ddr_is_active(i)) { 1185 br = ddr_base(i); 1186 /* 1187 * XXX for 6281 we should handle Mbus write 1188 * burst limit field in the ctrl reg 1189 */ 1190 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1191 (ddr_attr(i) << 8) | 1192 (ddr_target(i) << 4) | 1); 1193 1194 /* Set the first free USB window */ 1195 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1196 if (win_usb_cr_read(base, j) & 0x1) 1197 continue; 1198 1199 win_usb_br_write(base, j, br); 1200 win_usb_cr_write(base, j, cr); 1201 break; 1202 } 1203 } 1204 } 1205 } 1206 1207 /************************************************************************** 1208 * USB3 windows routines 1209 **************************************************************************/ 1210 #ifdef SOC_MV_ARMADA38X 1211 static int 1212 decode_win_usb3_valid(void) 1213 { 1214 1215 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1216 } 1217 1218 static void 1219 decode_win_usb3_dump(u_long base) 1220 { 1221 int i; 1222 1223 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1224 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1225 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1226 } 1227 1228 /* 1229 * Set USB3 decode windows 1230 */ 1231 static void 1232 decode_win_usb3_setup(u_long base) 1233 { 1234 uint32_t br, cr; 1235 int i, j; 1236 1237 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1238 win_usb3_cr_write(base, i, 0); 1239 win_usb3_br_write(base, i, 0); 1240 } 1241 1242 /* Only access to active DRAM banks is required */ 1243 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1244 if (ddr_is_active(i)) { 1245 br = ddr_base(i); 1246 cr = (((ddr_size(i) - 1) & 1247 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1248 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1249 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1250 IO_WIN_ENA_MASK); 1251 1252 /* Set the first free USB3.0 window */ 1253 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1254 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1255 continue; 1256 1257 win_usb3_br_write(base, j, br); 1258 win_usb3_cr_write(base, j, cr); 1259 break; 1260 } 1261 } 1262 } 1263 } 1264 #else 1265 /* 1266 * Provide dummy functions to satisfy the build 1267 * for SoCs not equipped with USB3 1268 */ 1269 static int 1270 decode_win_usb3_valid(void) 1271 { 1272 1273 return (1); 1274 } 1275 1276 static void 1277 decode_win_usb3_setup(u_long base) 1278 { 1279 } 1280 1281 static void 1282 decode_win_usb3_dump(u_long base) 1283 { 1284 } 1285 #endif 1286 /************************************************************************** 1287 * ETH windows routines 1288 **************************************************************************/ 1289 1290 static int 1291 win_eth_can_remap(int i) 1292 { 1293 1294 /* ETH encode windows 0-3 have remap capability */ 1295 if (i < 4) 1296 return (1); 1297 1298 return (0); 1299 } 1300 1301 static int 1302 eth_bare_read(uint32_t base, int i) 1303 { 1304 uint32_t v; 1305 1306 v = win_eth_bare_read(base); 1307 v &= (1 << i); 1308 1309 return (v >> i); 1310 } 1311 1312 static void 1313 eth_bare_write(uint32_t base, int i, int val) 1314 { 1315 uint32_t v; 1316 1317 v = win_eth_bare_read(base); 1318 v &= ~(1 << i); 1319 v |= (val << i); 1320 win_eth_bare_write(base, v); 1321 } 1322 1323 static void 1324 eth_epap_write(uint32_t base, int i, int val) 1325 { 1326 uint32_t v; 1327 1328 v = win_eth_epap_read(base); 1329 v &= ~(0x3 << (i * 2)); 1330 v |= (val << (i * 2)); 1331 win_eth_epap_write(base, v); 1332 } 1333 1334 static void 1335 decode_win_eth_dump(u_long base) 1336 { 1337 int i; 1338 1339 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1340 return; 1341 1342 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1343 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1344 win_eth_br_read(base, i), 1345 win_eth_sz_read(base, i)); 1346 1347 if (win_eth_can_remap(i)) 1348 printf(", ha 0x%08x", 1349 win_eth_har_read(base, i)); 1350 1351 printf("\n"); 1352 } 1353 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1354 win_eth_bare_read(base), 1355 win_eth_epap_read(base)); 1356 } 1357 1358 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1359 1360 static void 1361 decode_win_eth_setup(u_long base) 1362 { 1363 uint32_t br, sz; 1364 int i, j; 1365 1366 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1367 return; 1368 1369 eth_port++; 1370 1371 /* Disable, clear and revoke protection for all ETH windows */ 1372 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1373 1374 eth_bare_write(base, i, 1); 1375 eth_epap_write(base, i, 0); 1376 win_eth_br_write(base, i, 0); 1377 win_eth_sz_write(base, i, 0); 1378 if (win_eth_can_remap(i)) 1379 win_eth_har_write(base, i, 0); 1380 } 1381 1382 /* Only access to active DRAM banks is required */ 1383 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1384 if (ddr_is_active(i)) { 1385 1386 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1387 sz = ((ddr_size(i) - 1) & 0xffff0000); 1388 1389 /* Set the first free ETH window */ 1390 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1391 if (eth_bare_read(base, j) == 0) 1392 continue; 1393 1394 win_eth_br_write(base, j, br); 1395 win_eth_sz_write(base, j, sz); 1396 1397 /* XXX remapping ETH windows not supported */ 1398 1399 /* Set protection RW */ 1400 eth_epap_write(base, j, 0x3); 1401 1402 /* Enable window */ 1403 eth_bare_write(base, j, 0); 1404 break; 1405 } 1406 } 1407 } 1408 1409 static int 1410 decode_win_eth_valid(void) 1411 { 1412 1413 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1414 } 1415 1416 /************************************************************************** 1417 * PCIE windows routines 1418 **************************************************************************/ 1419 1420 void 1421 decode_win_pcie_setup(u_long base) 1422 { 1423 uint32_t size = 0, ddrbase = ~0; 1424 uint32_t cr, br; 1425 int i, j; 1426 1427 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1428 pcie_bar_br_write(base, i, 1429 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1430 if (i < 3) 1431 pcie_bar_brh_write(base, i, 0); 1432 if (i > 0) 1433 pcie_bar_cr_write(base, i, 0); 1434 } 1435 1436 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1437 win_pcie_cr_write(base, i, 0); 1438 win_pcie_br_write(base, i, 0); 1439 win_pcie_remap_write(base, i, 0); 1440 } 1441 1442 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1443 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1444 & MV_PCIE_ROOT_CMPLX) == 0) { 1445 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1446 return; 1447 } 1448 1449 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1450 if (ddr_is_active(i)) { 1451 /* Map DDR to BAR 1 */ 1452 cr = (ddr_size(i) - 1) & 0xffff0000; 1453 size += ddr_size(i) & 0xffff0000; 1454 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1455 br = ddr_base(i); 1456 if (br < ddrbase) 1457 ddrbase = br; 1458 1459 /* Use the first available PCIE window */ 1460 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1461 if (win_pcie_cr_read(base, j) != 0) 1462 continue; 1463 1464 win_pcie_br_write(base, j, br); 1465 win_pcie_cr_write(base, j, cr); 1466 break; 1467 } 1468 } 1469 } 1470 1471 /* 1472 * Upper 16 bits in BAR register is interpreted as BAR size 1473 * (in 64 kB units) plus 64kB, so subtract 0x10000 1474 * form value passed to register to get correct value. 1475 */ 1476 size -= 0x10000; 1477 pcie_bar_cr_write(base, 1, size | 1); 1478 pcie_bar_br_write(base, 1, ddrbase | 1479 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1480 pcie_bar_br_write(base, 0, fdt_immr_pa | 1481 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1482 } 1483 1484 static int 1485 decode_win_pcie_valid(void) 1486 { 1487 1488 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1489 } 1490 1491 /************************************************************************** 1492 * IDMA windows routines 1493 **************************************************************************/ 1494 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1495 static int 1496 idma_bare_read(u_long base, int i) 1497 { 1498 uint32_t v; 1499 1500 v = win_idma_bare_read(base); 1501 v &= (1 << i); 1502 1503 return (v >> i); 1504 } 1505 1506 static void 1507 idma_bare_write(u_long base, int i, int val) 1508 { 1509 uint32_t v; 1510 1511 v = win_idma_bare_read(base); 1512 v &= ~(1 << i); 1513 v |= (val << i); 1514 win_idma_bare_write(base, v); 1515 } 1516 1517 /* 1518 * Sets channel protection 'val' for window 'w' on channel 'c' 1519 */ 1520 static void 1521 idma_cap_write(u_long base, int c, int w, int val) 1522 { 1523 uint32_t v; 1524 1525 v = win_idma_cap_read(base, c); 1526 v &= ~(0x3 << (w * 2)); 1527 v |= (val << (w * 2)); 1528 win_idma_cap_write(base, c, v); 1529 } 1530 1531 /* 1532 * Set protection 'val' on all channels for window 'w' 1533 */ 1534 static void 1535 idma_set_prot(u_long base, int w, int val) 1536 { 1537 int c; 1538 1539 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1540 idma_cap_write(base, c, w, val); 1541 } 1542 1543 static int 1544 win_idma_can_remap(int i) 1545 { 1546 1547 /* IDMA decode windows 0-3 have remap capability */ 1548 if (i < 4) 1549 return (1); 1550 1551 return (0); 1552 } 1553 1554 void 1555 decode_win_idma_setup(u_long base) 1556 { 1557 uint32_t br, sz; 1558 int i, j; 1559 1560 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1561 return; 1562 /* 1563 * Disable and clear all IDMA windows, revoke protection for all channels 1564 */ 1565 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1566 1567 idma_bare_write(base, i, 1); 1568 win_idma_br_write(base, i, 0); 1569 win_idma_sz_write(base, i, 0); 1570 if (win_idma_can_remap(i) == 1) 1571 win_idma_har_write(base, i, 0); 1572 } 1573 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1574 win_idma_cap_write(base, i, 0); 1575 1576 /* 1577 * Set up access to all active DRAM banks 1578 */ 1579 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1580 if (ddr_is_active(i)) { 1581 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1582 sz = ((ddr_size(i) - 1) & 0xffff0000); 1583 1584 /* Place DDR entries in non-remapped windows */ 1585 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1586 if (win_idma_can_remap(j) != 1 && 1587 idma_bare_read(base, j) == 1) { 1588 1589 /* Configure window */ 1590 win_idma_br_write(base, j, br); 1591 win_idma_sz_write(base, j, sz); 1592 1593 /* Set protection RW on all channels */ 1594 idma_set_prot(base, j, 0x3); 1595 1596 /* Enable window */ 1597 idma_bare_write(base, j, 0); 1598 break; 1599 } 1600 } 1601 1602 /* 1603 * Remaining targets -- from statically defined table 1604 */ 1605 for (i = 0; i < idma_wins_no; i++) 1606 if (idma_wins[i].target > 0) { 1607 br = (idma_wins[i].base & 0xffff0000) | 1608 (idma_wins[i].attr << 8) | idma_wins[i].target; 1609 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1610 1611 /* Set the first free IDMA window */ 1612 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1613 if (idma_bare_read(base, j) == 0) 1614 continue; 1615 1616 /* Configure window */ 1617 win_idma_br_write(base, j, br); 1618 win_idma_sz_write(base, j, sz); 1619 if (win_idma_can_remap(j) && 1620 idma_wins[j].remap >= 0) 1621 win_idma_har_write(base, j, 1622 idma_wins[j].remap); 1623 1624 /* Set protection RW on all channels */ 1625 idma_set_prot(base, j, 0x3); 1626 1627 /* Enable window */ 1628 idma_bare_write(base, j, 0); 1629 break; 1630 } 1631 } 1632 } 1633 1634 int 1635 decode_win_idma_valid(void) 1636 { 1637 const struct decode_win *wintab; 1638 int c, i, j, rv; 1639 uint32_t b, e, s; 1640 1641 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1642 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1643 return (0); 1644 } 1645 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1646 if (ddr_is_active(i)) 1647 c++; 1648 1649 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1650 printf("IDMA windows: too many entries: %d, available: %d\n", 1651 idma_wins_no, MV_WIN_IDMA_MAX - c); 1652 return (0); 1653 } 1654 1655 wintab = idma_wins; 1656 rv = 1; 1657 for (i = 0; i < idma_wins_no; i++, wintab++) { 1658 1659 if (wintab->target == 0) { 1660 printf("IDMA window#%d: DDR target window is not " 1661 "supposed to be reprogrammed!\n", i); 1662 rv = 0; 1663 } 1664 1665 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1666 printf("IDMA window#%d: not capable of remapping, but " 1667 "val 0x%08x defined\n", i, wintab->remap); 1668 rv = 0; 1669 } 1670 1671 s = wintab->size; 1672 b = wintab->base; 1673 e = b + s - 1; 1674 if (s > (0xFFFFFFFF - b + 1)) { 1675 /* XXX this boundary check should account for 64bit and 1676 * remapping.. */ 1677 printf("IDMA window#%d: no space for size 0x%08x at " 1678 "0x%08x\n", i, s, b); 1679 rv = 0; 1680 continue; 1681 } 1682 1683 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1684 if (j >= 0) { 1685 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1686 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1687 idma_wins[j].base, 1688 idma_wins[j].base + idma_wins[j].size - 1); 1689 rv = 0; 1690 } 1691 } 1692 1693 return (rv); 1694 } 1695 1696 void 1697 decode_win_idma_dump(u_long base) 1698 { 1699 int i; 1700 1701 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1702 return; 1703 1704 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1705 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1706 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1707 1708 if (win_idma_can_remap(i)) 1709 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1710 1711 printf("\n"); 1712 } 1713 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1714 printf("IDMA channel#%d: ap 0x%08x\n", i, 1715 win_idma_cap_read(base, i)); 1716 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1717 } 1718 #else 1719 1720 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1721 int 1722 decode_win_idma_valid(void) 1723 { 1724 1725 return (1); 1726 } 1727 1728 void 1729 decode_win_idma_setup(u_long base) 1730 { 1731 } 1732 1733 void 1734 decode_win_idma_dump(u_long base) 1735 { 1736 } 1737 #endif 1738 1739 /************************************************************************** 1740 * XOR windows routines 1741 **************************************************************************/ 1742 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1743 static int 1744 xor_ctrl_read(u_long base, int i, int c, int e) 1745 { 1746 uint32_t v; 1747 v = win_xor_ctrl_read(base, c, e); 1748 v &= (1 << i); 1749 1750 return (v >> i); 1751 } 1752 1753 static void 1754 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1755 { 1756 uint32_t v; 1757 1758 v = win_xor_ctrl_read(base, c, e); 1759 v &= ~(1 << i); 1760 v |= (val << i); 1761 win_xor_ctrl_write(base, c, e, v); 1762 } 1763 1764 /* 1765 * Set channel protection 'val' for window 'w' on channel 'c' 1766 */ 1767 static void 1768 xor_chan_write(u_long base, int c, int e, int w, int val) 1769 { 1770 uint32_t v; 1771 1772 v = win_xor_ctrl_read(base, c, e); 1773 v &= ~(0x3 << (w * 2 + 16)); 1774 v |= (val << (w * 2 + 16)); 1775 win_xor_ctrl_write(base, c, e, v); 1776 } 1777 1778 /* 1779 * Set protection 'val' on all channels for window 'w' on engine 'e' 1780 */ 1781 static void 1782 xor_set_prot(u_long base, int w, int e, int val) 1783 { 1784 int c; 1785 1786 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1787 xor_chan_write(base, c, e, w, val); 1788 } 1789 1790 static int 1791 win_xor_can_remap(int i) 1792 { 1793 1794 /* XOR decode windows 0-3 have remap capability */ 1795 if (i < 4) 1796 return (1); 1797 1798 return (0); 1799 } 1800 1801 static int 1802 xor_max_eng(void) 1803 { 1804 uint32_t dev, rev; 1805 1806 soc_id(&dev, &rev); 1807 switch (dev) { 1808 case MV_DEV_88F6281: 1809 case MV_DEV_88F6282: 1810 case MV_DEV_MV78130: 1811 case MV_DEV_MV78160: 1812 case MV_DEV_MV78230: 1813 case MV_DEV_MV78260: 1814 case MV_DEV_MV78460: 1815 return (2); 1816 case MV_DEV_MV78100: 1817 case MV_DEV_MV78100_Z0: 1818 return (1); 1819 default: 1820 return (0); 1821 } 1822 } 1823 1824 static void 1825 xor_active_dram(u_long base, int c, int e, int *window) 1826 { 1827 uint32_t br, sz; 1828 int i, m, w; 1829 1830 /* 1831 * Set up access to all active DRAM banks 1832 */ 1833 m = xor_max_eng(); 1834 for (i = 0; i < m; i++) 1835 if (ddr_is_active(i)) { 1836 br = ddr_base(i) | (ddr_attr(i) << 8) | 1837 ddr_target(i); 1838 sz = ((ddr_size(i) - 1) & 0xffff0000); 1839 1840 /* Place DDR entries in non-remapped windows */ 1841 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1842 if (win_xor_can_remap(w) != 1 && 1843 (xor_ctrl_read(base, w, c, e) == 0) && 1844 w > *window) { 1845 /* Configure window */ 1846 win_xor_br_write(base, w, e, br); 1847 win_xor_sz_write(base, w, e, sz); 1848 1849 /* Set protection RW on all channels */ 1850 xor_set_prot(base, w, e, 0x3); 1851 1852 /* Enable window */ 1853 xor_ctrl_write(base, w, c, e, 1); 1854 (*window)++; 1855 break; 1856 } 1857 } 1858 } 1859 1860 void 1861 decode_win_xor_setup(u_long base) 1862 { 1863 uint32_t br, sz; 1864 int i, j, z, e = 1, m, window; 1865 1866 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1867 return; 1868 1869 /* 1870 * Disable and clear all XOR windows, revoke protection for all 1871 * channels 1872 */ 1873 m = xor_max_eng(); 1874 for (j = 0; j < m; j++, e--) { 1875 1876 /* Number of non-remaped windows */ 1877 window = MV_XOR_NON_REMAP - 1; 1878 1879 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1880 win_xor_br_write(base, i, e, 0); 1881 win_xor_sz_write(base, i, e, 0); 1882 } 1883 1884 if (win_xor_can_remap(i) == 1) 1885 win_xor_har_write(base, i, e, 0); 1886 1887 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1888 win_xor_ctrl_write(base, i, e, 0); 1889 xor_active_dram(base, i, e, &window); 1890 } 1891 1892 /* 1893 * Remaining targets -- from a statically defined table 1894 */ 1895 for (i = 0; i < xor_wins_no; i++) 1896 if (xor_wins[i].target > 0) { 1897 br = (xor_wins[i].base & 0xffff0000) | 1898 (xor_wins[i].attr << 8) | 1899 xor_wins[i].target; 1900 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1901 1902 /* Set the first free XOR window */ 1903 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1904 if (xor_ctrl_read(base, z, 0, e) && 1905 xor_ctrl_read(base, z, 1, e)) 1906 continue; 1907 1908 /* Configure window */ 1909 win_xor_br_write(base, z, e, br); 1910 win_xor_sz_write(base, z, e, sz); 1911 if (win_xor_can_remap(z) && 1912 xor_wins[z].remap >= 0) 1913 win_xor_har_write(base, z, e, 1914 xor_wins[z].remap); 1915 1916 /* Set protection RW on all channels */ 1917 xor_set_prot(base, z, e, 0x3); 1918 1919 /* Enable window */ 1920 xor_ctrl_write(base, z, 0, e, 1); 1921 xor_ctrl_write(base, z, 1, e, 1); 1922 break; 1923 } 1924 } 1925 } 1926 } 1927 1928 int 1929 decode_win_xor_valid(void) 1930 { 1931 const struct decode_win *wintab; 1932 int c, i, j, rv; 1933 uint32_t b, e, s; 1934 1935 if (xor_wins_no > MV_WIN_XOR_MAX) { 1936 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1937 return (0); 1938 } 1939 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1940 if (ddr_is_active(i)) 1941 c++; 1942 1943 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1944 printf("XOR windows: too many entries: %d, available: %d\n", 1945 xor_wins_no, MV_WIN_IDMA_MAX - c); 1946 return (0); 1947 } 1948 1949 wintab = xor_wins; 1950 rv = 1; 1951 for (i = 0; i < xor_wins_no; i++, wintab++) { 1952 1953 if (wintab->target == 0) { 1954 printf("XOR window#%d: DDR target window is not " 1955 "supposed to be reprogrammed!\n", i); 1956 rv = 0; 1957 } 1958 1959 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1960 printf("XOR window#%d: not capable of remapping, but " 1961 "val 0x%08x defined\n", i, wintab->remap); 1962 rv = 0; 1963 } 1964 1965 s = wintab->size; 1966 b = wintab->base; 1967 e = b + s - 1; 1968 if (s > (0xFFFFFFFF - b + 1)) { 1969 /* 1970 * XXX this boundary check should account for 64bit 1971 * and remapping.. 1972 */ 1973 printf("XOR window#%d: no space for size 0x%08x at " 1974 "0x%08x\n", i, s, b); 1975 rv = 0; 1976 continue; 1977 } 1978 1979 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 1980 if (j >= 0) { 1981 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 1982 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1983 xor_wins[j].base, 1984 xor_wins[j].base + xor_wins[j].size - 1); 1985 rv = 0; 1986 } 1987 } 1988 1989 return (rv); 1990 } 1991 1992 void 1993 decode_win_xor_dump(u_long base) 1994 { 1995 int i, j; 1996 int e = 1; 1997 1998 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1999 return; 2000 2001 for (j = 0; j < xor_max_eng(); j++, e--) { 2002 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2003 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2004 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2005 2006 if (win_xor_can_remap(i)) 2007 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2008 2009 printf("\n"); 2010 } 2011 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2012 printf("XOR control#%d: 0x%08x\n", i, 2013 win_xor_ctrl_read(base, i, e)); 2014 } 2015 } 2016 2017 #else 2018 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2019 static int 2020 decode_win_xor_valid(void) 2021 { 2022 2023 return (1); 2024 } 2025 2026 static void 2027 decode_win_xor_setup(u_long base) 2028 { 2029 } 2030 2031 static void 2032 decode_win_xor_dump(u_long base) 2033 { 2034 } 2035 #endif 2036 2037 /************************************************************************** 2038 * SATA windows routines 2039 **************************************************************************/ 2040 static void 2041 decode_win_sata_setup(u_long base) 2042 { 2043 uint32_t cr, br; 2044 int i, j; 2045 2046 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2047 return; 2048 2049 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2050 win_sata_cr_write(base, i, 0); 2051 win_sata_br_write(base, i, 0); 2052 } 2053 2054 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2055 if (ddr_is_active(i)) { 2056 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2057 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2058 br = ddr_base(i); 2059 2060 /* Use the first available SATA window */ 2061 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2062 if ((win_sata_cr_read(base, j) & 1) != 0) 2063 continue; 2064 2065 win_sata_br_write(base, j, br); 2066 win_sata_cr_write(base, j, cr); 2067 break; 2068 } 2069 } 2070 } 2071 2072 #ifdef SOC_MV_ARMADA38X 2073 /* 2074 * Configure AHCI decoding windows 2075 */ 2076 static void 2077 decode_win_ahci_setup(u_long base) 2078 { 2079 uint32_t br, cr, sz; 2080 int i, j; 2081 2082 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2083 win_sata_cr_write(base, i, 0); 2084 win_sata_br_write(base, i, 0); 2085 win_sata_sz_write(base, i, 0); 2086 } 2087 2088 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2089 if (ddr_is_active(i)) { 2090 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2091 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2092 IO_WIN_ENA_MASK; 2093 br = ddr_base(i); 2094 sz = (ddr_size(i) - 1) & 2095 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2096 2097 /* Use first available SATA window */ 2098 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2099 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2100 continue; 2101 2102 /* BASE is set to DRAM base (0x00000000) */ 2103 win_sata_br_write(base, j, br); 2104 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2105 win_sata_cr_write(base, j, cr); 2106 /* SIZE is set to 16MB - max value */ 2107 win_sata_sz_write(base, j, sz); 2108 break; 2109 } 2110 } 2111 } 2112 } 2113 2114 static void 2115 decode_win_ahci_dump(u_long base) 2116 { 2117 int i; 2118 2119 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2120 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2121 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2122 win_sata_sz_read(base,i)); 2123 } 2124 2125 #else 2126 /* 2127 * Provide dummy functions to satisfy the build 2128 * for SoC's not equipped with AHCI controller 2129 */ 2130 static void 2131 decode_win_ahci_setup(u_long base) 2132 { 2133 } 2134 2135 static void 2136 decode_win_ahci_dump(u_long base) 2137 { 2138 } 2139 #endif 2140 2141 static int 2142 decode_win_sata_valid(void) 2143 { 2144 uint32_t dev, rev; 2145 2146 soc_id(&dev, &rev); 2147 if (dev == MV_DEV_88F5281) 2148 return (1); 2149 2150 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2151 } 2152 2153 static void 2154 decode_win_sdhci_setup(u_long base) 2155 { 2156 uint32_t cr, br; 2157 int i, j; 2158 2159 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2160 win_sdhci_cr_write(base, i, 0); 2161 win_sdhci_br_write(base, i, 0); 2162 } 2163 2164 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2165 if (ddr_is_active(i)) { 2166 br = ddr_base(i); 2167 cr = (((ddr_size(i) - 1) & 2168 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2169 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2170 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2171 IO_WIN_ENA_MASK); 2172 2173 /* Use the first available SDHCI window */ 2174 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2175 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2176 continue; 2177 2178 win_sdhci_cr_write(base, j, cr); 2179 win_sdhci_br_write(base, j, br); 2180 break; 2181 } 2182 } 2183 } 2184 2185 static void 2186 decode_win_sdhci_dump(u_long base) 2187 { 2188 int i; 2189 2190 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2191 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2192 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2193 } 2194 2195 static int 2196 decode_win_sdhci_valid(void) 2197 { 2198 2199 #ifdef SOC_MV_ARMADA38X 2200 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2201 #endif 2202 2203 /* Satisfy platforms not equipped with this controller. */ 2204 return (1); 2205 } 2206 2207 /************************************************************************** 2208 * FDT parsing routines. 2209 **************************************************************************/ 2210 2211 static int 2212 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2213 int *tuplesize) 2214 { 2215 phandle_t node; 2216 pcell_t addr_cells, par_addr_cells, size_cells; 2217 int len, tuple_size, tuples_count; 2218 2219 node = OF_finddevice(nodename); 2220 if (node == -1) 2221 return (EINVAL); 2222 2223 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2224 return (ENXIO); 2225 2226 par_addr_cells = fdt_parent_addr_cells(node); 2227 if (par_addr_cells > 2) 2228 return (ERANGE); 2229 2230 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2231 size_cells); 2232 2233 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2234 len = OF_getprop(node, "ranges", buf, size); 2235 2236 /* 2237 * XXX this does not handle the empty 'ranges;' case, which is 2238 * legitimate and should be allowed. 2239 */ 2240 tuples_count = len / tuple_size; 2241 if (tuples_count <= 0) 2242 return (ERANGE); 2243 2244 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2245 return (ERANGE); 2246 2247 *tuples = tuples_count; 2248 *tuplesize = tuple_size; 2249 return (0); 2250 } 2251 2252 static int 2253 win_cpu_from_dt(void) 2254 { 2255 pcell_t ranges[48]; 2256 phandle_t node; 2257 int i, entry_size, err, t, tuple_size, tuples; 2258 u_long sram_base, sram_size; 2259 2260 t = 0; 2261 /* Retrieve 'ranges' property of '/localbus' node. */ 2262 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2263 &tuples, &tuple_size)) == 0) { 2264 /* 2265 * Fill CPU decode windows table. 2266 */ 2267 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2268 2269 entry_size = tuple_size / sizeof(pcell_t); 2270 cpu_wins_no = tuples; 2271 2272 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2273 cpu_win_tbl[t].target = 1; 2274 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2275 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2276 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2277 cpu_win_tbl[t].remap = ~0; 2278 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2279 "size = 0x%0x remap = 0x%0x\n", 2280 cpu_win_tbl[t].target, 2281 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2282 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2283 } 2284 } 2285 2286 /* 2287 * Retrieve CESA SRAM data. 2288 */ 2289 if ((node = OF_finddevice("sram")) != -1) 2290 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2291 goto moveon; 2292 2293 if ((node = OF_finddevice("/")) == 0) 2294 return (ENXIO); 2295 2296 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2297 /* SRAM block is not always present. */ 2298 return (0); 2299 moveon: 2300 sram_base = sram_size = 0; 2301 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2302 return (EINVAL); 2303 2304 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2305 #ifdef SOC_MV_ARMADA38X 2306 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2307 #else 2308 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2309 #endif 2310 cpu_win_tbl[t].base = sram_base; 2311 cpu_win_tbl[t].size = sram_size; 2312 cpu_win_tbl[t].remap = ~0; 2313 cpu_wins_no++; 2314 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2315 2316 /* Check if there is a second CESA node */ 2317 while ((node = OF_peer(node)) != 0) { 2318 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2319 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2320 return (EINVAL); 2321 break; 2322 } 2323 } 2324 2325 if (node == 0) 2326 return (0); 2327 2328 t++; 2329 if (t >= nitems(cpu_win_tbl)) { 2330 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2331 return (ENOMEM); 2332 } 2333 2334 /* Configure window for CESA1 */ 2335 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2336 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2337 cpu_win_tbl[t].base = sram_base; 2338 cpu_win_tbl[t].size = sram_size; 2339 cpu_win_tbl[t].remap = ~0; 2340 cpu_wins_no++; 2341 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2342 2343 return (0); 2344 } 2345 2346 static int 2347 fdt_win_setup(void) 2348 { 2349 phandle_t node, child, sb; 2350 struct soc_node_spec *soc_node; 2351 u_long size, base; 2352 int err, i; 2353 2354 sb = 0; 2355 node = OF_finddevice("/"); 2356 if (node == -1) 2357 panic("fdt_win_setup: no root node"); 2358 2359 /* 2360 * Traverse through all children of root and simple-bus nodes. 2361 * For each found device retrieve decode windows data (if applicable). 2362 */ 2363 child = OF_child(node); 2364 while (child != 0) { 2365 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2366 2367 soc_node = &soc_nodes[i]; 2368 2369 /* Setup only for enabled devices */ 2370 if (ofw_bus_node_status_okay(child) == 0) 2371 continue; 2372 2373 if (!ofw_bus_node_is_compatible(child,soc_node->compat)) 2374 continue; 2375 2376 err = fdt_regsize(child, &base, &size); 2377 if (err != 0) 2378 return (err); 2379 2380 base = (base & 0x000fffff) | fdt_immr_va; 2381 if (soc_node->decode_handler != NULL) 2382 soc_node->decode_handler(base); 2383 else 2384 return (ENXIO); 2385 2386 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2387 soc_node->dump_handler(base); 2388 } 2389 2390 /* 2391 * Once done with root-level children let's move down to 2392 * simple-bus and its children. 2393 */ 2394 child = OF_peer(child); 2395 if ((child == 0) && (node == OF_finddevice("/"))) { 2396 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2397 if (node == 0) 2398 return (ENXIO); 2399 child = OF_child(node); 2400 } 2401 /* 2402 * Next, move one more level down to internal-regs node (if 2403 * it is present) and its children. This node also have 2404 * "simple-bus" compatible. 2405 */ 2406 if ((child == 0) && (node == sb)) { 2407 node = fdt_find_compatible(node, "simple-bus", 0); 2408 if (node == 0) 2409 return (0); 2410 child = OF_child(node); 2411 } 2412 } 2413 2414 return (0); 2415 } 2416 2417 static void 2418 fdt_fixup_busfreq(phandle_t root) 2419 { 2420 phandle_t sb; 2421 pcell_t freq; 2422 2423 freq = cpu_to_fdt32(get_tclk()); 2424 2425 /* 2426 * Fix bus speed in cpu node 2427 */ 2428 if ((sb = OF_finddevice("cpu")) != 0) 2429 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2430 OF_setprop(sb, "bus-frequency", (void *)&freq, 2431 sizeof(freq)); 2432 2433 /* 2434 * This fixup sets the simple-bus bus-frequency property. 2435 */ 2436 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2437 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2438 } 2439 2440 static void 2441 fdt_fixup_ranges(phandle_t root) 2442 { 2443 phandle_t node; 2444 pcell_t par_addr_cells, addr_cells, size_cells; 2445 pcell_t ranges[3], reg[2], *rangesptr; 2446 int len, tuple_size, tuples_count; 2447 uint32_t base; 2448 2449 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2450 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2451 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2452 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2453 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2454 addr_cells + size_cells); 2455 len = OF_getprop(node, "ranges", ranges, 2456 sizeof(ranges)); 2457 tuples_count = len / tuple_size; 2458 /* Unexpected settings are not supported */ 2459 if (tuples_count != 1) 2460 goto fixup_failed; 2461 2462 rangesptr = &ranges[0]; 2463 rangesptr += par_addr_cells; 2464 base = fdt_data_get((void *)rangesptr, addr_cells); 2465 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2466 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2467 sizeof(ranges)) < 0) 2468 goto fixup_failed; 2469 } 2470 } 2471 2472 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2473 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2474 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2475 &size_cells) == 0) { 2476 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2477 size_cells); 2478 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2479 tuples_count = len / tuple_size; 2480 /* Unexpected settings are not supported */ 2481 if (tuples_count != 1) 2482 goto fixup_failed; 2483 2484 base = fdt_data_get((void *)®[0], par_addr_cells); 2485 base &= ~0xFF000000; 2486 base |= fdt_immr_pa; 2487 reg[0] = cpu_to_fdt32(base); 2488 if (OF_setprop(node, "reg", (void *)®[0], 2489 sizeof(reg)) < 0) 2490 goto fixup_failed; 2491 } 2492 } 2493 /* Fix-up succeeded. May return and continue */ 2494 return; 2495 2496 fixup_failed: 2497 while (1) { 2498 /* 2499 * In case of any error while fixing ranges just hang. 2500 * 1. No message can be displayed yet since console 2501 * is not initialized. 2502 * 2. Going further will cause failure on bus_space_map() 2503 * relying on the wrong ranges or data abort when 2504 * accessing PCIe registers. 2505 */ 2506 } 2507 } 2508 2509 struct fdt_fixup_entry fdt_fixup_table[] = { 2510 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2511 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2512 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2513 { NULL, NULL } 2514 }; 2515 2516 #ifndef INTRNG 2517 static int 2518 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2519 int *pol) 2520 { 2521 2522 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2523 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2524 return (ENXIO); 2525 2526 *interrupt = fdt32_to_cpu(intr[0]); 2527 *trig = INTR_TRIGGER_CONFORM; 2528 *pol = INTR_POLARITY_CONFORM; 2529 2530 return (0); 2531 } 2532 2533 fdt_pic_decode_t fdt_pic_table[] = { 2534 #ifdef SOC_MV_ARMADA38X 2535 &gic_decode_fdt, 2536 #endif 2537 &fdt_pic_decode_ic, 2538 NULL 2539 }; 2540 #endif 2541 2542 uint64_t 2543 get_sar_value(void) 2544 { 2545 uint32_t sar_low, sar_high; 2546 2547 #if defined(SOC_MV_ARMADAXP) 2548 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2549 SAMPLE_AT_RESET_HI); 2550 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2551 SAMPLE_AT_RESET_LO); 2552 #elif defined(SOC_MV_ARMADA38X) 2553 sar_high = 0; 2554 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2555 SAMPLE_AT_RESET); 2556 #else 2557 /* 2558 * TODO: Add getting proper values for other SoC configurations 2559 */ 2560 sar_high = 0; 2561 sar_low = 0; 2562 #endif 2563 2564 return (((uint64_t)sar_high << 32) | sar_low); 2565 } 2566