1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 46 #include <machine/bus.h> 47 #include <machine/fdt.h> 48 #include <machine/vmparam.h> 49 #include <machine/intr.h> 50 51 #include <arm/mv/mvreg.h> 52 #include <arm/mv/mvvar.h> 53 #include <arm/mv/mvwin.h> 54 55 56 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 57 58 #define IDMA_DEBUG 59 #undef IDMA_DEBUG 60 61 #define MAX_CPU_WIN 5 62 63 #ifdef DEBUG 64 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 65 printf(fmt,##args); } while (0) 66 #else 67 #define debugf(fmt, args...) 68 #endif 69 70 #ifdef DEBUG 71 #define MV_DUMP_WIN 1 72 #else 73 #define MV_DUMP_WIN 0 74 #endif 75 76 static int win_eth_can_remap(int i); 77 78 #ifndef SOC_MV_FREY 79 static int decode_win_cpu_valid(void); 80 #endif 81 static int decode_win_usb_valid(void); 82 static int decode_win_eth_valid(void); 83 static int decode_win_pcie_valid(void); 84 static int decode_win_sata_valid(void); 85 86 static int decode_win_idma_valid(void); 87 static int decode_win_xor_valid(void); 88 89 #ifndef SOC_MV_FREY 90 static void decode_win_cpu_setup(void); 91 #endif 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_usb_setup(u_long); 96 static void decode_win_eth_setup(u_long); 97 static void decode_win_sata_setup(u_long); 98 99 static void decode_win_idma_setup(u_long); 100 static void decode_win_xor_setup(u_long); 101 102 static void decode_win_usb_dump(u_long); 103 static void decode_win_eth_dump(u_long base); 104 static void decode_win_idma_dump(u_long base); 105 static void decode_win_xor_dump(u_long base); 106 107 static int fdt_get_ranges(const char *, void *, int, int *, int *); 108 #ifdef SOC_MV_ARMADA38X 109 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 110 int *trig, int *pol); 111 #endif 112 113 static int win_cpu_from_dt(void); 114 static int fdt_win_setup(void); 115 116 static uint32_t dev_mask = 0; 117 static int cpu_wins_no = 0; 118 static int eth_port = 0; 119 static int usb_port = 0; 120 121 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 122 123 const struct decode_win *cpu_wins = cpu_win_tbl; 124 125 typedef void (*decode_win_setup_t)(u_long); 126 typedef void (*dump_win_t)(u_long); 127 128 struct soc_node_spec { 129 const char *compat; 130 decode_win_setup_t decode_handler; 131 dump_win_t dump_handler; 132 }; 133 134 static struct soc_node_spec soc_nodes[] = { 135 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 136 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 137 { "mrvl,sata", &decode_win_sata_setup, NULL }, 138 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 139 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 140 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 141 { NULL, NULL, NULL }, 142 }; 143 144 struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 145 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 146 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 147 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 148 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 149 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 150 { "mrvl,xor", CPU_PM_CTRL_XOR }, 151 { "mrvl,sata", CPU_PM_CTRL_SATA }, 152 153 { NULL, 0 } 154 }; 155 156 static __inline int 157 pm_is_disabled(uint32_t mask) 158 { 159 #if defined(SOC_MV_KIRKWOOD) 160 return (soc_power_ctrl_get(mask) == mask); 161 #else 162 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 163 #endif 164 } 165 166 /* 167 * Disable device using power management register. 168 * 1 - Device Power On 169 * 0 - Device Power Off 170 * Mask can be set in loader. 171 * EXAMPLE: 172 * loader> set hw.pm-disable-mask=0x2 173 * 174 * Common mask: 175 * |-------------------------------| 176 * | Device | Kirkwood | Discovery | 177 * |-------------------------------| 178 * | USB0 | 0x00008 | 0x020000 | 179 * |-------------------------------| 180 * | USB1 | - | 0x040000 | 181 * |-------------------------------| 182 * | USB2 | - | 0x080000 | 183 * |-------------------------------| 184 * | GE0 | 0x00001 | 0x000002 | 185 * |-------------------------------| 186 * | GE1 | - | 0x000004 | 187 * |-------------------------------| 188 * | IDMA | - | 0x100000 | 189 * |-------------------------------| 190 * | XOR | 0x10000 | 0x200000 | 191 * |-------------------------------| 192 * | CESA | 0x20000 | 0x400000 | 193 * |-------------------------------| 194 * | SATA | 0x04000 | 0x004000 | 195 * --------------------------------| 196 * This feature can be used only on Kirkwood and Discovery 197 * machines. 198 */ 199 static __inline void 200 pm_disable_device(int mask) 201 { 202 #ifdef DIAGNOSTIC 203 uint32_t reg; 204 205 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 206 printf("Power Management Register: 0%x\n", reg); 207 208 reg &= ~mask; 209 soc_power_ctrl_set(reg); 210 printf("Device %x is disabled\n", mask); 211 212 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 213 printf("Power Management Register: 0%x\n", reg); 214 #endif 215 } 216 217 int 218 fdt_pm(phandle_t node) 219 { 220 uint32_t cpu_pm_ctrl; 221 int i, ena, compat; 222 223 ena = 1; 224 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 225 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 226 if (dev_mask & (1 << i)) 227 continue; 228 229 compat = fdt_is_compatible(node, fdt_pm_mask_table[i].compat); 230 #if defined(SOC_MV_KIRKWOOD) 231 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 232 dev_mask |= (1 << i); 233 ena = 0; 234 break; 235 } else if (compat) { 236 dev_mask |= (1 << i); 237 break; 238 } 239 #else 240 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 241 dev_mask |= (1 << i); 242 ena = 0; 243 break; 244 } else if (compat) { 245 dev_mask |= (1 << i); 246 break; 247 } 248 #endif 249 } 250 251 return (ena); 252 } 253 254 uint32_t 255 read_cpu_ctrl(uint32_t reg) 256 { 257 258 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 259 } 260 261 void 262 write_cpu_ctrl(uint32_t reg, uint32_t val) 263 { 264 265 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 266 } 267 268 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 269 uint32_t 270 read_cpu_mp_clocks(uint32_t reg) 271 { 272 273 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 274 } 275 276 void 277 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 278 { 279 280 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 281 } 282 283 uint32_t 284 read_cpu_misc(uint32_t reg) 285 { 286 287 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 288 } 289 290 void 291 write_cpu_misc(uint32_t reg, uint32_t val) 292 { 293 294 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 295 } 296 #endif 297 298 void 299 cpu_reset(void) 300 { 301 302 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 303 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 304 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 305 #else 306 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 307 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 308 #endif 309 while (1); 310 } 311 312 uint32_t 313 cpu_extra_feat(void) 314 { 315 uint32_t dev, rev; 316 uint32_t ef = 0; 317 318 soc_id(&dev, &rev); 319 320 switch (dev) { 321 case MV_DEV_88F6281: 322 case MV_DEV_88F6282: 323 case MV_DEV_88RC8180: 324 case MV_DEV_MV78100_Z0: 325 case MV_DEV_MV78100: 326 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 327 break; 328 case MV_DEV_88F5182: 329 case MV_DEV_88F5281: 330 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 331 break; 332 default: 333 if (bootverbose) 334 printf("This ARM Core does not support any extra features\n"); 335 } 336 337 return (ef); 338 } 339 340 /* 341 * Get the power status of device. This feature is only supported on 342 * Kirkwood and Discovery SoCs. 343 */ 344 uint32_t 345 soc_power_ctrl_get(uint32_t mask) 346 { 347 348 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY) 349 if (mask != CPU_PM_CTRL_NONE) 350 mask &= read_cpu_ctrl(CPU_PM_CTRL); 351 352 return (mask); 353 #else 354 return (mask); 355 #endif 356 } 357 358 /* 359 * Set the power status of device. This feature is only supported on 360 * Kirkwood and Discovery SoCs. 361 */ 362 void 363 soc_power_ctrl_set(uint32_t mask) 364 { 365 366 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) 367 if (mask != CPU_PM_CTRL_NONE) 368 write_cpu_ctrl(CPU_PM_CTRL, mask); 369 #endif 370 } 371 372 void 373 soc_id(uint32_t *dev, uint32_t *rev) 374 { 375 376 /* 377 * Notice: system identifiers are available in the registers range of 378 * PCIE controller, so using this function is only allowed (and 379 * possible) after the internal registers range has been mapped in via 380 * arm_devmap_bootstrap(). 381 */ 382 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 383 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 384 } 385 386 static void 387 soc_identify(void) 388 { 389 uint32_t d, r, size, mode; 390 const char *dev; 391 const char *rev; 392 393 soc_id(&d, &r); 394 395 printf("SOC: "); 396 if (bootverbose) 397 printf("(0x%4x:0x%02x) ", d, r); 398 399 rev = ""; 400 switch (d) { 401 case MV_DEV_88F5181: 402 dev = "Marvell 88F5181"; 403 if (r == 3) 404 rev = "B1"; 405 break; 406 case MV_DEV_88F5182: 407 dev = "Marvell 88F5182"; 408 if (r == 2) 409 rev = "A2"; 410 break; 411 case MV_DEV_88F5281: 412 dev = "Marvell 88F5281"; 413 if (r == 4) 414 rev = "D0"; 415 else if (r == 5) 416 rev = "D1"; 417 else if (r == 6) 418 rev = "D2"; 419 break; 420 case MV_DEV_88F6281: 421 dev = "Marvell 88F6281"; 422 if (r == 0) 423 rev = "Z0"; 424 else if (r == 2) 425 rev = "A0"; 426 else if (r == 3) 427 rev = "A1"; 428 break; 429 case MV_DEV_88RC8180: 430 dev = "Marvell 88RC8180"; 431 break; 432 case MV_DEV_88RC9480: 433 dev = "Marvell 88RC9480"; 434 break; 435 case MV_DEV_88RC9580: 436 dev = "Marvell 88RC9580"; 437 break; 438 case MV_DEV_88F6781: 439 dev = "Marvell 88F6781"; 440 if (r == 2) 441 rev = "Y0"; 442 break; 443 case MV_DEV_88F6282: 444 dev = "Marvell 88F6282"; 445 if (r == 0) 446 rev = "A0"; 447 else if (r == 1) 448 rev = "A1"; 449 break; 450 case MV_DEV_88F6828: 451 dev = "Marvell 88F6828"; 452 break; 453 case MV_DEV_88F6820: 454 dev = "Marvell 88F6820"; 455 break; 456 case MV_DEV_88F6810: 457 dev = "Marvell 88F6810"; 458 break; 459 case MV_DEV_MV78100_Z0: 460 dev = "Marvell MV78100 Z0"; 461 break; 462 case MV_DEV_MV78100: 463 dev = "Marvell MV78100"; 464 break; 465 case MV_DEV_MV78160: 466 dev = "Marvell MV78160"; 467 break; 468 case MV_DEV_MV78260: 469 dev = "Marvell MV78260"; 470 break; 471 case MV_DEV_MV78460: 472 dev = "Marvell MV78460"; 473 break; 474 default: 475 dev = "UNKNOWN"; 476 break; 477 } 478 479 printf("%s", dev); 480 if (*rev != '\0') 481 printf(" rev %s", rev); 482 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 483 484 mode = read_cpu_ctrl(CPU_CONFIG); 485 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 486 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 487 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 488 489 switch (d) { 490 case MV_DEV_88F6281: 491 case MV_DEV_88F6282: 492 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 493 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 494 mode ? "write-through" : "write-back"); 495 break; 496 case MV_DEV_MV78100: 497 mode = read_cpu_ctrl(CPU_CONTROL); 498 size = mode & CPU_CONTROL_L2_SIZE; 499 mode = mode & CPU_CONTROL_L2_MODE; 500 printf(" %s set-associative %s unified L2 cache\n", 501 size ? "256KB 4-way" : "512KB 8-way", 502 mode ? "write-through" : "write-back"); 503 break; 504 default: 505 break; 506 } 507 } 508 509 static void 510 platform_identify(void *dummy) 511 { 512 513 soc_identify(); 514 515 /* 516 * XXX Board identification e.g. read out from FPGA or similar should 517 * go here 518 */ 519 } 520 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 521 NULL); 522 523 #ifdef KDB 524 static void 525 mv_enter_debugger(void *dummy) 526 { 527 528 if (boothowto & RB_KDB) 529 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 530 } 531 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 532 #endif 533 534 int 535 soc_decode_win(void) 536 { 537 uint32_t dev, rev; 538 int mask, err; 539 540 mask = 0; 541 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 542 543 if (mask != 0) 544 pm_disable_device(mask); 545 546 /* Retrieve data about physical addresses from device tree. */ 547 if ((err = win_cpu_from_dt()) != 0) 548 return (err); 549 550 /* Retrieve our ID: some windows facilities vary between SoC models */ 551 soc_id(&dev, &rev); 552 553 #ifdef SOC_MV_ARMADAXP 554 if ((err = decode_win_sdram_fixup()) != 0) 555 return(err); 556 #endif 557 558 #ifndef SOC_MV_FREY 559 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 560 !decode_win_eth_valid() || !decode_win_idma_valid() || 561 !decode_win_pcie_valid() || !decode_win_sata_valid() || 562 !decode_win_xor_valid()) 563 return (EINVAL); 564 565 decode_win_cpu_setup(); 566 #else 567 if (!decode_win_usb_valid() || 568 !decode_win_eth_valid() || !decode_win_idma_valid() || 569 !decode_win_pcie_valid() || !decode_win_sata_valid() || 570 !decode_win_xor_valid()) 571 return (EINVAL); 572 #endif 573 if (MV_DUMP_WIN) 574 soc_dump_decode_win(); 575 576 eth_port = 0; 577 usb_port = 0; 578 if ((err = fdt_win_setup()) != 0) 579 return (err); 580 581 return (0); 582 } 583 584 /************************************************************************** 585 * Decode windows registers accessors 586 **************************************************************************/ 587 #if !defined(SOC_MV_FREY) 588 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 589 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 590 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 591 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 592 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 593 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 594 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 595 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 596 #endif 597 598 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 599 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 600 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 601 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 602 603 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 604 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 605 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 606 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 607 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 608 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 609 610 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 611 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 612 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 613 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 614 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 615 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 616 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 617 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 618 619 WIN_REG_BASE_RD(win_eth, bare, 0x290) 620 WIN_REG_BASE_RD(win_eth, epap, 0x294) 621 WIN_REG_BASE_WR(win_eth, bare, 0x290) 622 WIN_REG_BASE_WR(win_eth, epap, 0x294) 623 624 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 625 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 626 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 627 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 628 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 629 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 630 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 631 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 632 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 633 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 634 635 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 636 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 637 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 638 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 639 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 640 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 641 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 642 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 643 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 644 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 645 646 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 647 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 648 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 649 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 650 #ifndef SOC_MV_DOVE 651 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 652 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 653 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 654 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 655 #else 656 /* 657 * On 88F6781 (Dove) SoC DDR Controller is accessed through 658 * single MBUS <-> AXI bridge. In this case we provide emulated 659 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 660 * with common decoding windows setup code. 661 */ 662 663 static inline uint32_t ddr_br_read(int i) 664 { 665 uint32_t mmap; 666 667 /* Read Memory Address Map Register for CS i */ 668 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 669 670 /* Return CS i base address */ 671 return (mmap & 0xFF000000); 672 } 673 674 static inline uint32_t ddr_sz_read(int i) 675 { 676 uint32_t mmap, size; 677 678 /* Read Memory Address Map Register for CS i */ 679 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 680 681 /* Extract size of CS space in 64kB units */ 682 size = (1 << ((mmap >> 16) & 0x0F)); 683 684 /* Return CS size and enable/disable status */ 685 return (((size - 1) << 16) | (mmap & 0x01)); 686 } 687 #endif 688 689 #if !defined(SOC_MV_FREY) 690 /************************************************************************** 691 * Decode windows helper routines 692 **************************************************************************/ 693 void 694 soc_dump_decode_win(void) 695 { 696 uint32_t dev, rev; 697 int i; 698 699 soc_id(&dev, &rev); 700 701 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 702 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 703 win_cpu_cr_read(i), 704 win_cpu_br_read(i)); 705 706 if (win_cpu_can_remap(i)) 707 printf(", rl 0x%08x, rh 0x%08x", 708 win_cpu_remap_l_read(i), 709 win_cpu_remap_h_read(i)); 710 711 printf("\n"); 712 } 713 printf("Internal regs base: 0x%08x\n", 714 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 715 716 for (i = 0; i < MV_WIN_DDR_MAX; i++) 717 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 718 ddr_br_read(i), ddr_sz_read(i)); 719 } 720 721 /************************************************************************** 722 * CPU windows routines 723 **************************************************************************/ 724 int 725 win_cpu_can_remap(int i) 726 { 727 uint32_t dev, rev; 728 729 soc_id(&dev, &rev); 730 731 /* Depending on the SoC certain windows have remap capability */ 732 if ((dev == MV_DEV_88F5182 && i < 2) || 733 (dev == MV_DEV_88F5281 && i < 4) || 734 (dev == MV_DEV_88F6281 && i < 4) || 735 (dev == MV_DEV_88F6282 && i < 4) || 736 (dev == MV_DEV_88F6828 && i < 20) || 737 (dev == MV_DEV_88F6820 && i < 20) || 738 (dev == MV_DEV_88F6810 && i < 20) || 739 (dev == MV_DEV_88RC8180 && i < 2) || 740 (dev == MV_DEV_88F6781 && i < 4) || 741 (dev == MV_DEV_MV78100_Z0 && i < 8) || 742 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 743 return (1); 744 745 return (0); 746 } 747 748 /* XXX This should check for overlapping remap fields too.. */ 749 int 750 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 751 { 752 const struct decode_win *tab; 753 int i; 754 755 tab = wintab; 756 757 for (i = 0; i < win_no; i++, tab++) { 758 if (i == win) 759 /* Skip self */ 760 continue; 761 762 if ((tab->base + tab->size - 1) < (wintab + win)->base) 763 continue; 764 765 else if (((wintab + win)->base + (wintab + win)->size - 1) < 766 tab->base) 767 continue; 768 else 769 return (i); 770 } 771 772 return (-1); 773 } 774 775 static int 776 decode_win_cpu_valid(void) 777 { 778 int i, j, rv; 779 uint32_t b, e, s; 780 781 if (cpu_wins_no > MV_WIN_CPU_MAX) { 782 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 783 return (0); 784 } 785 786 rv = 1; 787 for (i = 0; i < cpu_wins_no; i++) { 788 789 if (cpu_wins[i].target == 0) { 790 printf("CPU window#%d: DDR target window is not " 791 "supposed to be reprogrammed!\n", i); 792 rv = 0; 793 } 794 795 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 796 printf("CPU window#%d: not capable of remapping, but " 797 "val 0x%08x defined\n", i, cpu_wins[i].remap); 798 rv = 0; 799 } 800 801 s = cpu_wins[i].size; 802 b = cpu_wins[i].base; 803 e = b + s - 1; 804 if (s > (0xFFFFFFFF - b + 1)) { 805 /* 806 * XXX this boundary check should account for 64bit 807 * and remapping.. 808 */ 809 printf("CPU window#%d: no space for size 0x%08x at " 810 "0x%08x\n", i, s, b); 811 rv = 0; 812 continue; 813 } 814 815 if (b != (b & ~(s - 1))) { 816 printf("CPU window#%d: address 0x%08x is not aligned " 817 "to 0x%08x\n", i, b, s); 818 rv = 0; 819 continue; 820 } 821 822 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 823 if (j >= 0) { 824 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 825 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 826 cpu_wins[j].base, 827 cpu_wins[j].base + cpu_wins[j].size - 1); 828 rv = 0; 829 } 830 } 831 832 return (rv); 833 } 834 835 int 836 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 837 vm_paddr_t remap) 838 { 839 uint32_t br, cr; 840 int win, i; 841 842 if (remap == ~0) { 843 win = MV_WIN_CPU_MAX - 1; 844 i = -1; 845 } else { 846 win = 0; 847 i = 1; 848 } 849 850 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 851 cr = win_cpu_cr_read(win); 852 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 853 break; 854 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 855 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 856 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 857 (target << MV_WIN_CPU_TARGET_SHIFT))) 858 break; 859 win += i; 860 } 861 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 862 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 863 return (-1); 864 865 br = base & 0xffff0000; 866 win_cpu_br_write(win, br); 867 868 if (win_cpu_can_remap(win)) { 869 if (remap != ~0) { 870 win_cpu_remap_l_write(win, remap & 0xffff0000); 871 win_cpu_remap_h_write(win, 0); 872 } else { 873 /* 874 * Remap function is not used for a given window 875 * (capable of remapping) - set remap field with the 876 * same value as base. 877 */ 878 win_cpu_remap_l_write(win, base & 0xffff0000); 879 win_cpu_remap_h_write(win, 0); 880 } 881 } 882 883 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 884 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 885 win_cpu_cr_write(win, cr); 886 887 return (0); 888 } 889 890 static void 891 decode_win_cpu_setup(void) 892 { 893 int i; 894 895 /* Disable all CPU windows */ 896 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 897 win_cpu_cr_write(i, 0); 898 win_cpu_br_write(i, 0); 899 if (win_cpu_can_remap(i)) { 900 win_cpu_remap_l_write(i, 0); 901 win_cpu_remap_h_write(i, 0); 902 } 903 } 904 905 for (i = 0; i < cpu_wins_no; i++) 906 if (cpu_wins[i].target > 0) 907 decode_win_cpu_set(cpu_wins[i].target, 908 cpu_wins[i].attr, cpu_wins[i].base, 909 cpu_wins[i].size, cpu_wins[i].remap); 910 911 } 912 #endif 913 914 #ifdef SOC_MV_ARMADAXP 915 static int 916 decode_win_sdram_fixup(void) 917 { 918 struct mem_region mr[FDT_MEM_REGIONS]; 919 uint8_t window_valid[MV_WIN_DDR_MAX]; 920 int mr_cnt, err, i, j; 921 u_long memsize; 922 uint32_t valid_win_num = 0; 923 924 /* Grab physical memory regions information from device tree. */ 925 err = fdt_get_mem_regions(mr, &mr_cnt, &memsize); 926 if (err != 0) 927 return (err); 928 929 for (i = 0; i < MV_WIN_DDR_MAX; i++) 930 window_valid[i] = 0; 931 932 /* Try to match entries from device tree with settings from u-boot */ 933 for (i = 0; i < mr_cnt; i++) { 934 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 935 if (ddr_is_active(j) && 936 (ddr_base(j) == mr[i].mr_start) && 937 (ddr_size(j) == mr[i].mr_size)) { 938 window_valid[j] = 1; 939 valid_win_num++; 940 } 941 } 942 } 943 944 if (mr_cnt != valid_win_num) 945 return (EINVAL); 946 947 /* Destroy windows without corresponding device tree entry */ 948 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 949 if (ddr_is_active(j) && (window_valid[j] != 1)) { 950 printf("Disabling SDRAM decoding window: %d\n", j); 951 ddr_disable(j); 952 } 953 } 954 955 return (0); 956 } 957 #endif 958 /* 959 * Check if we're able to cover all active DDR banks. 960 */ 961 static int 962 decode_win_can_cover_ddr(int max) 963 { 964 int i, c; 965 966 c = 0; 967 for (i = 0; i < MV_WIN_DDR_MAX; i++) 968 if (ddr_is_active(i)) 969 c++; 970 971 if (c > max) { 972 printf("Unable to cover all active DDR banks: " 973 "%d, available windows: %d\n", c, max); 974 return (0); 975 } 976 977 return (1); 978 } 979 980 /************************************************************************** 981 * DDR windows routines 982 **************************************************************************/ 983 int 984 ddr_is_active(int i) 985 { 986 987 if (ddr_sz_read(i) & 0x1) 988 return (1); 989 990 return (0); 991 } 992 993 void 994 ddr_disable(int i) 995 { 996 997 ddr_sz_write(i, 0); 998 ddr_br_write(i, 0); 999 } 1000 1001 uint32_t 1002 ddr_base(int i) 1003 { 1004 1005 return (ddr_br_read(i) & 0xff000000); 1006 } 1007 1008 uint32_t 1009 ddr_size(int i) 1010 { 1011 1012 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1013 } 1014 1015 uint32_t 1016 ddr_attr(int i) 1017 { 1018 uint32_t dev, rev; 1019 1020 soc_id(&dev, &rev); 1021 if (dev == MV_DEV_88RC8180) 1022 return ((ddr_sz_read(i) & 0xf0) >> 4); 1023 if (dev == MV_DEV_88F6781) 1024 return (0); 1025 1026 return (i == 0 ? 0xe : 1027 (i == 1 ? 0xd : 1028 (i == 2 ? 0xb : 1029 (i == 3 ? 0x7 : 0xff)))); 1030 } 1031 1032 uint32_t 1033 ddr_target(int i) 1034 { 1035 uint32_t dev, rev; 1036 1037 soc_id(&dev, &rev); 1038 if (dev == MV_DEV_88RC8180) { 1039 i = (ddr_sz_read(i) & 0xf0) >> 4; 1040 return (i == 0xe ? 0xc : 1041 (i == 0xd ? 0xd : 1042 (i == 0xb ? 0xe : 1043 (i == 0x7 ? 0xf : 0xc)))); 1044 } 1045 1046 /* 1047 * On SOCs other than 88RC8180 Mbus unit ID for 1048 * DDR SDRAM controller is always 0x0. 1049 */ 1050 return (0); 1051 } 1052 1053 /************************************************************************** 1054 * USB windows routines 1055 **************************************************************************/ 1056 static int 1057 decode_win_usb_valid(void) 1058 { 1059 1060 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1061 } 1062 1063 static void 1064 decode_win_usb_dump(u_long base) 1065 { 1066 int i; 1067 1068 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1069 return; 1070 1071 for (i = 0; i < MV_WIN_USB_MAX; i++) 1072 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1073 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1074 } 1075 1076 /* 1077 * Set USB decode windows. 1078 */ 1079 static void 1080 decode_win_usb_setup(u_long base) 1081 { 1082 uint32_t br, cr; 1083 int i, j; 1084 1085 1086 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1087 return; 1088 1089 usb_port++; 1090 1091 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1092 win_usb_cr_write(base, i, 0); 1093 win_usb_br_write(base, i, 0); 1094 } 1095 1096 /* Only access to active DRAM banks is required */ 1097 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1098 if (ddr_is_active(i)) { 1099 br = ddr_base(i); 1100 /* 1101 * XXX for 6281 we should handle Mbus write 1102 * burst limit field in the ctrl reg 1103 */ 1104 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1105 (ddr_attr(i) << 8) | 1106 (ddr_target(i) << 4) | 1); 1107 1108 /* Set the first free USB window */ 1109 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1110 if (win_usb_cr_read(base, j) & 0x1) 1111 continue; 1112 1113 win_usb_br_write(base, j, br); 1114 win_usb_cr_write(base, j, cr); 1115 break; 1116 } 1117 } 1118 } 1119 } 1120 1121 /************************************************************************** 1122 * ETH windows routines 1123 **************************************************************************/ 1124 1125 static int 1126 win_eth_can_remap(int i) 1127 { 1128 1129 /* ETH encode windows 0-3 have remap capability */ 1130 if (i < 4) 1131 return (1); 1132 1133 return (0); 1134 } 1135 1136 static int 1137 eth_bare_read(uint32_t base, int i) 1138 { 1139 uint32_t v; 1140 1141 v = win_eth_bare_read(base); 1142 v &= (1 << i); 1143 1144 return (v >> i); 1145 } 1146 1147 static void 1148 eth_bare_write(uint32_t base, int i, int val) 1149 { 1150 uint32_t v; 1151 1152 v = win_eth_bare_read(base); 1153 v &= ~(1 << i); 1154 v |= (val << i); 1155 win_eth_bare_write(base, v); 1156 } 1157 1158 static void 1159 eth_epap_write(uint32_t base, int i, int val) 1160 { 1161 uint32_t v; 1162 1163 v = win_eth_epap_read(base); 1164 v &= ~(0x3 << (i * 2)); 1165 v |= (val << (i * 2)); 1166 win_eth_epap_write(base, v); 1167 } 1168 1169 static void 1170 decode_win_eth_dump(u_long base) 1171 { 1172 int i; 1173 1174 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1175 return; 1176 1177 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1178 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1179 win_eth_br_read(base, i), 1180 win_eth_sz_read(base, i)); 1181 1182 if (win_eth_can_remap(i)) 1183 printf(", ha 0x%08x", 1184 win_eth_har_read(base, i)); 1185 1186 printf("\n"); 1187 } 1188 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1189 win_eth_bare_read(base), 1190 win_eth_epap_read(base)); 1191 } 1192 1193 #if defined(SOC_MV_LOKIPLUS) 1194 #define MV_WIN_ETH_DDR_TRGT(n) 0 1195 #else 1196 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1197 #endif 1198 1199 static void 1200 decode_win_eth_setup(u_long base) 1201 { 1202 uint32_t br, sz; 1203 int i, j; 1204 1205 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1206 return; 1207 1208 eth_port++; 1209 1210 /* Disable, clear and revoke protection for all ETH windows */ 1211 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1212 1213 eth_bare_write(base, i, 1); 1214 eth_epap_write(base, i, 0); 1215 win_eth_br_write(base, i, 0); 1216 win_eth_sz_write(base, i, 0); 1217 if (win_eth_can_remap(i)) 1218 win_eth_har_write(base, i, 0); 1219 } 1220 1221 /* Only access to active DRAM banks is required */ 1222 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1223 if (ddr_is_active(i)) { 1224 1225 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1226 sz = ((ddr_size(i) - 1) & 0xffff0000); 1227 1228 /* Set the first free ETH window */ 1229 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1230 if (eth_bare_read(base, j) == 0) 1231 continue; 1232 1233 win_eth_br_write(base, j, br); 1234 win_eth_sz_write(base, j, sz); 1235 1236 /* XXX remapping ETH windows not supported */ 1237 1238 /* Set protection RW */ 1239 eth_epap_write(base, j, 0x3); 1240 1241 /* Enable window */ 1242 eth_bare_write(base, j, 0); 1243 break; 1244 } 1245 } 1246 } 1247 1248 static int 1249 decode_win_eth_valid(void) 1250 { 1251 1252 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1253 } 1254 1255 /************************************************************************** 1256 * PCIE windows routines 1257 **************************************************************************/ 1258 1259 void 1260 decode_win_pcie_setup(u_long base) 1261 { 1262 uint32_t size = 0, ddrbase = ~0; 1263 uint32_t cr, br; 1264 int i, j; 1265 1266 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1267 pcie_bar_br_write(base, i, 1268 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1269 if (i < 3) 1270 pcie_bar_brh_write(base, i, 0); 1271 if (i > 0) 1272 pcie_bar_cr_write(base, i, 0); 1273 } 1274 1275 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1276 win_pcie_cr_write(base, i, 0); 1277 win_pcie_br_write(base, i, 0); 1278 win_pcie_remap_write(base, i, 0); 1279 } 1280 1281 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1282 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1283 & MV_PCIE_ROOT_CMPLX) == 0) { 1284 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1285 return; 1286 } 1287 1288 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1289 if (ddr_is_active(i)) { 1290 /* Map DDR to BAR 1 */ 1291 cr = (ddr_size(i) - 1) & 0xffff0000; 1292 size += ddr_size(i) & 0xffff0000; 1293 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1294 br = ddr_base(i); 1295 if (br < ddrbase) 1296 ddrbase = br; 1297 1298 /* Use the first available PCIE window */ 1299 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1300 if (win_pcie_cr_read(base, j) != 0) 1301 continue; 1302 1303 win_pcie_br_write(base, j, br); 1304 win_pcie_cr_write(base, j, cr); 1305 break; 1306 } 1307 } 1308 } 1309 1310 /* 1311 * Upper 16 bits in BAR register is interpreted as BAR size 1312 * (in 64 kB units) plus 64kB, so substract 0x10000 1313 * form value passed to register to get correct value. 1314 */ 1315 size -= 0x10000; 1316 pcie_bar_cr_write(base, 1, size | 1); 1317 pcie_bar_br_write(base, 1, ddrbase | 1318 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1319 pcie_bar_br_write(base, 0, fdt_immr_pa | 1320 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1321 } 1322 1323 static int 1324 decode_win_pcie_valid(void) 1325 { 1326 1327 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1328 } 1329 1330 /************************************************************************** 1331 * IDMA windows routines 1332 **************************************************************************/ 1333 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1334 static int 1335 idma_bare_read(u_long base, int i) 1336 { 1337 uint32_t v; 1338 1339 v = win_idma_bare_read(base); 1340 v &= (1 << i); 1341 1342 return (v >> i); 1343 } 1344 1345 static void 1346 idma_bare_write(u_long base, int i, int val) 1347 { 1348 uint32_t v; 1349 1350 v = win_idma_bare_read(base); 1351 v &= ~(1 << i); 1352 v |= (val << i); 1353 win_idma_bare_write(base, v); 1354 } 1355 1356 /* 1357 * Sets channel protection 'val' for window 'w' on channel 'c' 1358 */ 1359 static void 1360 idma_cap_write(u_long base, int c, int w, int val) 1361 { 1362 uint32_t v; 1363 1364 v = win_idma_cap_read(base, c); 1365 v &= ~(0x3 << (w * 2)); 1366 v |= (val << (w * 2)); 1367 win_idma_cap_write(base, c, v); 1368 } 1369 1370 /* 1371 * Set protection 'val' on all channels for window 'w' 1372 */ 1373 static void 1374 idma_set_prot(u_long base, int w, int val) 1375 { 1376 int c; 1377 1378 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1379 idma_cap_write(base, c, w, val); 1380 } 1381 1382 static int 1383 win_idma_can_remap(int i) 1384 { 1385 1386 /* IDMA decode windows 0-3 have remap capability */ 1387 if (i < 4) 1388 return (1); 1389 1390 return (0); 1391 } 1392 1393 void 1394 decode_win_idma_setup(u_long base) 1395 { 1396 uint32_t br, sz; 1397 int i, j; 1398 1399 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1400 return; 1401 /* 1402 * Disable and clear all IDMA windows, revoke protection for all channels 1403 */ 1404 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1405 1406 idma_bare_write(base, i, 1); 1407 win_idma_br_write(base, i, 0); 1408 win_idma_sz_write(base, i, 0); 1409 if (win_idma_can_remap(i) == 1) 1410 win_idma_har_write(base, i, 0); 1411 } 1412 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1413 win_idma_cap_write(base, i, 0); 1414 1415 /* 1416 * Set up access to all active DRAM banks 1417 */ 1418 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1419 if (ddr_is_active(i)) { 1420 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1421 sz = ((ddr_size(i) - 1) & 0xffff0000); 1422 1423 /* Place DDR entries in non-remapped windows */ 1424 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1425 if (win_idma_can_remap(j) != 1 && 1426 idma_bare_read(base, j) == 1) { 1427 1428 /* Configure window */ 1429 win_idma_br_write(base, j, br); 1430 win_idma_sz_write(base, j, sz); 1431 1432 /* Set protection RW on all channels */ 1433 idma_set_prot(base, j, 0x3); 1434 1435 /* Enable window */ 1436 idma_bare_write(base, j, 0); 1437 break; 1438 } 1439 } 1440 1441 /* 1442 * Remaining targets -- from statically defined table 1443 */ 1444 for (i = 0; i < idma_wins_no; i++) 1445 if (idma_wins[i].target > 0) { 1446 br = (idma_wins[i].base & 0xffff0000) | 1447 (idma_wins[i].attr << 8) | idma_wins[i].target; 1448 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1449 1450 /* Set the first free IDMA window */ 1451 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1452 if (idma_bare_read(base, j) == 0) 1453 continue; 1454 1455 /* Configure window */ 1456 win_idma_br_write(base, j, br); 1457 win_idma_sz_write(base, j, sz); 1458 if (win_idma_can_remap(j) && 1459 idma_wins[j].remap >= 0) 1460 win_idma_har_write(base, j, 1461 idma_wins[j].remap); 1462 1463 /* Set protection RW on all channels */ 1464 idma_set_prot(base, j, 0x3); 1465 1466 /* Enable window */ 1467 idma_bare_write(base, j, 0); 1468 break; 1469 } 1470 } 1471 } 1472 1473 int 1474 decode_win_idma_valid(void) 1475 { 1476 const struct decode_win *wintab; 1477 int c, i, j, rv; 1478 uint32_t b, e, s; 1479 1480 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1481 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1482 return (0); 1483 } 1484 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1485 if (ddr_is_active(i)) 1486 c++; 1487 1488 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1489 printf("IDMA windows: too many entries: %d, available: %d\n", 1490 idma_wins_no, MV_WIN_IDMA_MAX - c); 1491 return (0); 1492 } 1493 1494 wintab = idma_wins; 1495 rv = 1; 1496 for (i = 0; i < idma_wins_no; i++, wintab++) { 1497 1498 if (wintab->target == 0) { 1499 printf("IDMA window#%d: DDR target window is not " 1500 "supposed to be reprogrammed!\n", i); 1501 rv = 0; 1502 } 1503 1504 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1505 printf("IDMA window#%d: not capable of remapping, but " 1506 "val 0x%08x defined\n", i, wintab->remap); 1507 rv = 0; 1508 } 1509 1510 s = wintab->size; 1511 b = wintab->base; 1512 e = b + s - 1; 1513 if (s > (0xFFFFFFFF - b + 1)) { 1514 /* XXX this boundary check should account for 64bit and 1515 * remapping.. */ 1516 printf("IDMA window#%d: no space for size 0x%08x at " 1517 "0x%08x\n", i, s, b); 1518 rv = 0; 1519 continue; 1520 } 1521 1522 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1523 if (j >= 0) { 1524 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1525 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1526 idma_wins[j].base, 1527 idma_wins[j].base + idma_wins[j].size - 1); 1528 rv = 0; 1529 } 1530 } 1531 1532 return (rv); 1533 } 1534 1535 void 1536 decode_win_idma_dump(u_long base) 1537 { 1538 int i; 1539 1540 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1541 return; 1542 1543 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1544 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1545 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1546 1547 if (win_idma_can_remap(i)) 1548 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1549 1550 printf("\n"); 1551 } 1552 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1553 printf("IDMA channel#%d: ap 0x%08x\n", i, 1554 win_idma_cap_read(base, i)); 1555 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1556 } 1557 #else 1558 1559 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1560 int 1561 decode_win_idma_valid(void) 1562 { 1563 1564 return (1); 1565 } 1566 1567 void 1568 decode_win_idma_setup(u_long base) 1569 { 1570 } 1571 1572 void 1573 decode_win_idma_dump(u_long base) 1574 { 1575 } 1576 #endif 1577 1578 /************************************************************************** 1579 * XOR windows routines 1580 **************************************************************************/ 1581 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1582 static int 1583 xor_ctrl_read(u_long base, int i, int c, int e) 1584 { 1585 uint32_t v; 1586 v = win_xor_ctrl_read(base, c, e); 1587 v &= (1 << i); 1588 1589 return (v >> i); 1590 } 1591 1592 static void 1593 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1594 { 1595 uint32_t v; 1596 1597 v = win_xor_ctrl_read(base, c, e); 1598 v &= ~(1 << i); 1599 v |= (val << i); 1600 win_xor_ctrl_write(base, c, e, v); 1601 } 1602 1603 /* 1604 * Set channel protection 'val' for window 'w' on channel 'c' 1605 */ 1606 static void 1607 xor_chan_write(u_long base, int c, int e, int w, int val) 1608 { 1609 uint32_t v; 1610 1611 v = win_xor_ctrl_read(base, c, e); 1612 v &= ~(0x3 << (w * 2 + 16)); 1613 v |= (val << (w * 2 + 16)); 1614 win_xor_ctrl_write(base, c, e, v); 1615 } 1616 1617 /* 1618 * Set protection 'val' on all channels for window 'w' on engine 'e' 1619 */ 1620 static void 1621 xor_set_prot(u_long base, int w, int e, int val) 1622 { 1623 int c; 1624 1625 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1626 xor_chan_write(base, c, e, w, val); 1627 } 1628 1629 static int 1630 win_xor_can_remap(int i) 1631 { 1632 1633 /* XOR decode windows 0-3 have remap capability */ 1634 if (i < 4) 1635 return (1); 1636 1637 return (0); 1638 } 1639 1640 static int 1641 xor_max_eng(void) 1642 { 1643 uint32_t dev, rev; 1644 1645 soc_id(&dev, &rev); 1646 switch (dev) { 1647 case MV_DEV_88F6281: 1648 case MV_DEV_88F6282: 1649 case MV_DEV_MV78130: 1650 case MV_DEV_MV78160: 1651 case MV_DEV_MV78230: 1652 case MV_DEV_MV78260: 1653 case MV_DEV_MV78460: 1654 return (2); 1655 case MV_DEV_MV78100: 1656 case MV_DEV_MV78100_Z0: 1657 return (1); 1658 default: 1659 return (0); 1660 } 1661 } 1662 1663 static void 1664 xor_active_dram(u_long base, int c, int e, int *window) 1665 { 1666 uint32_t br, sz; 1667 int i, m, w; 1668 1669 /* 1670 * Set up access to all active DRAM banks 1671 */ 1672 m = xor_max_eng(); 1673 for (i = 0; i < m; i++) 1674 if (ddr_is_active(i)) { 1675 br = ddr_base(i) | (ddr_attr(i) << 8) | 1676 ddr_target(i); 1677 sz = ((ddr_size(i) - 1) & 0xffff0000); 1678 1679 /* Place DDR entries in non-remapped windows */ 1680 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1681 if (win_xor_can_remap(w) != 1 && 1682 (xor_ctrl_read(base, w, c, e) == 0) && 1683 w > *window) { 1684 /* Configure window */ 1685 win_xor_br_write(base, w, e, br); 1686 win_xor_sz_write(base, w, e, sz); 1687 1688 /* Set protection RW on all channels */ 1689 xor_set_prot(base, w, e, 0x3); 1690 1691 /* Enable window */ 1692 xor_ctrl_write(base, w, c, e, 1); 1693 (*window)++; 1694 break; 1695 } 1696 } 1697 } 1698 1699 void 1700 decode_win_xor_setup(u_long base) 1701 { 1702 uint32_t br, sz; 1703 int i, j, z, e = 1, m, window; 1704 1705 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1706 return; 1707 1708 /* 1709 * Disable and clear all XOR windows, revoke protection for all 1710 * channels 1711 */ 1712 m = xor_max_eng(); 1713 for (j = 0; j < m; j++, e--) { 1714 1715 /* Number of non-remaped windows */ 1716 window = MV_XOR_NON_REMAP - 1; 1717 1718 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1719 win_xor_br_write(base, i, e, 0); 1720 win_xor_sz_write(base, i, e, 0); 1721 } 1722 1723 if (win_xor_can_remap(i) == 1) 1724 win_xor_har_write(base, i, e, 0); 1725 1726 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1727 win_xor_ctrl_write(base, i, e, 0); 1728 xor_active_dram(base, i, e, &window); 1729 } 1730 1731 /* 1732 * Remaining targets -- from a statically defined table 1733 */ 1734 for (i = 0; i < xor_wins_no; i++) 1735 if (xor_wins[i].target > 0) { 1736 br = (xor_wins[i].base & 0xffff0000) | 1737 (xor_wins[i].attr << 8) | 1738 xor_wins[i].target; 1739 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1740 1741 /* Set the first free XOR window */ 1742 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1743 if (xor_ctrl_read(base, z, 0, e) && 1744 xor_ctrl_read(base, z, 1, e)) 1745 continue; 1746 1747 /* Configure window */ 1748 win_xor_br_write(base, z, e, br); 1749 win_xor_sz_write(base, z, e, sz); 1750 if (win_xor_can_remap(z) && 1751 xor_wins[z].remap >= 0) 1752 win_xor_har_write(base, z, e, 1753 xor_wins[z].remap); 1754 1755 /* Set protection RW on all channels */ 1756 xor_set_prot(base, z, e, 0x3); 1757 1758 /* Enable window */ 1759 xor_ctrl_write(base, z, 0, e, 1); 1760 xor_ctrl_write(base, z, 1, e, 1); 1761 break; 1762 } 1763 } 1764 } 1765 } 1766 1767 int 1768 decode_win_xor_valid(void) 1769 { 1770 const struct decode_win *wintab; 1771 int c, i, j, rv; 1772 uint32_t b, e, s; 1773 1774 if (xor_wins_no > MV_WIN_XOR_MAX) { 1775 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1776 return (0); 1777 } 1778 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1779 if (ddr_is_active(i)) 1780 c++; 1781 1782 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1783 printf("XOR windows: too many entries: %d, available: %d\n", 1784 xor_wins_no, MV_WIN_IDMA_MAX - c); 1785 return (0); 1786 } 1787 1788 wintab = xor_wins; 1789 rv = 1; 1790 for (i = 0; i < xor_wins_no; i++, wintab++) { 1791 1792 if (wintab->target == 0) { 1793 printf("XOR window#%d: DDR target window is not " 1794 "supposed to be reprogrammed!\n", i); 1795 rv = 0; 1796 } 1797 1798 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1799 printf("XOR window#%d: not capable of remapping, but " 1800 "val 0x%08x defined\n", i, wintab->remap); 1801 rv = 0; 1802 } 1803 1804 s = wintab->size; 1805 b = wintab->base; 1806 e = b + s - 1; 1807 if (s > (0xFFFFFFFF - b + 1)) { 1808 /* 1809 * XXX this boundary check should account for 64bit 1810 * and remapping.. 1811 */ 1812 printf("XOR window#%d: no space for size 0x%08x at " 1813 "0x%08x\n", i, s, b); 1814 rv = 0; 1815 continue; 1816 } 1817 1818 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 1819 if (j >= 0) { 1820 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 1821 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1822 xor_wins[j].base, 1823 xor_wins[j].base + xor_wins[j].size - 1); 1824 rv = 0; 1825 } 1826 } 1827 1828 return (rv); 1829 } 1830 1831 void 1832 decode_win_xor_dump(u_long base) 1833 { 1834 int i, j; 1835 int e = 1; 1836 1837 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1838 return; 1839 1840 for (j = 0; j < xor_max_eng(); j++, e--) { 1841 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1842 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 1843 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 1844 1845 if (win_xor_can_remap(i)) 1846 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 1847 1848 printf("\n"); 1849 } 1850 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 1851 printf("XOR control#%d: 0x%08x\n", i, 1852 win_xor_ctrl_read(base, i, e)); 1853 } 1854 } 1855 1856 #else 1857 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 1858 static int 1859 decode_win_xor_valid(void) 1860 { 1861 1862 return (1); 1863 } 1864 1865 static void 1866 decode_win_xor_setup(u_long base) 1867 { 1868 } 1869 1870 static void 1871 decode_win_xor_dump(u_long base) 1872 { 1873 } 1874 #endif 1875 1876 /************************************************************************** 1877 * SATA windows routines 1878 **************************************************************************/ 1879 static void 1880 decode_win_sata_setup(u_long base) 1881 { 1882 uint32_t cr, br; 1883 int i, j; 1884 1885 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 1886 return; 1887 1888 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 1889 win_sata_cr_write(base, i, 0); 1890 win_sata_br_write(base, i, 0); 1891 } 1892 1893 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1894 if (ddr_is_active(i)) { 1895 cr = ((ddr_size(i) - 1) & 0xffff0000) | 1896 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1897 br = ddr_base(i); 1898 1899 /* Use the first available SATA window */ 1900 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 1901 if ((win_sata_cr_read(base, j) & 1) != 0) 1902 continue; 1903 1904 win_sata_br_write(base, j, br); 1905 win_sata_cr_write(base, j, cr); 1906 break; 1907 } 1908 } 1909 } 1910 1911 static int 1912 decode_win_sata_valid(void) 1913 { 1914 uint32_t dev, rev; 1915 1916 soc_id(&dev, &rev); 1917 if (dev == MV_DEV_88F5281) 1918 return (1); 1919 1920 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 1921 } 1922 1923 /************************************************************************** 1924 * FDT parsing routines. 1925 **************************************************************************/ 1926 1927 static int 1928 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 1929 int *tuplesize) 1930 { 1931 phandle_t node; 1932 pcell_t addr_cells, par_addr_cells, size_cells; 1933 int len, tuple_size, tuples_count; 1934 1935 node = OF_finddevice(nodename); 1936 if (node == -1) 1937 return (EINVAL); 1938 1939 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 1940 return (ENXIO); 1941 1942 par_addr_cells = fdt_parent_addr_cells(node); 1943 if (par_addr_cells > 2) 1944 return (ERANGE); 1945 1946 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 1947 size_cells); 1948 1949 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 1950 len = OF_getprop(node, "ranges", buf, size); 1951 1952 /* 1953 * XXX this does not handle the empty 'ranges;' case, which is 1954 * legitimate and should be allowed. 1955 */ 1956 tuples_count = len / tuple_size; 1957 if (tuples_count <= 0) 1958 return (ERANGE); 1959 1960 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 1961 return (ERANGE); 1962 1963 *tuples = tuples_count; 1964 *tuplesize = tuple_size; 1965 return (0); 1966 } 1967 1968 static int 1969 win_cpu_from_dt(void) 1970 { 1971 pcell_t ranges[48]; 1972 phandle_t node; 1973 int i, entry_size, err, t, tuple_size, tuples; 1974 u_long sram_base, sram_size; 1975 1976 t = 0; 1977 /* Retrieve 'ranges' property of '/localbus' node. */ 1978 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 1979 &tuples, &tuple_size)) == 0) { 1980 /* 1981 * Fill CPU decode windows table. 1982 */ 1983 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 1984 1985 entry_size = tuple_size / sizeof(pcell_t); 1986 cpu_wins_no = tuples; 1987 1988 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 1989 cpu_win_tbl[t].target = 1; 1990 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 1991 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 1992 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 1993 cpu_win_tbl[t].remap = ~0; 1994 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 1995 "size = 0x%0x remap = 0x%0x\n", 1996 cpu_win_tbl[t].target, 1997 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 1998 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 1999 } 2000 } 2001 2002 /* 2003 * Retrieve CESA SRAM data. 2004 */ 2005 if ((node = OF_finddevice("sram")) != -1) 2006 if (fdt_is_compatible(node, "mrvl,cesa-sram")) 2007 goto moveon; 2008 2009 if ((node = OF_finddevice("/")) == 0) 2010 return (ENXIO); 2011 2012 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2013 /* SRAM block is not always present. */ 2014 return (0); 2015 moveon: 2016 sram_base = sram_size = 0; 2017 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2018 return (EINVAL); 2019 2020 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2021 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2022 cpu_win_tbl[t].base = sram_base; 2023 cpu_win_tbl[t].size = sram_size; 2024 cpu_win_tbl[t].remap = ~0; 2025 cpu_wins_no++; 2026 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2027 2028 return (0); 2029 } 2030 2031 static int 2032 fdt_win_setup(void) 2033 { 2034 phandle_t node, child; 2035 struct soc_node_spec *soc_node; 2036 u_long size, base; 2037 int err, i; 2038 2039 node = OF_finddevice("/"); 2040 if (node == -1) 2041 panic("fdt_win_setup: no root node"); 2042 2043 /* 2044 * Traverse through all children of root and simple-bus nodes. 2045 * For each found device retrieve decode windows data (if applicable). 2046 */ 2047 child = OF_child(node); 2048 while (child != 0) { 2049 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2050 2051 soc_node = &soc_nodes[i]; 2052 2053 if (!fdt_is_compatible(child, soc_node->compat)) 2054 continue; 2055 2056 err = fdt_regsize(child, &base, &size); 2057 if (err != 0) 2058 return (err); 2059 2060 base = (base & 0x000fffff) | fdt_immr_va; 2061 if (soc_node->decode_handler != NULL) 2062 soc_node->decode_handler(base); 2063 else 2064 return (ENXIO); 2065 2066 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2067 soc_node->dump_handler(base); 2068 } 2069 2070 /* 2071 * Once done with root-level children let's move down to 2072 * simple-bus and its children. 2073 */ 2074 child = OF_peer(child); 2075 if ((child == 0) && (node == OF_finddevice("/"))) { 2076 node = fdt_find_compatible(node, "simple-bus", 0); 2077 if (node == 0) 2078 return (ENXIO); 2079 child = OF_child(node); 2080 } 2081 } 2082 2083 return (0); 2084 } 2085 2086 static void 2087 fdt_fixup_busfreq(phandle_t root) 2088 { 2089 phandle_t sb; 2090 pcell_t freq; 2091 2092 freq = cpu_to_fdt32(get_tclk()); 2093 2094 /* 2095 * Fix bus speed in cpu node 2096 */ 2097 if ((sb = OF_finddevice("cpu")) != 0) 2098 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2099 OF_setprop(sb, "bus-frequency", (void *)&freq, 2100 sizeof(freq)); 2101 2102 /* 2103 * This fixup sets the simple-bus bus-frequency property. 2104 */ 2105 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2106 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2107 } 2108 2109 static void 2110 fdt_fixup_ranges(phandle_t root) 2111 { 2112 phandle_t node; 2113 pcell_t par_addr_cells, addr_cells, size_cells; 2114 pcell_t ranges[3], reg[2], *rangesptr; 2115 int len, tuple_size, tuples_count; 2116 uint32_t base; 2117 2118 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2119 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2120 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2121 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2122 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2123 addr_cells + size_cells); 2124 len = OF_getprop(node, "ranges", ranges, 2125 sizeof(ranges)); 2126 tuples_count = len / tuple_size; 2127 /* Unexpected settings are not supported */ 2128 if (tuples_count != 1) 2129 goto fixup_failed; 2130 2131 rangesptr = &ranges[0]; 2132 rangesptr += par_addr_cells; 2133 base = fdt_data_get((void *)rangesptr, addr_cells); 2134 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2135 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2136 sizeof(ranges)) < 0) 2137 goto fixup_failed; 2138 } 2139 } 2140 2141 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2142 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2143 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2144 &size_cells) == 0) { 2145 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2146 size_cells); 2147 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2148 tuples_count = len / tuple_size; 2149 /* Unexpected settings are not supported */ 2150 if (tuples_count != 1) 2151 goto fixup_failed; 2152 2153 base = fdt_data_get((void *)®[0], par_addr_cells); 2154 base &= ~0xFF000000; 2155 base |= fdt_immr_pa; 2156 reg[0] = cpu_to_fdt32(base); 2157 if (OF_setprop(node, "reg", (void *)®[0], 2158 sizeof(reg)) < 0) 2159 goto fixup_failed; 2160 } 2161 } 2162 /* Fix-up succeeded. May return and continue */ 2163 return; 2164 2165 fixup_failed: 2166 while (1) { 2167 /* 2168 * In case of any error while fixing ranges just hang. 2169 * 1. No message can be displayed yet since console 2170 * is not initialized. 2171 * 2. Going further will cause failure on bus_space_map() 2172 * relying on the wrong ranges or data abort when 2173 * accessing PCIe registers. 2174 */ 2175 } 2176 } 2177 2178 struct fdt_fixup_entry fdt_fixup_table[] = { 2179 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2180 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2181 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2182 { NULL, NULL } 2183 }; 2184 2185 #ifndef ARM_INTRNG 2186 static int 2187 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2188 int *pol) 2189 { 2190 2191 if (!fdt_is_compatible(node, "mrvl,pic") && 2192 !fdt_is_compatible(node, "mrvl,mpic")) 2193 return (ENXIO); 2194 2195 *interrupt = fdt32_to_cpu(intr[0]); 2196 *trig = INTR_TRIGGER_CONFORM; 2197 *pol = INTR_POLARITY_CONFORM; 2198 2199 return (0); 2200 } 2201 2202 fdt_pic_decode_t fdt_pic_table[] = { 2203 #ifdef SOC_MV_ARMADA38X 2204 &gic_decode_fdt, 2205 #endif 2206 &fdt_pic_decode_ic, 2207 NULL 2208 }; 2209 #endif 2210 2211 uint64_t 2212 get_sar_value(void) 2213 { 2214 uint32_t sar_low, sar_high; 2215 2216 #if defined(SOC_MV_ARMADAXP) 2217 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2218 SAMPLE_AT_RESET_HI); 2219 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2220 SAMPLE_AT_RESET_LO); 2221 #elif defined(SOC_MV_ARMADA38X) 2222 sar_high = 0; 2223 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2224 SAMPLE_AT_RESET); 2225 #else 2226 /* 2227 * TODO: Add getting proper values for other SoC configurations 2228 */ 2229 sar_high = 0; 2230 sar_low = 0; 2231 #endif 2232 2233 return (((uint64_t)sar_high << 32) | sar_low); 2234 } 2235