1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 #ifndef SOC_MV_FREY 80 static int decode_win_cpu_valid(void); 81 #endif 82 static int decode_win_usb_valid(void); 83 static int decode_win_usb3_valid(void); 84 static int decode_win_eth_valid(void); 85 static int decode_win_pcie_valid(void); 86 static int decode_win_sata_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 #ifndef SOC_MV_FREY 92 static void decode_win_cpu_setup(void); 93 #endif 94 #ifdef SOC_MV_ARMADAXP 95 static int decode_win_sdram_fixup(void); 96 #endif 97 static void decode_win_usb_setup(u_long); 98 static void decode_win_usb3_setup(u_long); 99 static void decode_win_eth_setup(u_long); 100 static void decode_win_sata_setup(u_long); 101 102 static void decode_win_idma_setup(u_long); 103 static void decode_win_xor_setup(u_long); 104 105 static void decode_win_usb_dump(u_long); 106 static void decode_win_usb3_dump(u_long); 107 static void decode_win_eth_dump(u_long base); 108 static void decode_win_idma_dump(u_long base); 109 static void decode_win_xor_dump(u_long base); 110 111 static int fdt_get_ranges(const char *, void *, int, int *, int *); 112 #ifdef SOC_MV_ARMADA38X 113 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 114 int *trig, int *pol); 115 #endif 116 117 static int win_cpu_from_dt(void); 118 static int fdt_win_setup(void); 119 120 static uint32_t dev_mask = 0; 121 static int cpu_wins_no = 0; 122 static int eth_port = 0; 123 static int usb_port = 0; 124 125 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 126 127 const struct decode_win *cpu_wins = cpu_win_tbl; 128 129 typedef void (*decode_win_setup_t)(u_long); 130 typedef void (*dump_win_t)(u_long); 131 132 struct soc_node_spec { 133 const char *compat; 134 decode_win_setup_t decode_handler; 135 dump_win_t dump_handler; 136 }; 137 138 static struct soc_node_spec soc_nodes[] = { 139 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 140 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 141 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 142 { "mrvl,sata", &decode_win_sata_setup, NULL }, 143 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 144 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 145 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 146 { NULL, NULL, NULL }, 147 }; 148 149 struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 150 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 151 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 152 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 153 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 154 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 155 { "mrvl,xor", CPU_PM_CTRL_XOR }, 156 { "mrvl,sata", CPU_PM_CTRL_SATA }, 157 158 { NULL, 0 } 159 }; 160 161 static __inline int 162 pm_is_disabled(uint32_t mask) 163 { 164 #if defined(SOC_MV_KIRKWOOD) 165 return (soc_power_ctrl_get(mask) == mask); 166 #else 167 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 168 #endif 169 } 170 171 /* 172 * Disable device using power management register. 173 * 1 - Device Power On 174 * 0 - Device Power Off 175 * Mask can be set in loader. 176 * EXAMPLE: 177 * loader> set hw.pm-disable-mask=0x2 178 * 179 * Common mask: 180 * |-------------------------------| 181 * | Device | Kirkwood | Discovery | 182 * |-------------------------------| 183 * | USB0 | 0x00008 | 0x020000 | 184 * |-------------------------------| 185 * | USB1 | - | 0x040000 | 186 * |-------------------------------| 187 * | USB2 | - | 0x080000 | 188 * |-------------------------------| 189 * | GE0 | 0x00001 | 0x000002 | 190 * |-------------------------------| 191 * | GE1 | - | 0x000004 | 192 * |-------------------------------| 193 * | IDMA | - | 0x100000 | 194 * |-------------------------------| 195 * | XOR | 0x10000 | 0x200000 | 196 * |-------------------------------| 197 * | CESA | 0x20000 | 0x400000 | 198 * |-------------------------------| 199 * | SATA | 0x04000 | 0x004000 | 200 * --------------------------------| 201 * This feature can be used only on Kirkwood and Discovery 202 * machines. 203 */ 204 static __inline void 205 pm_disable_device(int mask) 206 { 207 #ifdef DIAGNOSTIC 208 uint32_t reg; 209 210 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 211 printf("Power Management Register: 0%x\n", reg); 212 213 reg &= ~mask; 214 soc_power_ctrl_set(reg); 215 printf("Device %x is disabled\n", mask); 216 217 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 218 printf("Power Management Register: 0%x\n", reg); 219 #endif 220 } 221 222 int 223 fdt_pm(phandle_t node) 224 { 225 uint32_t cpu_pm_ctrl; 226 int i, ena, compat; 227 228 ena = 1; 229 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 230 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 231 if (dev_mask & (1 << i)) 232 continue; 233 234 compat = ofw_bus_node_is_compatible(node, 235 fdt_pm_mask_table[i].compat); 236 #if defined(SOC_MV_KIRKWOOD) 237 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 238 dev_mask |= (1 << i); 239 ena = 0; 240 break; 241 } else if (compat) { 242 dev_mask |= (1 << i); 243 break; 244 } 245 #else 246 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 247 dev_mask |= (1 << i); 248 ena = 0; 249 break; 250 } else if (compat) { 251 dev_mask |= (1 << i); 252 break; 253 } 254 #endif 255 } 256 257 return (ena); 258 } 259 260 uint32_t 261 read_cpu_ctrl(uint32_t reg) 262 { 263 264 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 265 } 266 267 void 268 write_cpu_ctrl(uint32_t reg, uint32_t val) 269 { 270 271 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 272 } 273 274 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 275 uint32_t 276 read_cpu_mp_clocks(uint32_t reg) 277 { 278 279 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 280 } 281 282 void 283 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 284 { 285 286 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 287 } 288 289 uint32_t 290 read_cpu_misc(uint32_t reg) 291 { 292 293 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 294 } 295 296 void 297 write_cpu_misc(uint32_t reg, uint32_t val) 298 { 299 300 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 301 } 302 #endif 303 304 void 305 cpu_reset(void) 306 { 307 308 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 309 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 310 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 311 #else 312 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 313 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 314 #endif 315 while (1); 316 } 317 318 uint32_t 319 cpu_extra_feat(void) 320 { 321 uint32_t dev, rev; 322 uint32_t ef = 0; 323 324 soc_id(&dev, &rev); 325 326 switch (dev) { 327 case MV_DEV_88F6281: 328 case MV_DEV_88F6282: 329 case MV_DEV_88RC8180: 330 case MV_DEV_MV78100_Z0: 331 case MV_DEV_MV78100: 332 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 333 break; 334 case MV_DEV_88F5182: 335 case MV_DEV_88F5281: 336 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 337 break; 338 default: 339 if (bootverbose) 340 printf("This ARM Core does not support any extra features\n"); 341 } 342 343 return (ef); 344 } 345 346 /* 347 * Get the power status of device. This feature is only supported on 348 * Kirkwood and Discovery SoCs. 349 */ 350 uint32_t 351 soc_power_ctrl_get(uint32_t mask) 352 { 353 354 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY) 355 if (mask != CPU_PM_CTRL_NONE) 356 mask &= read_cpu_ctrl(CPU_PM_CTRL); 357 358 return (mask); 359 #else 360 return (mask); 361 #endif 362 } 363 364 /* 365 * Set the power status of device. This feature is only supported on 366 * Kirkwood and Discovery SoCs. 367 */ 368 void 369 soc_power_ctrl_set(uint32_t mask) 370 { 371 372 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) 373 if (mask != CPU_PM_CTRL_NONE) 374 write_cpu_ctrl(CPU_PM_CTRL, mask); 375 #endif 376 } 377 378 void 379 soc_id(uint32_t *dev, uint32_t *rev) 380 { 381 382 /* 383 * Notice: system identifiers are available in the registers range of 384 * PCIE controller, so using this function is only allowed (and 385 * possible) after the internal registers range has been mapped in via 386 * devmap_bootstrap(). 387 */ 388 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 389 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 390 } 391 392 static void 393 soc_identify(void) 394 { 395 uint32_t d, r, size, mode; 396 const char *dev; 397 const char *rev; 398 399 soc_id(&d, &r); 400 401 printf("SOC: "); 402 if (bootverbose) 403 printf("(0x%4x:0x%02x) ", d, r); 404 405 rev = ""; 406 switch (d) { 407 case MV_DEV_88F5181: 408 dev = "Marvell 88F5181"; 409 if (r == 3) 410 rev = "B1"; 411 break; 412 case MV_DEV_88F5182: 413 dev = "Marvell 88F5182"; 414 if (r == 2) 415 rev = "A2"; 416 break; 417 case MV_DEV_88F5281: 418 dev = "Marvell 88F5281"; 419 if (r == 4) 420 rev = "D0"; 421 else if (r == 5) 422 rev = "D1"; 423 else if (r == 6) 424 rev = "D2"; 425 break; 426 case MV_DEV_88F6281: 427 dev = "Marvell 88F6281"; 428 if (r == 0) 429 rev = "Z0"; 430 else if (r == 2) 431 rev = "A0"; 432 else if (r == 3) 433 rev = "A1"; 434 break; 435 case MV_DEV_88RC8180: 436 dev = "Marvell 88RC8180"; 437 break; 438 case MV_DEV_88RC9480: 439 dev = "Marvell 88RC9480"; 440 break; 441 case MV_DEV_88RC9580: 442 dev = "Marvell 88RC9580"; 443 break; 444 case MV_DEV_88F6781: 445 dev = "Marvell 88F6781"; 446 if (r == 2) 447 rev = "Y0"; 448 break; 449 case MV_DEV_88F6282: 450 dev = "Marvell 88F6282"; 451 if (r == 0) 452 rev = "A0"; 453 else if (r == 1) 454 rev = "A1"; 455 break; 456 case MV_DEV_88F6828: 457 dev = "Marvell 88F6828"; 458 break; 459 case MV_DEV_88F6820: 460 dev = "Marvell 88F6820"; 461 break; 462 case MV_DEV_88F6810: 463 dev = "Marvell 88F6810"; 464 break; 465 case MV_DEV_MV78100_Z0: 466 dev = "Marvell MV78100 Z0"; 467 break; 468 case MV_DEV_MV78100: 469 dev = "Marvell MV78100"; 470 break; 471 case MV_DEV_MV78160: 472 dev = "Marvell MV78160"; 473 break; 474 case MV_DEV_MV78260: 475 dev = "Marvell MV78260"; 476 break; 477 case MV_DEV_MV78460: 478 dev = "Marvell MV78460"; 479 break; 480 default: 481 dev = "UNKNOWN"; 482 break; 483 } 484 485 printf("%s", dev); 486 if (*rev != '\0') 487 printf(" rev %s", rev); 488 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 489 490 mode = read_cpu_ctrl(CPU_CONFIG); 491 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 492 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 493 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 494 495 switch (d) { 496 case MV_DEV_88F6281: 497 case MV_DEV_88F6282: 498 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 499 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 500 mode ? "write-through" : "write-back"); 501 break; 502 case MV_DEV_MV78100: 503 mode = read_cpu_ctrl(CPU_CONTROL); 504 size = mode & CPU_CONTROL_L2_SIZE; 505 mode = mode & CPU_CONTROL_L2_MODE; 506 printf(" %s set-associative %s unified L2 cache\n", 507 size ? "256KB 4-way" : "512KB 8-way", 508 mode ? "write-through" : "write-back"); 509 break; 510 default: 511 break; 512 } 513 } 514 515 static void 516 platform_identify(void *dummy) 517 { 518 519 soc_identify(); 520 521 /* 522 * XXX Board identification e.g. read out from FPGA or similar should 523 * go here 524 */ 525 } 526 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 527 NULL); 528 529 #ifdef KDB 530 static void 531 mv_enter_debugger(void *dummy) 532 { 533 534 if (boothowto & RB_KDB) 535 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 536 } 537 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 538 #endif 539 540 int 541 soc_decode_win(void) 542 { 543 uint32_t dev, rev; 544 int mask, err; 545 546 mask = 0; 547 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 548 549 if (mask != 0) 550 pm_disable_device(mask); 551 552 /* Retrieve data about physical addresses from device tree. */ 553 if ((err = win_cpu_from_dt()) != 0) 554 return (err); 555 556 /* Retrieve our ID: some windows facilities vary between SoC models */ 557 soc_id(&dev, &rev); 558 559 #ifdef SOC_MV_ARMADAXP 560 if ((err = decode_win_sdram_fixup()) != 0) 561 return(err); 562 #endif 563 564 #ifndef SOC_MV_FREY 565 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 566 !decode_win_eth_valid() || !decode_win_idma_valid() || 567 !decode_win_pcie_valid() || !decode_win_sata_valid() || 568 !decode_win_xor_valid() || !decode_win_usb3_valid()) 569 return (EINVAL); 570 571 decode_win_cpu_setup(); 572 #else 573 if (!decode_win_usb_valid() || 574 !decode_win_eth_valid() || !decode_win_idma_valid() || 575 !decode_win_pcie_valid() || !decode_win_sata_valid() || 576 !decode_win_xor_valid() || !decode_win_usb3_valid()) 577 return (EINVAL); 578 #endif 579 if (MV_DUMP_WIN) 580 soc_dump_decode_win(); 581 582 eth_port = 0; 583 usb_port = 0; 584 if ((err = fdt_win_setup()) != 0) 585 return (err); 586 587 return (0); 588 } 589 590 /************************************************************************** 591 * Decode windows registers accessors 592 **************************************************************************/ 593 #if !defined(SOC_MV_FREY) 594 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 595 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 596 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 597 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 598 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 599 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 600 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 601 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 602 #endif 603 604 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 605 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 606 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 607 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 608 609 #ifdef SOC_MV_ARMADA38X 610 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 611 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 612 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 613 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 614 #endif 615 616 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 617 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 618 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 619 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 620 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 621 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 622 623 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 624 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 625 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 626 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 627 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 628 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 629 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 630 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 631 632 WIN_REG_BASE_RD(win_eth, bare, 0x290) 633 WIN_REG_BASE_RD(win_eth, epap, 0x294) 634 WIN_REG_BASE_WR(win_eth, bare, 0x290) 635 WIN_REG_BASE_WR(win_eth, epap, 0x294) 636 637 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 638 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 639 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 640 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 641 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 642 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 643 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 644 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 645 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 646 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 647 648 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 649 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 650 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 651 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 652 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 653 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 654 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 655 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 656 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 657 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 658 659 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 660 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 661 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 662 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 663 #ifndef SOC_MV_DOVE 664 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 665 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 666 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 667 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 668 #else 669 /* 670 * On 88F6781 (Dove) SoC DDR Controller is accessed through 671 * single MBUS <-> AXI bridge. In this case we provide emulated 672 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 673 * with common decoding windows setup code. 674 */ 675 676 static inline uint32_t ddr_br_read(int i) 677 { 678 uint32_t mmap; 679 680 /* Read Memory Address Map Register for CS i */ 681 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 682 683 /* Return CS i base address */ 684 return (mmap & 0xFF000000); 685 } 686 687 static inline uint32_t ddr_sz_read(int i) 688 { 689 uint32_t mmap, size; 690 691 /* Read Memory Address Map Register for CS i */ 692 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 693 694 /* Extract size of CS space in 64kB units */ 695 size = (1 << ((mmap >> 16) & 0x0F)); 696 697 /* Return CS size and enable/disable status */ 698 return (((size - 1) << 16) | (mmap & 0x01)); 699 } 700 #endif 701 702 #if !defined(SOC_MV_FREY) 703 /************************************************************************** 704 * Decode windows helper routines 705 **************************************************************************/ 706 void 707 soc_dump_decode_win(void) 708 { 709 uint32_t dev, rev; 710 int i; 711 712 soc_id(&dev, &rev); 713 714 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 715 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 716 win_cpu_cr_read(i), 717 win_cpu_br_read(i)); 718 719 if (win_cpu_can_remap(i)) 720 printf(", rl 0x%08x, rh 0x%08x", 721 win_cpu_remap_l_read(i), 722 win_cpu_remap_h_read(i)); 723 724 printf("\n"); 725 } 726 printf("Internal regs base: 0x%08x\n", 727 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 728 729 for (i = 0; i < MV_WIN_DDR_MAX; i++) 730 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 731 ddr_br_read(i), ddr_sz_read(i)); 732 } 733 734 /************************************************************************** 735 * CPU windows routines 736 **************************************************************************/ 737 int 738 win_cpu_can_remap(int i) 739 { 740 uint32_t dev, rev; 741 742 soc_id(&dev, &rev); 743 744 /* Depending on the SoC certain windows have remap capability */ 745 if ((dev == MV_DEV_88F5182 && i < 2) || 746 (dev == MV_DEV_88F5281 && i < 4) || 747 (dev == MV_DEV_88F6281 && i < 4) || 748 (dev == MV_DEV_88F6282 && i < 4) || 749 (dev == MV_DEV_88F6828 && i < 20) || 750 (dev == MV_DEV_88F6820 && i < 20) || 751 (dev == MV_DEV_88F6810 && i < 20) || 752 (dev == MV_DEV_88RC8180 && i < 2) || 753 (dev == MV_DEV_88F6781 && i < 4) || 754 (dev == MV_DEV_MV78100_Z0 && i < 8) || 755 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 756 return (1); 757 758 return (0); 759 } 760 761 /* XXX This should check for overlapping remap fields too.. */ 762 int 763 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 764 { 765 const struct decode_win *tab; 766 int i; 767 768 tab = wintab; 769 770 for (i = 0; i < win_no; i++, tab++) { 771 if (i == win) 772 /* Skip self */ 773 continue; 774 775 if ((tab->base + tab->size - 1) < (wintab + win)->base) 776 continue; 777 778 else if (((wintab + win)->base + (wintab + win)->size - 1) < 779 tab->base) 780 continue; 781 else 782 return (i); 783 } 784 785 return (-1); 786 } 787 788 static int 789 decode_win_cpu_valid(void) 790 { 791 int i, j, rv; 792 uint32_t b, e, s; 793 794 if (cpu_wins_no > MV_WIN_CPU_MAX) { 795 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 796 return (0); 797 } 798 799 rv = 1; 800 for (i = 0; i < cpu_wins_no; i++) { 801 802 if (cpu_wins[i].target == 0) { 803 printf("CPU window#%d: DDR target window is not " 804 "supposed to be reprogrammed!\n", i); 805 rv = 0; 806 } 807 808 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 809 printf("CPU window#%d: not capable of remapping, but " 810 "val 0x%08x defined\n", i, cpu_wins[i].remap); 811 rv = 0; 812 } 813 814 s = cpu_wins[i].size; 815 b = cpu_wins[i].base; 816 e = b + s - 1; 817 if (s > (0xFFFFFFFF - b + 1)) { 818 /* 819 * XXX this boundary check should account for 64bit 820 * and remapping.. 821 */ 822 printf("CPU window#%d: no space for size 0x%08x at " 823 "0x%08x\n", i, s, b); 824 rv = 0; 825 continue; 826 } 827 828 if (b != rounddown2(b, s)) { 829 printf("CPU window#%d: address 0x%08x is not aligned " 830 "to 0x%08x\n", i, b, s); 831 rv = 0; 832 continue; 833 } 834 835 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 836 if (j >= 0) { 837 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 838 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 839 cpu_wins[j].base, 840 cpu_wins[j].base + cpu_wins[j].size - 1); 841 rv = 0; 842 } 843 } 844 845 return (rv); 846 } 847 848 int 849 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 850 vm_paddr_t remap) 851 { 852 uint32_t br, cr; 853 int win, i; 854 855 if (remap == ~0) { 856 win = MV_WIN_CPU_MAX - 1; 857 i = -1; 858 } else { 859 win = 0; 860 i = 1; 861 } 862 863 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 864 cr = win_cpu_cr_read(win); 865 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 866 break; 867 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 868 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 869 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 870 (target << MV_WIN_CPU_TARGET_SHIFT))) 871 break; 872 win += i; 873 } 874 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 875 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 876 return (-1); 877 878 br = base & 0xffff0000; 879 win_cpu_br_write(win, br); 880 881 if (win_cpu_can_remap(win)) { 882 if (remap != ~0) { 883 win_cpu_remap_l_write(win, remap & 0xffff0000); 884 win_cpu_remap_h_write(win, 0); 885 } else { 886 /* 887 * Remap function is not used for a given window 888 * (capable of remapping) - set remap field with the 889 * same value as base. 890 */ 891 win_cpu_remap_l_write(win, base & 0xffff0000); 892 win_cpu_remap_h_write(win, 0); 893 } 894 } 895 896 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 897 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 898 win_cpu_cr_write(win, cr); 899 900 return (0); 901 } 902 903 static void 904 decode_win_cpu_setup(void) 905 { 906 int i; 907 908 /* Disable all CPU windows */ 909 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 910 win_cpu_cr_write(i, 0); 911 win_cpu_br_write(i, 0); 912 if (win_cpu_can_remap(i)) { 913 win_cpu_remap_l_write(i, 0); 914 win_cpu_remap_h_write(i, 0); 915 } 916 } 917 918 for (i = 0; i < cpu_wins_no; i++) 919 if (cpu_wins[i].target > 0) 920 decode_win_cpu_set(cpu_wins[i].target, 921 cpu_wins[i].attr, cpu_wins[i].base, 922 cpu_wins[i].size, cpu_wins[i].remap); 923 924 } 925 #endif 926 927 #ifdef SOC_MV_ARMADAXP 928 static int 929 decode_win_sdram_fixup(void) 930 { 931 struct mem_region mr[FDT_MEM_REGIONS]; 932 uint8_t window_valid[MV_WIN_DDR_MAX]; 933 int mr_cnt, err, i, j; 934 uint32_t valid_win_num = 0; 935 936 /* Grab physical memory regions information from device tree. */ 937 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 938 if (err != 0) 939 return (err); 940 941 for (i = 0; i < MV_WIN_DDR_MAX; i++) 942 window_valid[i] = 0; 943 944 /* Try to match entries from device tree with settings from u-boot */ 945 for (i = 0; i < mr_cnt; i++) { 946 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 947 if (ddr_is_active(j) && 948 (ddr_base(j) == mr[i].mr_start) && 949 (ddr_size(j) == mr[i].mr_size)) { 950 window_valid[j] = 1; 951 valid_win_num++; 952 } 953 } 954 } 955 956 if (mr_cnt != valid_win_num) 957 return (EINVAL); 958 959 /* Destroy windows without corresponding device tree entry */ 960 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 961 if (ddr_is_active(j) && (window_valid[j] != 1)) { 962 printf("Disabling SDRAM decoding window: %d\n", j); 963 ddr_disable(j); 964 } 965 } 966 967 return (0); 968 } 969 #endif 970 /* 971 * Check if we're able to cover all active DDR banks. 972 */ 973 static int 974 decode_win_can_cover_ddr(int max) 975 { 976 int i, c; 977 978 c = 0; 979 for (i = 0; i < MV_WIN_DDR_MAX; i++) 980 if (ddr_is_active(i)) 981 c++; 982 983 if (c > max) { 984 printf("Unable to cover all active DDR banks: " 985 "%d, available windows: %d\n", c, max); 986 return (0); 987 } 988 989 return (1); 990 } 991 992 /************************************************************************** 993 * DDR windows routines 994 **************************************************************************/ 995 int 996 ddr_is_active(int i) 997 { 998 999 if (ddr_sz_read(i) & 0x1) 1000 return (1); 1001 1002 return (0); 1003 } 1004 1005 void 1006 ddr_disable(int i) 1007 { 1008 1009 ddr_sz_write(i, 0); 1010 ddr_br_write(i, 0); 1011 } 1012 1013 uint32_t 1014 ddr_base(int i) 1015 { 1016 1017 return (ddr_br_read(i) & 0xff000000); 1018 } 1019 1020 uint32_t 1021 ddr_size(int i) 1022 { 1023 1024 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1025 } 1026 1027 uint32_t 1028 ddr_attr(int i) 1029 { 1030 uint32_t dev, rev; 1031 1032 soc_id(&dev, &rev); 1033 if (dev == MV_DEV_88RC8180) 1034 return ((ddr_sz_read(i) & 0xf0) >> 4); 1035 if (dev == MV_DEV_88F6781) 1036 return (0); 1037 1038 return (i == 0 ? 0xe : 1039 (i == 1 ? 0xd : 1040 (i == 2 ? 0xb : 1041 (i == 3 ? 0x7 : 0xff)))); 1042 } 1043 1044 uint32_t 1045 ddr_target(int i) 1046 { 1047 uint32_t dev, rev; 1048 1049 soc_id(&dev, &rev); 1050 if (dev == MV_DEV_88RC8180) { 1051 i = (ddr_sz_read(i) & 0xf0) >> 4; 1052 return (i == 0xe ? 0xc : 1053 (i == 0xd ? 0xd : 1054 (i == 0xb ? 0xe : 1055 (i == 0x7 ? 0xf : 0xc)))); 1056 } 1057 1058 /* 1059 * On SOCs other than 88RC8180 Mbus unit ID for 1060 * DDR SDRAM controller is always 0x0. 1061 */ 1062 return (0); 1063 } 1064 1065 /************************************************************************** 1066 * USB windows routines 1067 **************************************************************************/ 1068 static int 1069 decode_win_usb_valid(void) 1070 { 1071 1072 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1073 } 1074 1075 static void 1076 decode_win_usb_dump(u_long base) 1077 { 1078 int i; 1079 1080 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1081 return; 1082 1083 for (i = 0; i < MV_WIN_USB_MAX; i++) 1084 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1085 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1086 } 1087 1088 /* 1089 * Set USB decode windows. 1090 */ 1091 static void 1092 decode_win_usb_setup(u_long base) 1093 { 1094 uint32_t br, cr; 1095 int i, j; 1096 1097 1098 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1099 return; 1100 1101 usb_port++; 1102 1103 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1104 win_usb_cr_write(base, i, 0); 1105 win_usb_br_write(base, i, 0); 1106 } 1107 1108 /* Only access to active DRAM banks is required */ 1109 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1110 if (ddr_is_active(i)) { 1111 br = ddr_base(i); 1112 /* 1113 * XXX for 6281 we should handle Mbus write 1114 * burst limit field in the ctrl reg 1115 */ 1116 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1117 (ddr_attr(i) << 8) | 1118 (ddr_target(i) << 4) | 1); 1119 1120 /* Set the first free USB window */ 1121 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1122 if (win_usb_cr_read(base, j) & 0x1) 1123 continue; 1124 1125 win_usb_br_write(base, j, br); 1126 win_usb_cr_write(base, j, cr); 1127 break; 1128 } 1129 } 1130 } 1131 } 1132 1133 /************************************************************************** 1134 * USB3 windows routines 1135 **************************************************************************/ 1136 #ifdef SOC_MV_ARMADA38X 1137 static int 1138 decode_win_usb3_valid(void) 1139 { 1140 1141 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1142 } 1143 1144 static void 1145 decode_win_usb3_dump(u_long base) 1146 { 1147 int i; 1148 1149 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1150 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1151 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1152 } 1153 1154 /* 1155 * Set USB3 decode windows 1156 */ 1157 static void 1158 decode_win_usb3_setup(u_long base) 1159 { 1160 uint32_t br, cr; 1161 int i, j; 1162 1163 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1164 win_usb3_cr_write(base, i, 0); 1165 win_usb3_br_write(base, i, 0); 1166 } 1167 1168 /* Only access to active DRAM banks is required */ 1169 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1170 if (ddr_is_active(i)) { 1171 br = ddr_base(i); 1172 cr = (((ddr_size(i) - 1) & 1173 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1174 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1175 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1176 IO_WIN_ENA_MASK); 1177 1178 /* Set the first free USB3.0 window */ 1179 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1180 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1181 continue; 1182 1183 win_usb3_br_write(base, j, br); 1184 win_usb3_cr_write(base, j, cr); 1185 break; 1186 } 1187 } 1188 } 1189 } 1190 #else 1191 /* 1192 * Provide dummy functions to satisfy the build 1193 * for SoCs not equipped with USB3 1194 */ 1195 static int 1196 decode_win_usb3_valid(void) 1197 { 1198 1199 return (1); 1200 } 1201 1202 static void 1203 decode_win_usb3_setup(u_long base) 1204 { 1205 } 1206 1207 static void 1208 decode_win_usb3_dump(u_long base) 1209 { 1210 } 1211 #endif 1212 /************************************************************************** 1213 * ETH windows routines 1214 **************************************************************************/ 1215 1216 static int 1217 win_eth_can_remap(int i) 1218 { 1219 1220 /* ETH encode windows 0-3 have remap capability */ 1221 if (i < 4) 1222 return (1); 1223 1224 return (0); 1225 } 1226 1227 static int 1228 eth_bare_read(uint32_t base, int i) 1229 { 1230 uint32_t v; 1231 1232 v = win_eth_bare_read(base); 1233 v &= (1 << i); 1234 1235 return (v >> i); 1236 } 1237 1238 static void 1239 eth_bare_write(uint32_t base, int i, int val) 1240 { 1241 uint32_t v; 1242 1243 v = win_eth_bare_read(base); 1244 v &= ~(1 << i); 1245 v |= (val << i); 1246 win_eth_bare_write(base, v); 1247 } 1248 1249 static void 1250 eth_epap_write(uint32_t base, int i, int val) 1251 { 1252 uint32_t v; 1253 1254 v = win_eth_epap_read(base); 1255 v &= ~(0x3 << (i * 2)); 1256 v |= (val << (i * 2)); 1257 win_eth_epap_write(base, v); 1258 } 1259 1260 static void 1261 decode_win_eth_dump(u_long base) 1262 { 1263 int i; 1264 1265 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1266 return; 1267 1268 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1269 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1270 win_eth_br_read(base, i), 1271 win_eth_sz_read(base, i)); 1272 1273 if (win_eth_can_remap(i)) 1274 printf(", ha 0x%08x", 1275 win_eth_har_read(base, i)); 1276 1277 printf("\n"); 1278 } 1279 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1280 win_eth_bare_read(base), 1281 win_eth_epap_read(base)); 1282 } 1283 1284 #if defined(SOC_MV_LOKIPLUS) 1285 #define MV_WIN_ETH_DDR_TRGT(n) 0 1286 #else 1287 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1288 #endif 1289 1290 static void 1291 decode_win_eth_setup(u_long base) 1292 { 1293 uint32_t br, sz; 1294 int i, j; 1295 1296 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1297 return; 1298 1299 eth_port++; 1300 1301 /* Disable, clear and revoke protection for all ETH windows */ 1302 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1303 1304 eth_bare_write(base, i, 1); 1305 eth_epap_write(base, i, 0); 1306 win_eth_br_write(base, i, 0); 1307 win_eth_sz_write(base, i, 0); 1308 if (win_eth_can_remap(i)) 1309 win_eth_har_write(base, i, 0); 1310 } 1311 1312 /* Only access to active DRAM banks is required */ 1313 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1314 if (ddr_is_active(i)) { 1315 1316 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1317 sz = ((ddr_size(i) - 1) & 0xffff0000); 1318 1319 /* Set the first free ETH window */ 1320 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1321 if (eth_bare_read(base, j) == 0) 1322 continue; 1323 1324 win_eth_br_write(base, j, br); 1325 win_eth_sz_write(base, j, sz); 1326 1327 /* XXX remapping ETH windows not supported */ 1328 1329 /* Set protection RW */ 1330 eth_epap_write(base, j, 0x3); 1331 1332 /* Enable window */ 1333 eth_bare_write(base, j, 0); 1334 break; 1335 } 1336 } 1337 } 1338 1339 static int 1340 decode_win_eth_valid(void) 1341 { 1342 1343 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1344 } 1345 1346 /************************************************************************** 1347 * PCIE windows routines 1348 **************************************************************************/ 1349 1350 void 1351 decode_win_pcie_setup(u_long base) 1352 { 1353 uint32_t size = 0, ddrbase = ~0; 1354 uint32_t cr, br; 1355 int i, j; 1356 1357 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1358 pcie_bar_br_write(base, i, 1359 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1360 if (i < 3) 1361 pcie_bar_brh_write(base, i, 0); 1362 if (i > 0) 1363 pcie_bar_cr_write(base, i, 0); 1364 } 1365 1366 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1367 win_pcie_cr_write(base, i, 0); 1368 win_pcie_br_write(base, i, 0); 1369 win_pcie_remap_write(base, i, 0); 1370 } 1371 1372 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1373 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1374 & MV_PCIE_ROOT_CMPLX) == 0) { 1375 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1376 return; 1377 } 1378 1379 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1380 if (ddr_is_active(i)) { 1381 /* Map DDR to BAR 1 */ 1382 cr = (ddr_size(i) - 1) & 0xffff0000; 1383 size += ddr_size(i) & 0xffff0000; 1384 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1385 br = ddr_base(i); 1386 if (br < ddrbase) 1387 ddrbase = br; 1388 1389 /* Use the first available PCIE window */ 1390 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1391 if (win_pcie_cr_read(base, j) != 0) 1392 continue; 1393 1394 win_pcie_br_write(base, j, br); 1395 win_pcie_cr_write(base, j, cr); 1396 break; 1397 } 1398 } 1399 } 1400 1401 /* 1402 * Upper 16 bits in BAR register is interpreted as BAR size 1403 * (in 64 kB units) plus 64kB, so subtract 0x10000 1404 * form value passed to register to get correct value. 1405 */ 1406 size -= 0x10000; 1407 pcie_bar_cr_write(base, 1, size | 1); 1408 pcie_bar_br_write(base, 1, ddrbase | 1409 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1410 pcie_bar_br_write(base, 0, fdt_immr_pa | 1411 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1412 } 1413 1414 static int 1415 decode_win_pcie_valid(void) 1416 { 1417 1418 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1419 } 1420 1421 /************************************************************************** 1422 * IDMA windows routines 1423 **************************************************************************/ 1424 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1425 static int 1426 idma_bare_read(u_long base, int i) 1427 { 1428 uint32_t v; 1429 1430 v = win_idma_bare_read(base); 1431 v &= (1 << i); 1432 1433 return (v >> i); 1434 } 1435 1436 static void 1437 idma_bare_write(u_long base, int i, int val) 1438 { 1439 uint32_t v; 1440 1441 v = win_idma_bare_read(base); 1442 v &= ~(1 << i); 1443 v |= (val << i); 1444 win_idma_bare_write(base, v); 1445 } 1446 1447 /* 1448 * Sets channel protection 'val' for window 'w' on channel 'c' 1449 */ 1450 static void 1451 idma_cap_write(u_long base, int c, int w, int val) 1452 { 1453 uint32_t v; 1454 1455 v = win_idma_cap_read(base, c); 1456 v &= ~(0x3 << (w * 2)); 1457 v |= (val << (w * 2)); 1458 win_idma_cap_write(base, c, v); 1459 } 1460 1461 /* 1462 * Set protection 'val' on all channels for window 'w' 1463 */ 1464 static void 1465 idma_set_prot(u_long base, int w, int val) 1466 { 1467 int c; 1468 1469 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1470 idma_cap_write(base, c, w, val); 1471 } 1472 1473 static int 1474 win_idma_can_remap(int i) 1475 { 1476 1477 /* IDMA decode windows 0-3 have remap capability */ 1478 if (i < 4) 1479 return (1); 1480 1481 return (0); 1482 } 1483 1484 void 1485 decode_win_idma_setup(u_long base) 1486 { 1487 uint32_t br, sz; 1488 int i, j; 1489 1490 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1491 return; 1492 /* 1493 * Disable and clear all IDMA windows, revoke protection for all channels 1494 */ 1495 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1496 1497 idma_bare_write(base, i, 1); 1498 win_idma_br_write(base, i, 0); 1499 win_idma_sz_write(base, i, 0); 1500 if (win_idma_can_remap(i) == 1) 1501 win_idma_har_write(base, i, 0); 1502 } 1503 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1504 win_idma_cap_write(base, i, 0); 1505 1506 /* 1507 * Set up access to all active DRAM banks 1508 */ 1509 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1510 if (ddr_is_active(i)) { 1511 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1512 sz = ((ddr_size(i) - 1) & 0xffff0000); 1513 1514 /* Place DDR entries in non-remapped windows */ 1515 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1516 if (win_idma_can_remap(j) != 1 && 1517 idma_bare_read(base, j) == 1) { 1518 1519 /* Configure window */ 1520 win_idma_br_write(base, j, br); 1521 win_idma_sz_write(base, j, sz); 1522 1523 /* Set protection RW on all channels */ 1524 idma_set_prot(base, j, 0x3); 1525 1526 /* Enable window */ 1527 idma_bare_write(base, j, 0); 1528 break; 1529 } 1530 } 1531 1532 /* 1533 * Remaining targets -- from statically defined table 1534 */ 1535 for (i = 0; i < idma_wins_no; i++) 1536 if (idma_wins[i].target > 0) { 1537 br = (idma_wins[i].base & 0xffff0000) | 1538 (idma_wins[i].attr << 8) | idma_wins[i].target; 1539 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1540 1541 /* Set the first free IDMA window */ 1542 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1543 if (idma_bare_read(base, j) == 0) 1544 continue; 1545 1546 /* Configure window */ 1547 win_idma_br_write(base, j, br); 1548 win_idma_sz_write(base, j, sz); 1549 if (win_idma_can_remap(j) && 1550 idma_wins[j].remap >= 0) 1551 win_idma_har_write(base, j, 1552 idma_wins[j].remap); 1553 1554 /* Set protection RW on all channels */ 1555 idma_set_prot(base, j, 0x3); 1556 1557 /* Enable window */ 1558 idma_bare_write(base, j, 0); 1559 break; 1560 } 1561 } 1562 } 1563 1564 int 1565 decode_win_idma_valid(void) 1566 { 1567 const struct decode_win *wintab; 1568 int c, i, j, rv; 1569 uint32_t b, e, s; 1570 1571 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1572 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1573 return (0); 1574 } 1575 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1576 if (ddr_is_active(i)) 1577 c++; 1578 1579 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1580 printf("IDMA windows: too many entries: %d, available: %d\n", 1581 idma_wins_no, MV_WIN_IDMA_MAX - c); 1582 return (0); 1583 } 1584 1585 wintab = idma_wins; 1586 rv = 1; 1587 for (i = 0; i < idma_wins_no; i++, wintab++) { 1588 1589 if (wintab->target == 0) { 1590 printf("IDMA window#%d: DDR target window is not " 1591 "supposed to be reprogrammed!\n", i); 1592 rv = 0; 1593 } 1594 1595 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1596 printf("IDMA window#%d: not capable of remapping, but " 1597 "val 0x%08x defined\n", i, wintab->remap); 1598 rv = 0; 1599 } 1600 1601 s = wintab->size; 1602 b = wintab->base; 1603 e = b + s - 1; 1604 if (s > (0xFFFFFFFF - b + 1)) { 1605 /* XXX this boundary check should account for 64bit and 1606 * remapping.. */ 1607 printf("IDMA window#%d: no space for size 0x%08x at " 1608 "0x%08x\n", i, s, b); 1609 rv = 0; 1610 continue; 1611 } 1612 1613 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1614 if (j >= 0) { 1615 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1616 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1617 idma_wins[j].base, 1618 idma_wins[j].base + idma_wins[j].size - 1); 1619 rv = 0; 1620 } 1621 } 1622 1623 return (rv); 1624 } 1625 1626 void 1627 decode_win_idma_dump(u_long base) 1628 { 1629 int i; 1630 1631 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1632 return; 1633 1634 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1635 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1636 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1637 1638 if (win_idma_can_remap(i)) 1639 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1640 1641 printf("\n"); 1642 } 1643 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1644 printf("IDMA channel#%d: ap 0x%08x\n", i, 1645 win_idma_cap_read(base, i)); 1646 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1647 } 1648 #else 1649 1650 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1651 int 1652 decode_win_idma_valid(void) 1653 { 1654 1655 return (1); 1656 } 1657 1658 void 1659 decode_win_idma_setup(u_long base) 1660 { 1661 } 1662 1663 void 1664 decode_win_idma_dump(u_long base) 1665 { 1666 } 1667 #endif 1668 1669 /************************************************************************** 1670 * XOR windows routines 1671 **************************************************************************/ 1672 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1673 static int 1674 xor_ctrl_read(u_long base, int i, int c, int e) 1675 { 1676 uint32_t v; 1677 v = win_xor_ctrl_read(base, c, e); 1678 v &= (1 << i); 1679 1680 return (v >> i); 1681 } 1682 1683 static void 1684 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1685 { 1686 uint32_t v; 1687 1688 v = win_xor_ctrl_read(base, c, e); 1689 v &= ~(1 << i); 1690 v |= (val << i); 1691 win_xor_ctrl_write(base, c, e, v); 1692 } 1693 1694 /* 1695 * Set channel protection 'val' for window 'w' on channel 'c' 1696 */ 1697 static void 1698 xor_chan_write(u_long base, int c, int e, int w, int val) 1699 { 1700 uint32_t v; 1701 1702 v = win_xor_ctrl_read(base, c, e); 1703 v &= ~(0x3 << (w * 2 + 16)); 1704 v |= (val << (w * 2 + 16)); 1705 win_xor_ctrl_write(base, c, e, v); 1706 } 1707 1708 /* 1709 * Set protection 'val' on all channels for window 'w' on engine 'e' 1710 */ 1711 static void 1712 xor_set_prot(u_long base, int w, int e, int val) 1713 { 1714 int c; 1715 1716 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1717 xor_chan_write(base, c, e, w, val); 1718 } 1719 1720 static int 1721 win_xor_can_remap(int i) 1722 { 1723 1724 /* XOR decode windows 0-3 have remap capability */ 1725 if (i < 4) 1726 return (1); 1727 1728 return (0); 1729 } 1730 1731 static int 1732 xor_max_eng(void) 1733 { 1734 uint32_t dev, rev; 1735 1736 soc_id(&dev, &rev); 1737 switch (dev) { 1738 case MV_DEV_88F6281: 1739 case MV_DEV_88F6282: 1740 case MV_DEV_MV78130: 1741 case MV_DEV_MV78160: 1742 case MV_DEV_MV78230: 1743 case MV_DEV_MV78260: 1744 case MV_DEV_MV78460: 1745 return (2); 1746 case MV_DEV_MV78100: 1747 case MV_DEV_MV78100_Z0: 1748 return (1); 1749 default: 1750 return (0); 1751 } 1752 } 1753 1754 static void 1755 xor_active_dram(u_long base, int c, int e, int *window) 1756 { 1757 uint32_t br, sz; 1758 int i, m, w; 1759 1760 /* 1761 * Set up access to all active DRAM banks 1762 */ 1763 m = xor_max_eng(); 1764 for (i = 0; i < m; i++) 1765 if (ddr_is_active(i)) { 1766 br = ddr_base(i) | (ddr_attr(i) << 8) | 1767 ddr_target(i); 1768 sz = ((ddr_size(i) - 1) & 0xffff0000); 1769 1770 /* Place DDR entries in non-remapped windows */ 1771 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1772 if (win_xor_can_remap(w) != 1 && 1773 (xor_ctrl_read(base, w, c, e) == 0) && 1774 w > *window) { 1775 /* Configure window */ 1776 win_xor_br_write(base, w, e, br); 1777 win_xor_sz_write(base, w, e, sz); 1778 1779 /* Set protection RW on all channels */ 1780 xor_set_prot(base, w, e, 0x3); 1781 1782 /* Enable window */ 1783 xor_ctrl_write(base, w, c, e, 1); 1784 (*window)++; 1785 break; 1786 } 1787 } 1788 } 1789 1790 void 1791 decode_win_xor_setup(u_long base) 1792 { 1793 uint32_t br, sz; 1794 int i, j, z, e = 1, m, window; 1795 1796 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1797 return; 1798 1799 /* 1800 * Disable and clear all XOR windows, revoke protection for all 1801 * channels 1802 */ 1803 m = xor_max_eng(); 1804 for (j = 0; j < m; j++, e--) { 1805 1806 /* Number of non-remaped windows */ 1807 window = MV_XOR_NON_REMAP - 1; 1808 1809 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1810 win_xor_br_write(base, i, e, 0); 1811 win_xor_sz_write(base, i, e, 0); 1812 } 1813 1814 if (win_xor_can_remap(i) == 1) 1815 win_xor_har_write(base, i, e, 0); 1816 1817 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1818 win_xor_ctrl_write(base, i, e, 0); 1819 xor_active_dram(base, i, e, &window); 1820 } 1821 1822 /* 1823 * Remaining targets -- from a statically defined table 1824 */ 1825 for (i = 0; i < xor_wins_no; i++) 1826 if (xor_wins[i].target > 0) { 1827 br = (xor_wins[i].base & 0xffff0000) | 1828 (xor_wins[i].attr << 8) | 1829 xor_wins[i].target; 1830 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1831 1832 /* Set the first free XOR window */ 1833 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1834 if (xor_ctrl_read(base, z, 0, e) && 1835 xor_ctrl_read(base, z, 1, e)) 1836 continue; 1837 1838 /* Configure window */ 1839 win_xor_br_write(base, z, e, br); 1840 win_xor_sz_write(base, z, e, sz); 1841 if (win_xor_can_remap(z) && 1842 xor_wins[z].remap >= 0) 1843 win_xor_har_write(base, z, e, 1844 xor_wins[z].remap); 1845 1846 /* Set protection RW on all channels */ 1847 xor_set_prot(base, z, e, 0x3); 1848 1849 /* Enable window */ 1850 xor_ctrl_write(base, z, 0, e, 1); 1851 xor_ctrl_write(base, z, 1, e, 1); 1852 break; 1853 } 1854 } 1855 } 1856 } 1857 1858 int 1859 decode_win_xor_valid(void) 1860 { 1861 const struct decode_win *wintab; 1862 int c, i, j, rv; 1863 uint32_t b, e, s; 1864 1865 if (xor_wins_no > MV_WIN_XOR_MAX) { 1866 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1867 return (0); 1868 } 1869 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1870 if (ddr_is_active(i)) 1871 c++; 1872 1873 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1874 printf("XOR windows: too many entries: %d, available: %d\n", 1875 xor_wins_no, MV_WIN_IDMA_MAX - c); 1876 return (0); 1877 } 1878 1879 wintab = xor_wins; 1880 rv = 1; 1881 for (i = 0; i < xor_wins_no; i++, wintab++) { 1882 1883 if (wintab->target == 0) { 1884 printf("XOR window#%d: DDR target window is not " 1885 "supposed to be reprogrammed!\n", i); 1886 rv = 0; 1887 } 1888 1889 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1890 printf("XOR window#%d: not capable of remapping, but " 1891 "val 0x%08x defined\n", i, wintab->remap); 1892 rv = 0; 1893 } 1894 1895 s = wintab->size; 1896 b = wintab->base; 1897 e = b + s - 1; 1898 if (s > (0xFFFFFFFF - b + 1)) { 1899 /* 1900 * XXX this boundary check should account for 64bit 1901 * and remapping.. 1902 */ 1903 printf("XOR window#%d: no space for size 0x%08x at " 1904 "0x%08x\n", i, s, b); 1905 rv = 0; 1906 continue; 1907 } 1908 1909 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 1910 if (j >= 0) { 1911 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 1912 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1913 xor_wins[j].base, 1914 xor_wins[j].base + xor_wins[j].size - 1); 1915 rv = 0; 1916 } 1917 } 1918 1919 return (rv); 1920 } 1921 1922 void 1923 decode_win_xor_dump(u_long base) 1924 { 1925 int i, j; 1926 int e = 1; 1927 1928 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1929 return; 1930 1931 for (j = 0; j < xor_max_eng(); j++, e--) { 1932 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1933 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 1934 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 1935 1936 if (win_xor_can_remap(i)) 1937 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 1938 1939 printf("\n"); 1940 } 1941 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 1942 printf("XOR control#%d: 0x%08x\n", i, 1943 win_xor_ctrl_read(base, i, e)); 1944 } 1945 } 1946 1947 #else 1948 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 1949 static int 1950 decode_win_xor_valid(void) 1951 { 1952 1953 return (1); 1954 } 1955 1956 static void 1957 decode_win_xor_setup(u_long base) 1958 { 1959 } 1960 1961 static void 1962 decode_win_xor_dump(u_long base) 1963 { 1964 } 1965 #endif 1966 1967 /************************************************************************** 1968 * SATA windows routines 1969 **************************************************************************/ 1970 static void 1971 decode_win_sata_setup(u_long base) 1972 { 1973 uint32_t cr, br; 1974 int i, j; 1975 1976 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 1977 return; 1978 1979 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 1980 win_sata_cr_write(base, i, 0); 1981 win_sata_br_write(base, i, 0); 1982 } 1983 1984 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1985 if (ddr_is_active(i)) { 1986 cr = ((ddr_size(i) - 1) & 0xffff0000) | 1987 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1988 br = ddr_base(i); 1989 1990 /* Use the first available SATA window */ 1991 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 1992 if ((win_sata_cr_read(base, j) & 1) != 0) 1993 continue; 1994 1995 win_sata_br_write(base, j, br); 1996 win_sata_cr_write(base, j, cr); 1997 break; 1998 } 1999 } 2000 } 2001 2002 static int 2003 decode_win_sata_valid(void) 2004 { 2005 uint32_t dev, rev; 2006 2007 soc_id(&dev, &rev); 2008 if (dev == MV_DEV_88F5281) 2009 return (1); 2010 2011 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2012 } 2013 2014 /************************************************************************** 2015 * FDT parsing routines. 2016 **************************************************************************/ 2017 2018 static int 2019 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2020 int *tuplesize) 2021 { 2022 phandle_t node; 2023 pcell_t addr_cells, par_addr_cells, size_cells; 2024 int len, tuple_size, tuples_count; 2025 2026 node = OF_finddevice(nodename); 2027 if (node == -1) 2028 return (EINVAL); 2029 2030 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2031 return (ENXIO); 2032 2033 par_addr_cells = fdt_parent_addr_cells(node); 2034 if (par_addr_cells > 2) 2035 return (ERANGE); 2036 2037 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2038 size_cells); 2039 2040 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2041 len = OF_getprop(node, "ranges", buf, size); 2042 2043 /* 2044 * XXX this does not handle the empty 'ranges;' case, which is 2045 * legitimate and should be allowed. 2046 */ 2047 tuples_count = len / tuple_size; 2048 if (tuples_count <= 0) 2049 return (ERANGE); 2050 2051 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2052 return (ERANGE); 2053 2054 *tuples = tuples_count; 2055 *tuplesize = tuple_size; 2056 return (0); 2057 } 2058 2059 static int 2060 win_cpu_from_dt(void) 2061 { 2062 pcell_t ranges[48]; 2063 phandle_t node; 2064 int i, entry_size, err, t, tuple_size, tuples; 2065 u_long sram_base, sram_size; 2066 2067 t = 0; 2068 /* Retrieve 'ranges' property of '/localbus' node. */ 2069 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2070 &tuples, &tuple_size)) == 0) { 2071 /* 2072 * Fill CPU decode windows table. 2073 */ 2074 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2075 2076 entry_size = tuple_size / sizeof(pcell_t); 2077 cpu_wins_no = tuples; 2078 2079 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2080 cpu_win_tbl[t].target = 1; 2081 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2082 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2083 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2084 cpu_win_tbl[t].remap = ~0; 2085 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2086 "size = 0x%0x remap = 0x%0x\n", 2087 cpu_win_tbl[t].target, 2088 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2089 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2090 } 2091 } 2092 2093 /* 2094 * Retrieve CESA SRAM data. 2095 */ 2096 if ((node = OF_finddevice("sram")) != -1) 2097 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2098 goto moveon; 2099 2100 if ((node = OF_finddevice("/")) == 0) 2101 return (ENXIO); 2102 2103 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2104 /* SRAM block is not always present. */ 2105 return (0); 2106 moveon: 2107 sram_base = sram_size = 0; 2108 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2109 return (EINVAL); 2110 2111 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2112 #ifdef SOC_MV_ARMADA38X 2113 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2114 #else 2115 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2116 #endif 2117 cpu_win_tbl[t].base = sram_base; 2118 cpu_win_tbl[t].size = sram_size; 2119 cpu_win_tbl[t].remap = ~0; 2120 cpu_wins_no++; 2121 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2122 2123 /* Check if there is a second CESA node */ 2124 while ((node = OF_peer(node)) != 0) { 2125 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2126 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2127 return (EINVAL); 2128 break; 2129 } 2130 } 2131 2132 if (node == 0) 2133 return (0); 2134 2135 t++; 2136 if (t >= nitems(cpu_win_tbl)) { 2137 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2138 return (ENOMEM); 2139 } 2140 2141 /* Configure window for CESA1 */ 2142 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2143 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2144 cpu_win_tbl[t].base = sram_base; 2145 cpu_win_tbl[t].size = sram_size; 2146 cpu_win_tbl[t].remap = ~0; 2147 cpu_wins_no++; 2148 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2149 2150 return (0); 2151 } 2152 2153 static int 2154 fdt_win_setup(void) 2155 { 2156 phandle_t node, child; 2157 struct soc_node_spec *soc_node; 2158 u_long size, base; 2159 int err, i; 2160 2161 node = OF_finddevice("/"); 2162 if (node == -1) 2163 panic("fdt_win_setup: no root node"); 2164 2165 /* 2166 * Traverse through all children of root and simple-bus nodes. 2167 * For each found device retrieve decode windows data (if applicable). 2168 */ 2169 child = OF_child(node); 2170 while (child != 0) { 2171 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2172 2173 soc_node = &soc_nodes[i]; 2174 2175 if (!ofw_bus_node_is_compatible(child,soc_node->compat)) 2176 continue; 2177 2178 err = fdt_regsize(child, &base, &size); 2179 if (err != 0) 2180 return (err); 2181 2182 base = (base & 0x000fffff) | fdt_immr_va; 2183 if (soc_node->decode_handler != NULL) 2184 soc_node->decode_handler(base); 2185 else 2186 return (ENXIO); 2187 2188 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2189 soc_node->dump_handler(base); 2190 } 2191 2192 /* 2193 * Once done with root-level children let's move down to 2194 * simple-bus and its children. 2195 */ 2196 child = OF_peer(child); 2197 if ((child == 0) && (node == OF_finddevice("/"))) { 2198 node = fdt_find_compatible(node, "simple-bus", 0); 2199 if (node == 0) 2200 return (ENXIO); 2201 child = OF_child(node); 2202 } 2203 /* 2204 * Next, move one more level down to internal-regs node (if 2205 * it is present) and its children. This node also have 2206 * "simple-bus" compatible. 2207 */ 2208 if ((child == 0) && (node == OF_finddevice("simple-bus"))) { 2209 node = fdt_find_compatible(node, "simple-bus", 0); 2210 if (node == 0) 2211 return (0); 2212 child = OF_child(node); 2213 } 2214 } 2215 2216 return (0); 2217 } 2218 2219 static void 2220 fdt_fixup_busfreq(phandle_t root) 2221 { 2222 phandle_t sb; 2223 pcell_t freq; 2224 2225 freq = cpu_to_fdt32(get_tclk()); 2226 2227 /* 2228 * Fix bus speed in cpu node 2229 */ 2230 if ((sb = OF_finddevice("cpu")) != 0) 2231 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2232 OF_setprop(sb, "bus-frequency", (void *)&freq, 2233 sizeof(freq)); 2234 2235 /* 2236 * This fixup sets the simple-bus bus-frequency property. 2237 */ 2238 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2239 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2240 } 2241 2242 static void 2243 fdt_fixup_ranges(phandle_t root) 2244 { 2245 phandle_t node; 2246 pcell_t par_addr_cells, addr_cells, size_cells; 2247 pcell_t ranges[3], reg[2], *rangesptr; 2248 int len, tuple_size, tuples_count; 2249 uint32_t base; 2250 2251 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2252 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2253 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2254 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2255 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2256 addr_cells + size_cells); 2257 len = OF_getprop(node, "ranges", ranges, 2258 sizeof(ranges)); 2259 tuples_count = len / tuple_size; 2260 /* Unexpected settings are not supported */ 2261 if (tuples_count != 1) 2262 goto fixup_failed; 2263 2264 rangesptr = &ranges[0]; 2265 rangesptr += par_addr_cells; 2266 base = fdt_data_get((void *)rangesptr, addr_cells); 2267 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2268 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2269 sizeof(ranges)) < 0) 2270 goto fixup_failed; 2271 } 2272 } 2273 2274 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2275 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2276 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2277 &size_cells) == 0) { 2278 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2279 size_cells); 2280 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2281 tuples_count = len / tuple_size; 2282 /* Unexpected settings are not supported */ 2283 if (tuples_count != 1) 2284 goto fixup_failed; 2285 2286 base = fdt_data_get((void *)®[0], par_addr_cells); 2287 base &= ~0xFF000000; 2288 base |= fdt_immr_pa; 2289 reg[0] = cpu_to_fdt32(base); 2290 if (OF_setprop(node, "reg", (void *)®[0], 2291 sizeof(reg)) < 0) 2292 goto fixup_failed; 2293 } 2294 } 2295 /* Fix-up succeeded. May return and continue */ 2296 return; 2297 2298 fixup_failed: 2299 while (1) { 2300 /* 2301 * In case of any error while fixing ranges just hang. 2302 * 1. No message can be displayed yet since console 2303 * is not initialized. 2304 * 2. Going further will cause failure on bus_space_map() 2305 * relying on the wrong ranges or data abort when 2306 * accessing PCIe registers. 2307 */ 2308 } 2309 } 2310 2311 struct fdt_fixup_entry fdt_fixup_table[] = { 2312 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2313 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2314 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2315 { NULL, NULL } 2316 }; 2317 2318 #ifndef INTRNG 2319 static int 2320 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2321 int *pol) 2322 { 2323 2324 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2325 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2326 return (ENXIO); 2327 2328 *interrupt = fdt32_to_cpu(intr[0]); 2329 *trig = INTR_TRIGGER_CONFORM; 2330 *pol = INTR_POLARITY_CONFORM; 2331 2332 return (0); 2333 } 2334 2335 fdt_pic_decode_t fdt_pic_table[] = { 2336 #ifdef SOC_MV_ARMADA38X 2337 &gic_decode_fdt, 2338 #endif 2339 &fdt_pic_decode_ic, 2340 NULL 2341 }; 2342 #endif 2343 2344 uint64_t 2345 get_sar_value(void) 2346 { 2347 uint32_t sar_low, sar_high; 2348 2349 #if defined(SOC_MV_ARMADAXP) 2350 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2351 SAMPLE_AT_RESET_HI); 2352 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2353 SAMPLE_AT_RESET_LO); 2354 #elif defined(SOC_MV_ARMADA38X) 2355 sar_high = 0; 2356 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2357 SAMPLE_AT_RESET); 2358 #else 2359 /* 2360 * TODO: Add getting proper values for other SoC configurations 2361 */ 2362 sar_high = 0; 2363 sar_low = 0; 2364 #endif 2365 2366 return (((uint64_t)sar_high << 32) | sar_low); 2367 } 2368