1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cpu_valid(void); 80 static int decode_win_usb_valid(void); 81 static int decode_win_usb3_valid(void); 82 static int decode_win_eth_valid(void); 83 static int decode_win_pcie_valid(void); 84 static int decode_win_sata_valid(void); 85 86 static int decode_win_idma_valid(void); 87 static int decode_win_xor_valid(void); 88 89 static void decode_win_cpu_setup(void); 90 #ifdef SOC_MV_ARMADAXP 91 static int decode_win_sdram_fixup(void); 92 #endif 93 static void decode_win_usb_setup(u_long); 94 static void decode_win_usb3_setup(u_long); 95 static void decode_win_eth_setup(u_long); 96 static void decode_win_sata_setup(u_long); 97 static void decode_win_ahci_setup(u_long); 98 99 static void decode_win_idma_setup(u_long); 100 static void decode_win_xor_setup(u_long); 101 102 static void decode_win_usb_dump(u_long); 103 static void decode_win_usb3_dump(u_long); 104 static void decode_win_eth_dump(u_long base); 105 static void decode_win_idma_dump(u_long base); 106 static void decode_win_xor_dump(u_long base); 107 static void decode_win_ahci_dump(u_long base); 108 109 static int fdt_get_ranges(const char *, void *, int, int *, int *); 110 #ifdef SOC_MV_ARMADA38X 111 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 112 int *trig, int *pol); 113 #endif 114 115 static int win_cpu_from_dt(void); 116 static int fdt_win_setup(void); 117 118 static uint32_t dev_mask = 0; 119 static int cpu_wins_no = 0; 120 static int eth_port = 0; 121 static int usb_port = 0; 122 123 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 124 125 const struct decode_win *cpu_wins = cpu_win_tbl; 126 127 typedef void (*decode_win_setup_t)(u_long); 128 typedef void (*dump_win_t)(u_long); 129 130 struct soc_node_spec { 131 const char *compat; 132 decode_win_setup_t decode_handler; 133 dump_win_t dump_handler; 134 }; 135 136 static struct soc_node_spec soc_nodes[] = { 137 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 138 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 139 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 140 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 141 { "mrvl,sata", &decode_win_sata_setup, NULL }, 142 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 143 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 144 { "mrvl,pcie", &decode_win_pcie_setup, NULL }, 145 { NULL, NULL, NULL }, 146 }; 147 148 struct fdt_pm_mask_entry { 149 char *compat; 150 uint32_t mask; 151 }; 152 153 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 154 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 155 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 156 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 157 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 158 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 159 { "mrvl,xor", CPU_PM_CTRL_XOR }, 160 { "mrvl,sata", CPU_PM_CTRL_SATA }, 161 162 { NULL, 0 } 163 }; 164 165 static __inline int 166 pm_is_disabled(uint32_t mask) 167 { 168 #if defined(SOC_MV_KIRKWOOD) 169 return (soc_power_ctrl_get(mask) == mask); 170 #else 171 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 172 #endif 173 } 174 175 /* 176 * Disable device using power management register. 177 * 1 - Device Power On 178 * 0 - Device Power Off 179 * Mask can be set in loader. 180 * EXAMPLE: 181 * loader> set hw.pm-disable-mask=0x2 182 * 183 * Common mask: 184 * |-------------------------------| 185 * | Device | Kirkwood | Discovery | 186 * |-------------------------------| 187 * | USB0 | 0x00008 | 0x020000 | 188 * |-------------------------------| 189 * | USB1 | - | 0x040000 | 190 * |-------------------------------| 191 * | USB2 | - | 0x080000 | 192 * |-------------------------------| 193 * | GE0 | 0x00001 | 0x000002 | 194 * |-------------------------------| 195 * | GE1 | - | 0x000004 | 196 * |-------------------------------| 197 * | IDMA | - | 0x100000 | 198 * |-------------------------------| 199 * | XOR | 0x10000 | 0x200000 | 200 * |-------------------------------| 201 * | CESA | 0x20000 | 0x400000 | 202 * |-------------------------------| 203 * | SATA | 0x04000 | 0x004000 | 204 * --------------------------------| 205 * This feature can be used only on Kirkwood and Discovery 206 * machines. 207 */ 208 static __inline void 209 pm_disable_device(int mask) 210 { 211 #ifdef DIAGNOSTIC 212 uint32_t reg; 213 214 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 215 printf("Power Management Register: 0%x\n", reg); 216 217 reg &= ~mask; 218 soc_power_ctrl_set(reg); 219 printf("Device %x is disabled\n", mask); 220 221 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 222 printf("Power Management Register: 0%x\n", reg); 223 #endif 224 } 225 226 int 227 fdt_pm(phandle_t node) 228 { 229 uint32_t cpu_pm_ctrl; 230 int i, ena, compat; 231 232 ena = 1; 233 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 234 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 235 if (dev_mask & (1 << i)) 236 continue; 237 238 compat = ofw_bus_node_is_compatible(node, 239 fdt_pm_mask_table[i].compat); 240 #if defined(SOC_MV_KIRKWOOD) 241 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 242 dev_mask |= (1 << i); 243 ena = 0; 244 break; 245 } else if (compat) { 246 dev_mask |= (1 << i); 247 break; 248 } 249 #else 250 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 251 dev_mask |= (1 << i); 252 ena = 0; 253 break; 254 } else if (compat) { 255 dev_mask |= (1 << i); 256 break; 257 } 258 #endif 259 } 260 261 return (ena); 262 } 263 264 uint32_t 265 read_cpu_ctrl(uint32_t reg) 266 { 267 268 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 269 } 270 271 void 272 write_cpu_ctrl(uint32_t reg, uint32_t val) 273 { 274 275 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 276 } 277 278 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 279 uint32_t 280 read_cpu_mp_clocks(uint32_t reg) 281 { 282 283 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 284 } 285 286 void 287 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 288 { 289 290 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 291 } 292 293 uint32_t 294 read_cpu_misc(uint32_t reg) 295 { 296 297 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 298 } 299 300 void 301 write_cpu_misc(uint32_t reg, uint32_t val) 302 { 303 304 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 305 } 306 #endif 307 308 void 309 cpu_reset(void) 310 { 311 312 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 313 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 314 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 315 #else 316 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 317 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 318 #endif 319 while (1); 320 } 321 322 uint32_t 323 cpu_extra_feat(void) 324 { 325 uint32_t dev, rev; 326 uint32_t ef = 0; 327 328 soc_id(&dev, &rev); 329 330 switch (dev) { 331 case MV_DEV_88F6281: 332 case MV_DEV_88F6282: 333 case MV_DEV_88RC8180: 334 case MV_DEV_MV78100_Z0: 335 case MV_DEV_MV78100: 336 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 337 break; 338 case MV_DEV_88F5182: 339 case MV_DEV_88F5281: 340 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 341 break; 342 default: 343 if (bootverbose) 344 printf("This ARM Core does not support any extra features\n"); 345 } 346 347 return (ef); 348 } 349 350 /* 351 * Get the power status of device. This feature is only supported on 352 * Kirkwood and Discovery SoCs. 353 */ 354 uint32_t 355 soc_power_ctrl_get(uint32_t mask) 356 { 357 358 #if !defined(SOC_MV_ORION) 359 if (mask != CPU_PM_CTRL_NONE) 360 mask &= read_cpu_ctrl(CPU_PM_CTRL); 361 362 return (mask); 363 #else 364 return (mask); 365 #endif 366 } 367 368 /* 369 * Set the power status of device. This feature is only supported on 370 * Kirkwood and Discovery SoCs. 371 */ 372 void 373 soc_power_ctrl_set(uint32_t mask) 374 { 375 376 #if !defined(SOC_MV_ORION) 377 if (mask != CPU_PM_CTRL_NONE) 378 write_cpu_ctrl(CPU_PM_CTRL, mask); 379 #endif 380 } 381 382 void 383 soc_id(uint32_t *dev, uint32_t *rev) 384 { 385 386 /* 387 * Notice: system identifiers are available in the registers range of 388 * PCIE controller, so using this function is only allowed (and 389 * possible) after the internal registers range has been mapped in via 390 * devmap_bootstrap(). 391 */ 392 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 393 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 394 } 395 396 static void 397 soc_identify(void) 398 { 399 uint32_t d, r, size, mode; 400 const char *dev; 401 const char *rev; 402 403 soc_id(&d, &r); 404 405 printf("SOC: "); 406 if (bootverbose) 407 printf("(0x%4x:0x%02x) ", d, r); 408 409 rev = ""; 410 switch (d) { 411 case MV_DEV_88F5181: 412 dev = "Marvell 88F5181"; 413 if (r == 3) 414 rev = "B1"; 415 break; 416 case MV_DEV_88F5182: 417 dev = "Marvell 88F5182"; 418 if (r == 2) 419 rev = "A2"; 420 break; 421 case MV_DEV_88F5281: 422 dev = "Marvell 88F5281"; 423 if (r == 4) 424 rev = "D0"; 425 else if (r == 5) 426 rev = "D1"; 427 else if (r == 6) 428 rev = "D2"; 429 break; 430 case MV_DEV_88F6281: 431 dev = "Marvell 88F6281"; 432 if (r == 0) 433 rev = "Z0"; 434 else if (r == 2) 435 rev = "A0"; 436 else if (r == 3) 437 rev = "A1"; 438 break; 439 case MV_DEV_88RC8180: 440 dev = "Marvell 88RC8180"; 441 break; 442 case MV_DEV_88RC9480: 443 dev = "Marvell 88RC9480"; 444 break; 445 case MV_DEV_88RC9580: 446 dev = "Marvell 88RC9580"; 447 break; 448 case MV_DEV_88F6781: 449 dev = "Marvell 88F6781"; 450 if (r == 2) 451 rev = "Y0"; 452 break; 453 case MV_DEV_88F6282: 454 dev = "Marvell 88F6282"; 455 if (r == 0) 456 rev = "A0"; 457 else if (r == 1) 458 rev = "A1"; 459 break; 460 case MV_DEV_88F6828: 461 dev = "Marvell 88F6828"; 462 break; 463 case MV_DEV_88F6820: 464 dev = "Marvell 88F6820"; 465 break; 466 case MV_DEV_88F6810: 467 dev = "Marvell 88F6810"; 468 break; 469 case MV_DEV_MV78100_Z0: 470 dev = "Marvell MV78100 Z0"; 471 break; 472 case MV_DEV_MV78100: 473 dev = "Marvell MV78100"; 474 break; 475 case MV_DEV_MV78160: 476 dev = "Marvell MV78160"; 477 break; 478 case MV_DEV_MV78260: 479 dev = "Marvell MV78260"; 480 break; 481 case MV_DEV_MV78460: 482 dev = "Marvell MV78460"; 483 break; 484 default: 485 dev = "UNKNOWN"; 486 break; 487 } 488 489 printf("%s", dev); 490 if (*rev != '\0') 491 printf(" rev %s", rev); 492 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 493 494 mode = read_cpu_ctrl(CPU_CONFIG); 495 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 496 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 497 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 498 499 switch (d) { 500 case MV_DEV_88F6281: 501 case MV_DEV_88F6282: 502 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 503 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 504 mode ? "write-through" : "write-back"); 505 break; 506 case MV_DEV_MV78100: 507 mode = read_cpu_ctrl(CPU_CONTROL); 508 size = mode & CPU_CONTROL_L2_SIZE; 509 mode = mode & CPU_CONTROL_L2_MODE; 510 printf(" %s set-associative %s unified L2 cache\n", 511 size ? "256KB 4-way" : "512KB 8-way", 512 mode ? "write-through" : "write-back"); 513 break; 514 default: 515 break; 516 } 517 } 518 519 static void 520 platform_identify(void *dummy) 521 { 522 523 soc_identify(); 524 525 /* 526 * XXX Board identification e.g. read out from FPGA or similar should 527 * go here 528 */ 529 } 530 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 531 NULL); 532 533 #ifdef KDB 534 static void 535 mv_enter_debugger(void *dummy) 536 { 537 538 if (boothowto & RB_KDB) 539 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 540 } 541 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 542 #endif 543 544 int 545 soc_decode_win(void) 546 { 547 uint32_t dev, rev; 548 int mask, err; 549 550 mask = 0; 551 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 552 553 if (mask != 0) 554 pm_disable_device(mask); 555 556 /* Retrieve data about physical addresses from device tree. */ 557 if ((err = win_cpu_from_dt()) != 0) 558 return (err); 559 560 /* Retrieve our ID: some windows facilities vary between SoC models */ 561 soc_id(&dev, &rev); 562 563 #ifdef SOC_MV_ARMADAXP 564 if ((err = decode_win_sdram_fixup()) != 0) 565 return(err); 566 #endif 567 568 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 569 !decode_win_eth_valid() || !decode_win_idma_valid() || 570 !decode_win_pcie_valid() || !decode_win_sata_valid() || 571 !decode_win_xor_valid() || !decode_win_usb3_valid()) 572 return (EINVAL); 573 574 decode_win_cpu_setup(); 575 if (MV_DUMP_WIN) 576 soc_dump_decode_win(); 577 578 eth_port = 0; 579 usb_port = 0; 580 if ((err = fdt_win_setup()) != 0) 581 return (err); 582 583 return (0); 584 } 585 586 /************************************************************************** 587 * Decode windows registers accessors 588 **************************************************************************/ 589 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 590 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 591 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 592 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 593 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 594 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 595 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 596 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 597 598 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 599 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 600 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 601 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 602 603 #ifdef SOC_MV_ARMADA38X 604 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 605 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 606 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 607 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 608 #endif 609 610 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 611 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 612 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 613 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 614 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 615 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 616 617 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 618 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 619 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 620 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 621 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 622 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 623 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 624 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 625 626 WIN_REG_BASE_RD(win_eth, bare, 0x290) 627 WIN_REG_BASE_RD(win_eth, epap, 0x294) 628 WIN_REG_BASE_WR(win_eth, bare, 0x290) 629 WIN_REG_BASE_WR(win_eth, epap, 0x294) 630 631 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 632 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 633 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 634 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 635 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 636 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 637 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 638 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 639 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 640 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 641 642 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 643 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 644 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 645 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 646 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 647 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 648 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 649 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 650 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 651 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 652 653 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 654 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 655 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 656 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 657 #if defined(SOC_MV_ARMADA38X) 658 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 659 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 660 #endif 661 662 #ifndef SOC_MV_DOVE 663 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 664 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 665 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 666 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 667 #else 668 /* 669 * On 88F6781 (Dove) SoC DDR Controller is accessed through 670 * single MBUS <-> AXI bridge. In this case we provide emulated 671 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 672 * with common decoding windows setup code. 673 */ 674 675 static inline uint32_t ddr_br_read(int i) 676 { 677 uint32_t mmap; 678 679 /* Read Memory Address Map Register for CS i */ 680 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 681 682 /* Return CS i base address */ 683 return (mmap & 0xFF000000); 684 } 685 686 static inline uint32_t ddr_sz_read(int i) 687 { 688 uint32_t mmap, size; 689 690 /* Read Memory Address Map Register for CS i */ 691 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 692 693 /* Extract size of CS space in 64kB units */ 694 size = (1 << ((mmap >> 16) & 0x0F)); 695 696 /* Return CS size and enable/disable status */ 697 return (((size - 1) << 16) | (mmap & 0x01)); 698 } 699 #endif 700 701 /************************************************************************** 702 * Decode windows helper routines 703 **************************************************************************/ 704 void 705 soc_dump_decode_win(void) 706 { 707 uint32_t dev, rev; 708 int i; 709 710 soc_id(&dev, &rev); 711 712 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 713 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 714 win_cpu_cr_read(i), 715 win_cpu_br_read(i)); 716 717 if (win_cpu_can_remap(i)) 718 printf(", rl 0x%08x, rh 0x%08x", 719 win_cpu_remap_l_read(i), 720 win_cpu_remap_h_read(i)); 721 722 printf("\n"); 723 } 724 printf("Internal regs base: 0x%08x\n", 725 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 726 727 for (i = 0; i < MV_WIN_DDR_MAX; i++) 728 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 729 ddr_br_read(i), ddr_sz_read(i)); 730 } 731 732 /************************************************************************** 733 * CPU windows routines 734 **************************************************************************/ 735 int 736 win_cpu_can_remap(int i) 737 { 738 uint32_t dev, rev; 739 740 soc_id(&dev, &rev); 741 742 /* Depending on the SoC certain windows have remap capability */ 743 if ((dev == MV_DEV_88F5182 && i < 2) || 744 (dev == MV_DEV_88F5281 && i < 4) || 745 (dev == MV_DEV_88F6281 && i < 4) || 746 (dev == MV_DEV_88F6282 && i < 4) || 747 (dev == MV_DEV_88F6828 && i < 20) || 748 (dev == MV_DEV_88F6820 && i < 20) || 749 (dev == MV_DEV_88F6810 && i < 20) || 750 (dev == MV_DEV_88RC8180 && i < 2) || 751 (dev == MV_DEV_88F6781 && i < 4) || 752 (dev == MV_DEV_MV78100_Z0 && i < 8) || 753 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 754 return (1); 755 756 return (0); 757 } 758 759 /* XXX This should check for overlapping remap fields too.. */ 760 int 761 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 762 { 763 const struct decode_win *tab; 764 int i; 765 766 tab = wintab; 767 768 for (i = 0; i < win_no; i++, tab++) { 769 if (i == win) 770 /* Skip self */ 771 continue; 772 773 if ((tab->base + tab->size - 1) < (wintab + win)->base) 774 continue; 775 776 else if (((wintab + win)->base + (wintab + win)->size - 1) < 777 tab->base) 778 continue; 779 else 780 return (i); 781 } 782 783 return (-1); 784 } 785 786 static int 787 decode_win_cpu_valid(void) 788 { 789 int i, j, rv; 790 uint32_t b, e, s; 791 792 if (cpu_wins_no > MV_WIN_CPU_MAX) { 793 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 794 return (0); 795 } 796 797 rv = 1; 798 for (i = 0; i < cpu_wins_no; i++) { 799 800 if (cpu_wins[i].target == 0) { 801 printf("CPU window#%d: DDR target window is not " 802 "supposed to be reprogrammed!\n", i); 803 rv = 0; 804 } 805 806 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 807 printf("CPU window#%d: not capable of remapping, but " 808 "val 0x%08x defined\n", i, cpu_wins[i].remap); 809 rv = 0; 810 } 811 812 s = cpu_wins[i].size; 813 b = cpu_wins[i].base; 814 e = b + s - 1; 815 if (s > (0xFFFFFFFF - b + 1)) { 816 /* 817 * XXX this boundary check should account for 64bit 818 * and remapping.. 819 */ 820 printf("CPU window#%d: no space for size 0x%08x at " 821 "0x%08x\n", i, s, b); 822 rv = 0; 823 continue; 824 } 825 826 if (b != rounddown2(b, s)) { 827 printf("CPU window#%d: address 0x%08x is not aligned " 828 "to 0x%08x\n", i, b, s); 829 rv = 0; 830 continue; 831 } 832 833 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 834 if (j >= 0) { 835 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 836 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 837 cpu_wins[j].base, 838 cpu_wins[j].base + cpu_wins[j].size - 1); 839 rv = 0; 840 } 841 } 842 843 return (rv); 844 } 845 846 int 847 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 848 vm_paddr_t remap) 849 { 850 uint32_t br, cr; 851 int win, i; 852 853 if (remap == ~0) { 854 win = MV_WIN_CPU_MAX - 1; 855 i = -1; 856 } else { 857 win = 0; 858 i = 1; 859 } 860 861 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 862 cr = win_cpu_cr_read(win); 863 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 864 break; 865 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 866 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 867 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 868 (target << MV_WIN_CPU_TARGET_SHIFT))) 869 break; 870 win += i; 871 } 872 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 873 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 874 return (-1); 875 876 br = base & 0xffff0000; 877 win_cpu_br_write(win, br); 878 879 if (win_cpu_can_remap(win)) { 880 if (remap != ~0) { 881 win_cpu_remap_l_write(win, remap & 0xffff0000); 882 win_cpu_remap_h_write(win, 0); 883 } else { 884 /* 885 * Remap function is not used for a given window 886 * (capable of remapping) - set remap field with the 887 * same value as base. 888 */ 889 win_cpu_remap_l_write(win, base & 0xffff0000); 890 win_cpu_remap_h_write(win, 0); 891 } 892 } 893 894 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 895 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 896 win_cpu_cr_write(win, cr); 897 898 return (0); 899 } 900 901 static void 902 decode_win_cpu_setup(void) 903 { 904 int i; 905 906 /* Disable all CPU windows */ 907 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 908 win_cpu_cr_write(i, 0); 909 win_cpu_br_write(i, 0); 910 if (win_cpu_can_remap(i)) { 911 win_cpu_remap_l_write(i, 0); 912 win_cpu_remap_h_write(i, 0); 913 } 914 } 915 916 for (i = 0; i < cpu_wins_no; i++) 917 if (cpu_wins[i].target > 0) 918 decode_win_cpu_set(cpu_wins[i].target, 919 cpu_wins[i].attr, cpu_wins[i].base, 920 cpu_wins[i].size, cpu_wins[i].remap); 921 922 } 923 924 #ifdef SOC_MV_ARMADAXP 925 static int 926 decode_win_sdram_fixup(void) 927 { 928 struct mem_region mr[FDT_MEM_REGIONS]; 929 uint8_t window_valid[MV_WIN_DDR_MAX]; 930 int mr_cnt, err, i, j; 931 uint32_t valid_win_num = 0; 932 933 /* Grab physical memory regions information from device tree. */ 934 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 935 if (err != 0) 936 return (err); 937 938 for (i = 0; i < MV_WIN_DDR_MAX; i++) 939 window_valid[i] = 0; 940 941 /* Try to match entries from device tree with settings from u-boot */ 942 for (i = 0; i < mr_cnt; i++) { 943 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 944 if (ddr_is_active(j) && 945 (ddr_base(j) == mr[i].mr_start) && 946 (ddr_size(j) == mr[i].mr_size)) { 947 window_valid[j] = 1; 948 valid_win_num++; 949 } 950 } 951 } 952 953 if (mr_cnt != valid_win_num) 954 return (EINVAL); 955 956 /* Destroy windows without corresponding device tree entry */ 957 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 958 if (ddr_is_active(j) && (window_valid[j] != 1)) { 959 printf("Disabling SDRAM decoding window: %d\n", j); 960 ddr_disable(j); 961 } 962 } 963 964 return (0); 965 } 966 #endif 967 /* 968 * Check if we're able to cover all active DDR banks. 969 */ 970 static int 971 decode_win_can_cover_ddr(int max) 972 { 973 int i, c; 974 975 c = 0; 976 for (i = 0; i < MV_WIN_DDR_MAX; i++) 977 if (ddr_is_active(i)) 978 c++; 979 980 if (c > max) { 981 printf("Unable to cover all active DDR banks: " 982 "%d, available windows: %d\n", c, max); 983 return (0); 984 } 985 986 return (1); 987 } 988 989 /************************************************************************** 990 * DDR windows routines 991 **************************************************************************/ 992 int 993 ddr_is_active(int i) 994 { 995 996 if (ddr_sz_read(i) & 0x1) 997 return (1); 998 999 return (0); 1000 } 1001 1002 void 1003 ddr_disable(int i) 1004 { 1005 1006 ddr_sz_write(i, 0); 1007 ddr_br_write(i, 0); 1008 } 1009 1010 uint32_t 1011 ddr_base(int i) 1012 { 1013 1014 return (ddr_br_read(i) & 0xff000000); 1015 } 1016 1017 uint32_t 1018 ddr_size(int i) 1019 { 1020 1021 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1022 } 1023 1024 uint32_t 1025 ddr_attr(int i) 1026 { 1027 uint32_t dev, rev; 1028 1029 soc_id(&dev, &rev); 1030 if (dev == MV_DEV_88RC8180) 1031 return ((ddr_sz_read(i) & 0xf0) >> 4); 1032 if (dev == MV_DEV_88F6781) 1033 return (0); 1034 1035 return (i == 0 ? 0xe : 1036 (i == 1 ? 0xd : 1037 (i == 2 ? 0xb : 1038 (i == 3 ? 0x7 : 0xff)))); 1039 } 1040 1041 uint32_t 1042 ddr_target(int i) 1043 { 1044 uint32_t dev, rev; 1045 1046 soc_id(&dev, &rev); 1047 if (dev == MV_DEV_88RC8180) { 1048 i = (ddr_sz_read(i) & 0xf0) >> 4; 1049 return (i == 0xe ? 0xc : 1050 (i == 0xd ? 0xd : 1051 (i == 0xb ? 0xe : 1052 (i == 0x7 ? 0xf : 0xc)))); 1053 } 1054 1055 /* 1056 * On SOCs other than 88RC8180 Mbus unit ID for 1057 * DDR SDRAM controller is always 0x0. 1058 */ 1059 return (0); 1060 } 1061 1062 /************************************************************************** 1063 * USB windows routines 1064 **************************************************************************/ 1065 static int 1066 decode_win_usb_valid(void) 1067 { 1068 1069 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1070 } 1071 1072 static void 1073 decode_win_usb_dump(u_long base) 1074 { 1075 int i; 1076 1077 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1078 return; 1079 1080 for (i = 0; i < MV_WIN_USB_MAX; i++) 1081 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1082 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1083 } 1084 1085 /* 1086 * Set USB decode windows. 1087 */ 1088 static void 1089 decode_win_usb_setup(u_long base) 1090 { 1091 uint32_t br, cr; 1092 int i, j; 1093 1094 1095 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1096 return; 1097 1098 usb_port++; 1099 1100 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1101 win_usb_cr_write(base, i, 0); 1102 win_usb_br_write(base, i, 0); 1103 } 1104 1105 /* Only access to active DRAM banks is required */ 1106 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1107 if (ddr_is_active(i)) { 1108 br = ddr_base(i); 1109 /* 1110 * XXX for 6281 we should handle Mbus write 1111 * burst limit field in the ctrl reg 1112 */ 1113 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1114 (ddr_attr(i) << 8) | 1115 (ddr_target(i) << 4) | 1); 1116 1117 /* Set the first free USB window */ 1118 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1119 if (win_usb_cr_read(base, j) & 0x1) 1120 continue; 1121 1122 win_usb_br_write(base, j, br); 1123 win_usb_cr_write(base, j, cr); 1124 break; 1125 } 1126 } 1127 } 1128 } 1129 1130 /************************************************************************** 1131 * USB3 windows routines 1132 **************************************************************************/ 1133 #ifdef SOC_MV_ARMADA38X 1134 static int 1135 decode_win_usb3_valid(void) 1136 { 1137 1138 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1139 } 1140 1141 static void 1142 decode_win_usb3_dump(u_long base) 1143 { 1144 int i; 1145 1146 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1147 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1148 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1149 } 1150 1151 /* 1152 * Set USB3 decode windows 1153 */ 1154 static void 1155 decode_win_usb3_setup(u_long base) 1156 { 1157 uint32_t br, cr; 1158 int i, j; 1159 1160 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1161 win_usb3_cr_write(base, i, 0); 1162 win_usb3_br_write(base, i, 0); 1163 } 1164 1165 /* Only access to active DRAM banks is required */ 1166 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1167 if (ddr_is_active(i)) { 1168 br = ddr_base(i); 1169 cr = (((ddr_size(i) - 1) & 1170 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1171 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1172 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1173 IO_WIN_ENA_MASK); 1174 1175 /* Set the first free USB3.0 window */ 1176 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1177 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1178 continue; 1179 1180 win_usb3_br_write(base, j, br); 1181 win_usb3_cr_write(base, j, cr); 1182 break; 1183 } 1184 } 1185 } 1186 } 1187 #else 1188 /* 1189 * Provide dummy functions to satisfy the build 1190 * for SoCs not equipped with USB3 1191 */ 1192 static int 1193 decode_win_usb3_valid(void) 1194 { 1195 1196 return (1); 1197 } 1198 1199 static void 1200 decode_win_usb3_setup(u_long base) 1201 { 1202 } 1203 1204 static void 1205 decode_win_usb3_dump(u_long base) 1206 { 1207 } 1208 #endif 1209 /************************************************************************** 1210 * ETH windows routines 1211 **************************************************************************/ 1212 1213 static int 1214 win_eth_can_remap(int i) 1215 { 1216 1217 /* ETH encode windows 0-3 have remap capability */ 1218 if (i < 4) 1219 return (1); 1220 1221 return (0); 1222 } 1223 1224 static int 1225 eth_bare_read(uint32_t base, int i) 1226 { 1227 uint32_t v; 1228 1229 v = win_eth_bare_read(base); 1230 v &= (1 << i); 1231 1232 return (v >> i); 1233 } 1234 1235 static void 1236 eth_bare_write(uint32_t base, int i, int val) 1237 { 1238 uint32_t v; 1239 1240 v = win_eth_bare_read(base); 1241 v &= ~(1 << i); 1242 v |= (val << i); 1243 win_eth_bare_write(base, v); 1244 } 1245 1246 static void 1247 eth_epap_write(uint32_t base, int i, int val) 1248 { 1249 uint32_t v; 1250 1251 v = win_eth_epap_read(base); 1252 v &= ~(0x3 << (i * 2)); 1253 v |= (val << (i * 2)); 1254 win_eth_epap_write(base, v); 1255 } 1256 1257 static void 1258 decode_win_eth_dump(u_long base) 1259 { 1260 int i; 1261 1262 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1263 return; 1264 1265 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1266 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1267 win_eth_br_read(base, i), 1268 win_eth_sz_read(base, i)); 1269 1270 if (win_eth_can_remap(i)) 1271 printf(", ha 0x%08x", 1272 win_eth_har_read(base, i)); 1273 1274 printf("\n"); 1275 } 1276 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1277 win_eth_bare_read(base), 1278 win_eth_epap_read(base)); 1279 } 1280 1281 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1282 1283 static void 1284 decode_win_eth_setup(u_long base) 1285 { 1286 uint32_t br, sz; 1287 int i, j; 1288 1289 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1290 return; 1291 1292 eth_port++; 1293 1294 /* Disable, clear and revoke protection for all ETH windows */ 1295 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1296 1297 eth_bare_write(base, i, 1); 1298 eth_epap_write(base, i, 0); 1299 win_eth_br_write(base, i, 0); 1300 win_eth_sz_write(base, i, 0); 1301 if (win_eth_can_remap(i)) 1302 win_eth_har_write(base, i, 0); 1303 } 1304 1305 /* Only access to active DRAM banks is required */ 1306 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1307 if (ddr_is_active(i)) { 1308 1309 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1310 sz = ((ddr_size(i) - 1) & 0xffff0000); 1311 1312 /* Set the first free ETH window */ 1313 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1314 if (eth_bare_read(base, j) == 0) 1315 continue; 1316 1317 win_eth_br_write(base, j, br); 1318 win_eth_sz_write(base, j, sz); 1319 1320 /* XXX remapping ETH windows not supported */ 1321 1322 /* Set protection RW */ 1323 eth_epap_write(base, j, 0x3); 1324 1325 /* Enable window */ 1326 eth_bare_write(base, j, 0); 1327 break; 1328 } 1329 } 1330 } 1331 1332 static int 1333 decode_win_eth_valid(void) 1334 { 1335 1336 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1337 } 1338 1339 /************************************************************************** 1340 * PCIE windows routines 1341 **************************************************************************/ 1342 1343 void 1344 decode_win_pcie_setup(u_long base) 1345 { 1346 uint32_t size = 0, ddrbase = ~0; 1347 uint32_t cr, br; 1348 int i, j; 1349 1350 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1351 pcie_bar_br_write(base, i, 1352 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1353 if (i < 3) 1354 pcie_bar_brh_write(base, i, 0); 1355 if (i > 0) 1356 pcie_bar_cr_write(base, i, 0); 1357 } 1358 1359 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1360 win_pcie_cr_write(base, i, 0); 1361 win_pcie_br_write(base, i, 0); 1362 win_pcie_remap_write(base, i, 0); 1363 } 1364 1365 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1366 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1367 & MV_PCIE_ROOT_CMPLX) == 0) { 1368 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1369 return; 1370 } 1371 1372 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1373 if (ddr_is_active(i)) { 1374 /* Map DDR to BAR 1 */ 1375 cr = (ddr_size(i) - 1) & 0xffff0000; 1376 size += ddr_size(i) & 0xffff0000; 1377 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1378 br = ddr_base(i); 1379 if (br < ddrbase) 1380 ddrbase = br; 1381 1382 /* Use the first available PCIE window */ 1383 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1384 if (win_pcie_cr_read(base, j) != 0) 1385 continue; 1386 1387 win_pcie_br_write(base, j, br); 1388 win_pcie_cr_write(base, j, cr); 1389 break; 1390 } 1391 } 1392 } 1393 1394 /* 1395 * Upper 16 bits in BAR register is interpreted as BAR size 1396 * (in 64 kB units) plus 64kB, so subtract 0x10000 1397 * form value passed to register to get correct value. 1398 */ 1399 size -= 0x10000; 1400 pcie_bar_cr_write(base, 1, size | 1); 1401 pcie_bar_br_write(base, 1, ddrbase | 1402 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1403 pcie_bar_br_write(base, 0, fdt_immr_pa | 1404 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1405 } 1406 1407 static int 1408 decode_win_pcie_valid(void) 1409 { 1410 1411 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1412 } 1413 1414 /************************************************************************** 1415 * IDMA windows routines 1416 **************************************************************************/ 1417 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1418 static int 1419 idma_bare_read(u_long base, int i) 1420 { 1421 uint32_t v; 1422 1423 v = win_idma_bare_read(base); 1424 v &= (1 << i); 1425 1426 return (v >> i); 1427 } 1428 1429 static void 1430 idma_bare_write(u_long base, int i, int val) 1431 { 1432 uint32_t v; 1433 1434 v = win_idma_bare_read(base); 1435 v &= ~(1 << i); 1436 v |= (val << i); 1437 win_idma_bare_write(base, v); 1438 } 1439 1440 /* 1441 * Sets channel protection 'val' for window 'w' on channel 'c' 1442 */ 1443 static void 1444 idma_cap_write(u_long base, int c, int w, int val) 1445 { 1446 uint32_t v; 1447 1448 v = win_idma_cap_read(base, c); 1449 v &= ~(0x3 << (w * 2)); 1450 v |= (val << (w * 2)); 1451 win_idma_cap_write(base, c, v); 1452 } 1453 1454 /* 1455 * Set protection 'val' on all channels for window 'w' 1456 */ 1457 static void 1458 idma_set_prot(u_long base, int w, int val) 1459 { 1460 int c; 1461 1462 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1463 idma_cap_write(base, c, w, val); 1464 } 1465 1466 static int 1467 win_idma_can_remap(int i) 1468 { 1469 1470 /* IDMA decode windows 0-3 have remap capability */ 1471 if (i < 4) 1472 return (1); 1473 1474 return (0); 1475 } 1476 1477 void 1478 decode_win_idma_setup(u_long base) 1479 { 1480 uint32_t br, sz; 1481 int i, j; 1482 1483 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1484 return; 1485 /* 1486 * Disable and clear all IDMA windows, revoke protection for all channels 1487 */ 1488 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1489 1490 idma_bare_write(base, i, 1); 1491 win_idma_br_write(base, i, 0); 1492 win_idma_sz_write(base, i, 0); 1493 if (win_idma_can_remap(i) == 1) 1494 win_idma_har_write(base, i, 0); 1495 } 1496 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1497 win_idma_cap_write(base, i, 0); 1498 1499 /* 1500 * Set up access to all active DRAM banks 1501 */ 1502 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1503 if (ddr_is_active(i)) { 1504 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1505 sz = ((ddr_size(i) - 1) & 0xffff0000); 1506 1507 /* Place DDR entries in non-remapped windows */ 1508 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1509 if (win_idma_can_remap(j) != 1 && 1510 idma_bare_read(base, j) == 1) { 1511 1512 /* Configure window */ 1513 win_idma_br_write(base, j, br); 1514 win_idma_sz_write(base, j, sz); 1515 1516 /* Set protection RW on all channels */ 1517 idma_set_prot(base, j, 0x3); 1518 1519 /* Enable window */ 1520 idma_bare_write(base, j, 0); 1521 break; 1522 } 1523 } 1524 1525 /* 1526 * Remaining targets -- from statically defined table 1527 */ 1528 for (i = 0; i < idma_wins_no; i++) 1529 if (idma_wins[i].target > 0) { 1530 br = (idma_wins[i].base & 0xffff0000) | 1531 (idma_wins[i].attr << 8) | idma_wins[i].target; 1532 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1533 1534 /* Set the first free IDMA window */ 1535 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1536 if (idma_bare_read(base, j) == 0) 1537 continue; 1538 1539 /* Configure window */ 1540 win_idma_br_write(base, j, br); 1541 win_idma_sz_write(base, j, sz); 1542 if (win_idma_can_remap(j) && 1543 idma_wins[j].remap >= 0) 1544 win_idma_har_write(base, j, 1545 idma_wins[j].remap); 1546 1547 /* Set protection RW on all channels */ 1548 idma_set_prot(base, j, 0x3); 1549 1550 /* Enable window */ 1551 idma_bare_write(base, j, 0); 1552 break; 1553 } 1554 } 1555 } 1556 1557 int 1558 decode_win_idma_valid(void) 1559 { 1560 const struct decode_win *wintab; 1561 int c, i, j, rv; 1562 uint32_t b, e, s; 1563 1564 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1565 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1566 return (0); 1567 } 1568 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1569 if (ddr_is_active(i)) 1570 c++; 1571 1572 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1573 printf("IDMA windows: too many entries: %d, available: %d\n", 1574 idma_wins_no, MV_WIN_IDMA_MAX - c); 1575 return (0); 1576 } 1577 1578 wintab = idma_wins; 1579 rv = 1; 1580 for (i = 0; i < idma_wins_no; i++, wintab++) { 1581 1582 if (wintab->target == 0) { 1583 printf("IDMA window#%d: DDR target window is not " 1584 "supposed to be reprogrammed!\n", i); 1585 rv = 0; 1586 } 1587 1588 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1589 printf("IDMA window#%d: not capable of remapping, but " 1590 "val 0x%08x defined\n", i, wintab->remap); 1591 rv = 0; 1592 } 1593 1594 s = wintab->size; 1595 b = wintab->base; 1596 e = b + s - 1; 1597 if (s > (0xFFFFFFFF - b + 1)) { 1598 /* XXX this boundary check should account for 64bit and 1599 * remapping.. */ 1600 printf("IDMA window#%d: no space for size 0x%08x at " 1601 "0x%08x\n", i, s, b); 1602 rv = 0; 1603 continue; 1604 } 1605 1606 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1607 if (j >= 0) { 1608 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1609 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1610 idma_wins[j].base, 1611 idma_wins[j].base + idma_wins[j].size - 1); 1612 rv = 0; 1613 } 1614 } 1615 1616 return (rv); 1617 } 1618 1619 void 1620 decode_win_idma_dump(u_long base) 1621 { 1622 int i; 1623 1624 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1625 return; 1626 1627 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1628 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1629 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1630 1631 if (win_idma_can_remap(i)) 1632 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1633 1634 printf("\n"); 1635 } 1636 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1637 printf("IDMA channel#%d: ap 0x%08x\n", i, 1638 win_idma_cap_read(base, i)); 1639 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1640 } 1641 #else 1642 1643 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1644 int 1645 decode_win_idma_valid(void) 1646 { 1647 1648 return (1); 1649 } 1650 1651 void 1652 decode_win_idma_setup(u_long base) 1653 { 1654 } 1655 1656 void 1657 decode_win_idma_dump(u_long base) 1658 { 1659 } 1660 #endif 1661 1662 /************************************************************************** 1663 * XOR windows routines 1664 **************************************************************************/ 1665 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1666 static int 1667 xor_ctrl_read(u_long base, int i, int c, int e) 1668 { 1669 uint32_t v; 1670 v = win_xor_ctrl_read(base, c, e); 1671 v &= (1 << i); 1672 1673 return (v >> i); 1674 } 1675 1676 static void 1677 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1678 { 1679 uint32_t v; 1680 1681 v = win_xor_ctrl_read(base, c, e); 1682 v &= ~(1 << i); 1683 v |= (val << i); 1684 win_xor_ctrl_write(base, c, e, v); 1685 } 1686 1687 /* 1688 * Set channel protection 'val' for window 'w' on channel 'c' 1689 */ 1690 static void 1691 xor_chan_write(u_long base, int c, int e, int w, int val) 1692 { 1693 uint32_t v; 1694 1695 v = win_xor_ctrl_read(base, c, e); 1696 v &= ~(0x3 << (w * 2 + 16)); 1697 v |= (val << (w * 2 + 16)); 1698 win_xor_ctrl_write(base, c, e, v); 1699 } 1700 1701 /* 1702 * Set protection 'val' on all channels for window 'w' on engine 'e' 1703 */ 1704 static void 1705 xor_set_prot(u_long base, int w, int e, int val) 1706 { 1707 int c; 1708 1709 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1710 xor_chan_write(base, c, e, w, val); 1711 } 1712 1713 static int 1714 win_xor_can_remap(int i) 1715 { 1716 1717 /* XOR decode windows 0-3 have remap capability */ 1718 if (i < 4) 1719 return (1); 1720 1721 return (0); 1722 } 1723 1724 static int 1725 xor_max_eng(void) 1726 { 1727 uint32_t dev, rev; 1728 1729 soc_id(&dev, &rev); 1730 switch (dev) { 1731 case MV_DEV_88F6281: 1732 case MV_DEV_88F6282: 1733 case MV_DEV_MV78130: 1734 case MV_DEV_MV78160: 1735 case MV_DEV_MV78230: 1736 case MV_DEV_MV78260: 1737 case MV_DEV_MV78460: 1738 return (2); 1739 case MV_DEV_MV78100: 1740 case MV_DEV_MV78100_Z0: 1741 return (1); 1742 default: 1743 return (0); 1744 } 1745 } 1746 1747 static void 1748 xor_active_dram(u_long base, int c, int e, int *window) 1749 { 1750 uint32_t br, sz; 1751 int i, m, w; 1752 1753 /* 1754 * Set up access to all active DRAM banks 1755 */ 1756 m = xor_max_eng(); 1757 for (i = 0; i < m; i++) 1758 if (ddr_is_active(i)) { 1759 br = ddr_base(i) | (ddr_attr(i) << 8) | 1760 ddr_target(i); 1761 sz = ((ddr_size(i) - 1) & 0xffff0000); 1762 1763 /* Place DDR entries in non-remapped windows */ 1764 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1765 if (win_xor_can_remap(w) != 1 && 1766 (xor_ctrl_read(base, w, c, e) == 0) && 1767 w > *window) { 1768 /* Configure window */ 1769 win_xor_br_write(base, w, e, br); 1770 win_xor_sz_write(base, w, e, sz); 1771 1772 /* Set protection RW on all channels */ 1773 xor_set_prot(base, w, e, 0x3); 1774 1775 /* Enable window */ 1776 xor_ctrl_write(base, w, c, e, 1); 1777 (*window)++; 1778 break; 1779 } 1780 } 1781 } 1782 1783 void 1784 decode_win_xor_setup(u_long base) 1785 { 1786 uint32_t br, sz; 1787 int i, j, z, e = 1, m, window; 1788 1789 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1790 return; 1791 1792 /* 1793 * Disable and clear all XOR windows, revoke protection for all 1794 * channels 1795 */ 1796 m = xor_max_eng(); 1797 for (j = 0; j < m; j++, e--) { 1798 1799 /* Number of non-remaped windows */ 1800 window = MV_XOR_NON_REMAP - 1; 1801 1802 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1803 win_xor_br_write(base, i, e, 0); 1804 win_xor_sz_write(base, i, e, 0); 1805 } 1806 1807 if (win_xor_can_remap(i) == 1) 1808 win_xor_har_write(base, i, e, 0); 1809 1810 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1811 win_xor_ctrl_write(base, i, e, 0); 1812 xor_active_dram(base, i, e, &window); 1813 } 1814 1815 /* 1816 * Remaining targets -- from a statically defined table 1817 */ 1818 for (i = 0; i < xor_wins_no; i++) 1819 if (xor_wins[i].target > 0) { 1820 br = (xor_wins[i].base & 0xffff0000) | 1821 (xor_wins[i].attr << 8) | 1822 xor_wins[i].target; 1823 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1824 1825 /* Set the first free XOR window */ 1826 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1827 if (xor_ctrl_read(base, z, 0, e) && 1828 xor_ctrl_read(base, z, 1, e)) 1829 continue; 1830 1831 /* Configure window */ 1832 win_xor_br_write(base, z, e, br); 1833 win_xor_sz_write(base, z, e, sz); 1834 if (win_xor_can_remap(z) && 1835 xor_wins[z].remap >= 0) 1836 win_xor_har_write(base, z, e, 1837 xor_wins[z].remap); 1838 1839 /* Set protection RW on all channels */ 1840 xor_set_prot(base, z, e, 0x3); 1841 1842 /* Enable window */ 1843 xor_ctrl_write(base, z, 0, e, 1); 1844 xor_ctrl_write(base, z, 1, e, 1); 1845 break; 1846 } 1847 } 1848 } 1849 } 1850 1851 int 1852 decode_win_xor_valid(void) 1853 { 1854 const struct decode_win *wintab; 1855 int c, i, j, rv; 1856 uint32_t b, e, s; 1857 1858 if (xor_wins_no > MV_WIN_XOR_MAX) { 1859 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1860 return (0); 1861 } 1862 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1863 if (ddr_is_active(i)) 1864 c++; 1865 1866 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 1867 printf("XOR windows: too many entries: %d, available: %d\n", 1868 xor_wins_no, MV_WIN_IDMA_MAX - c); 1869 return (0); 1870 } 1871 1872 wintab = xor_wins; 1873 rv = 1; 1874 for (i = 0; i < xor_wins_no; i++, wintab++) { 1875 1876 if (wintab->target == 0) { 1877 printf("XOR window#%d: DDR target window is not " 1878 "supposed to be reprogrammed!\n", i); 1879 rv = 0; 1880 } 1881 1882 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1883 printf("XOR window#%d: not capable of remapping, but " 1884 "val 0x%08x defined\n", i, wintab->remap); 1885 rv = 0; 1886 } 1887 1888 s = wintab->size; 1889 b = wintab->base; 1890 e = b + s - 1; 1891 if (s > (0xFFFFFFFF - b + 1)) { 1892 /* 1893 * XXX this boundary check should account for 64bit 1894 * and remapping.. 1895 */ 1896 printf("XOR window#%d: no space for size 0x%08x at " 1897 "0x%08x\n", i, s, b); 1898 rv = 0; 1899 continue; 1900 } 1901 1902 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 1903 if (j >= 0) { 1904 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 1905 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1906 xor_wins[j].base, 1907 xor_wins[j].base + xor_wins[j].size - 1); 1908 rv = 0; 1909 } 1910 } 1911 1912 return (rv); 1913 } 1914 1915 void 1916 decode_win_xor_dump(u_long base) 1917 { 1918 int i, j; 1919 int e = 1; 1920 1921 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1922 return; 1923 1924 for (j = 0; j < xor_max_eng(); j++, e--) { 1925 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1926 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 1927 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 1928 1929 if (win_xor_can_remap(i)) 1930 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 1931 1932 printf("\n"); 1933 } 1934 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 1935 printf("XOR control#%d: 0x%08x\n", i, 1936 win_xor_ctrl_read(base, i, e)); 1937 } 1938 } 1939 1940 #else 1941 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 1942 static int 1943 decode_win_xor_valid(void) 1944 { 1945 1946 return (1); 1947 } 1948 1949 static void 1950 decode_win_xor_setup(u_long base) 1951 { 1952 } 1953 1954 static void 1955 decode_win_xor_dump(u_long base) 1956 { 1957 } 1958 #endif 1959 1960 /************************************************************************** 1961 * SATA windows routines 1962 **************************************************************************/ 1963 static void 1964 decode_win_sata_setup(u_long base) 1965 { 1966 uint32_t cr, br; 1967 int i, j; 1968 1969 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 1970 return; 1971 1972 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 1973 win_sata_cr_write(base, i, 0); 1974 win_sata_br_write(base, i, 0); 1975 } 1976 1977 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1978 if (ddr_is_active(i)) { 1979 cr = ((ddr_size(i) - 1) & 0xffff0000) | 1980 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1981 br = ddr_base(i); 1982 1983 /* Use the first available SATA window */ 1984 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 1985 if ((win_sata_cr_read(base, j) & 1) != 0) 1986 continue; 1987 1988 win_sata_br_write(base, j, br); 1989 win_sata_cr_write(base, j, cr); 1990 break; 1991 } 1992 } 1993 } 1994 1995 #ifdef SOC_MV_ARMADA38X 1996 /* 1997 * Configure AHCI decoding windows 1998 */ 1999 static void 2000 decode_win_ahci_setup(u_long base) 2001 { 2002 uint32_t br, cr, sz; 2003 int i, j; 2004 2005 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2006 win_sata_cr_write(base, i, 0); 2007 win_sata_br_write(base, i, 0); 2008 win_sata_sz_write(base, i, 0); 2009 } 2010 2011 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2012 if (ddr_is_active(i)) { 2013 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2014 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2015 IO_WIN_ENA_MASK; 2016 br = ddr_base(i); 2017 sz = (ddr_size(i) - 1) & 2018 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2019 2020 /* Use first available SATA window */ 2021 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2022 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2023 continue; 2024 2025 /* BASE is set to DRAM base (0x00000000) */ 2026 win_sata_br_write(base, j, br); 2027 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2028 win_sata_cr_write(base, j, cr); 2029 /* SIZE is set to 16MB - max value */ 2030 win_sata_sz_write(base, j, sz); 2031 break; 2032 } 2033 } 2034 } 2035 } 2036 2037 static void 2038 decode_win_ahci_dump(u_long base) 2039 { 2040 int i; 2041 2042 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2043 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2044 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2045 win_sata_sz_read(base,i)); 2046 } 2047 2048 #else 2049 /* 2050 * Provide dummy functions to satisfy the build 2051 * for SoC's not equipped with AHCI controller 2052 */ 2053 static void 2054 decode_win_ahci_setup(u_long base) 2055 { 2056 } 2057 2058 static void 2059 decode_win_ahci_dump(u_long base) 2060 { 2061 } 2062 #endif 2063 2064 static int 2065 decode_win_sata_valid(void) 2066 { 2067 uint32_t dev, rev; 2068 2069 soc_id(&dev, &rev); 2070 if (dev == MV_DEV_88F5281) 2071 return (1); 2072 2073 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2074 } 2075 2076 /************************************************************************** 2077 * FDT parsing routines. 2078 **************************************************************************/ 2079 2080 static int 2081 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2082 int *tuplesize) 2083 { 2084 phandle_t node; 2085 pcell_t addr_cells, par_addr_cells, size_cells; 2086 int len, tuple_size, tuples_count; 2087 2088 node = OF_finddevice(nodename); 2089 if (node == -1) 2090 return (EINVAL); 2091 2092 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2093 return (ENXIO); 2094 2095 par_addr_cells = fdt_parent_addr_cells(node); 2096 if (par_addr_cells > 2) 2097 return (ERANGE); 2098 2099 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2100 size_cells); 2101 2102 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2103 len = OF_getprop(node, "ranges", buf, size); 2104 2105 /* 2106 * XXX this does not handle the empty 'ranges;' case, which is 2107 * legitimate and should be allowed. 2108 */ 2109 tuples_count = len / tuple_size; 2110 if (tuples_count <= 0) 2111 return (ERANGE); 2112 2113 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2114 return (ERANGE); 2115 2116 *tuples = tuples_count; 2117 *tuplesize = tuple_size; 2118 return (0); 2119 } 2120 2121 static int 2122 win_cpu_from_dt(void) 2123 { 2124 pcell_t ranges[48]; 2125 phandle_t node; 2126 int i, entry_size, err, t, tuple_size, tuples; 2127 u_long sram_base, sram_size; 2128 2129 t = 0; 2130 /* Retrieve 'ranges' property of '/localbus' node. */ 2131 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2132 &tuples, &tuple_size)) == 0) { 2133 /* 2134 * Fill CPU decode windows table. 2135 */ 2136 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2137 2138 entry_size = tuple_size / sizeof(pcell_t); 2139 cpu_wins_no = tuples; 2140 2141 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2142 cpu_win_tbl[t].target = 1; 2143 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2144 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2145 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2146 cpu_win_tbl[t].remap = ~0; 2147 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2148 "size = 0x%0x remap = 0x%0x\n", 2149 cpu_win_tbl[t].target, 2150 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2151 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2152 } 2153 } 2154 2155 /* 2156 * Retrieve CESA SRAM data. 2157 */ 2158 if ((node = OF_finddevice("sram")) != -1) 2159 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2160 goto moveon; 2161 2162 if ((node = OF_finddevice("/")) == 0) 2163 return (ENXIO); 2164 2165 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2166 /* SRAM block is not always present. */ 2167 return (0); 2168 moveon: 2169 sram_base = sram_size = 0; 2170 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2171 return (EINVAL); 2172 2173 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2174 #ifdef SOC_MV_ARMADA38X 2175 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2176 #else 2177 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2178 #endif 2179 cpu_win_tbl[t].base = sram_base; 2180 cpu_win_tbl[t].size = sram_size; 2181 cpu_win_tbl[t].remap = ~0; 2182 cpu_wins_no++; 2183 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2184 2185 /* Check if there is a second CESA node */ 2186 while ((node = OF_peer(node)) != 0) { 2187 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2188 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2189 return (EINVAL); 2190 break; 2191 } 2192 } 2193 2194 if (node == 0) 2195 return (0); 2196 2197 t++; 2198 if (t >= nitems(cpu_win_tbl)) { 2199 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2200 return (ENOMEM); 2201 } 2202 2203 /* Configure window for CESA1 */ 2204 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2205 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2206 cpu_win_tbl[t].base = sram_base; 2207 cpu_win_tbl[t].size = sram_size; 2208 cpu_win_tbl[t].remap = ~0; 2209 cpu_wins_no++; 2210 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2211 2212 return (0); 2213 } 2214 2215 static int 2216 fdt_win_setup(void) 2217 { 2218 phandle_t node, child; 2219 struct soc_node_spec *soc_node; 2220 u_long size, base; 2221 int err, i; 2222 2223 node = OF_finddevice("/"); 2224 if (node == -1) 2225 panic("fdt_win_setup: no root node"); 2226 2227 /* 2228 * Traverse through all children of root and simple-bus nodes. 2229 * For each found device retrieve decode windows data (if applicable). 2230 */ 2231 child = OF_child(node); 2232 while (child != 0) { 2233 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2234 2235 soc_node = &soc_nodes[i]; 2236 2237 /* Setup only for enabled devices */ 2238 if (ofw_bus_node_status_okay(child) == 0) 2239 continue; 2240 2241 if (!ofw_bus_node_is_compatible(child,soc_node->compat)) 2242 continue; 2243 2244 err = fdt_regsize(child, &base, &size); 2245 if (err != 0) 2246 return (err); 2247 2248 base = (base & 0x000fffff) | fdt_immr_va; 2249 if (soc_node->decode_handler != NULL) 2250 soc_node->decode_handler(base); 2251 else 2252 return (ENXIO); 2253 2254 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2255 soc_node->dump_handler(base); 2256 } 2257 2258 /* 2259 * Once done with root-level children let's move down to 2260 * simple-bus and its children. 2261 */ 2262 child = OF_peer(child); 2263 if ((child == 0) && (node == OF_finddevice("/"))) { 2264 node = fdt_find_compatible(node, "simple-bus", 0); 2265 if (node == 0) 2266 return (ENXIO); 2267 child = OF_child(node); 2268 } 2269 /* 2270 * Next, move one more level down to internal-regs node (if 2271 * it is present) and its children. This node also have 2272 * "simple-bus" compatible. 2273 */ 2274 if ((child == 0) && (node == OF_finddevice("simple-bus"))) { 2275 node = fdt_find_compatible(node, "simple-bus", 0); 2276 if (node == 0) 2277 return (0); 2278 child = OF_child(node); 2279 } 2280 } 2281 2282 return (0); 2283 } 2284 2285 static void 2286 fdt_fixup_busfreq(phandle_t root) 2287 { 2288 phandle_t sb; 2289 pcell_t freq; 2290 2291 freq = cpu_to_fdt32(get_tclk()); 2292 2293 /* 2294 * Fix bus speed in cpu node 2295 */ 2296 if ((sb = OF_finddevice("cpu")) != 0) 2297 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2298 OF_setprop(sb, "bus-frequency", (void *)&freq, 2299 sizeof(freq)); 2300 2301 /* 2302 * This fixup sets the simple-bus bus-frequency property. 2303 */ 2304 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2305 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2306 } 2307 2308 static void 2309 fdt_fixup_ranges(phandle_t root) 2310 { 2311 phandle_t node; 2312 pcell_t par_addr_cells, addr_cells, size_cells; 2313 pcell_t ranges[3], reg[2], *rangesptr; 2314 int len, tuple_size, tuples_count; 2315 uint32_t base; 2316 2317 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2318 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2319 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2320 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2321 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2322 addr_cells + size_cells); 2323 len = OF_getprop(node, "ranges", ranges, 2324 sizeof(ranges)); 2325 tuples_count = len / tuple_size; 2326 /* Unexpected settings are not supported */ 2327 if (tuples_count != 1) 2328 goto fixup_failed; 2329 2330 rangesptr = &ranges[0]; 2331 rangesptr += par_addr_cells; 2332 base = fdt_data_get((void *)rangesptr, addr_cells); 2333 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2334 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2335 sizeof(ranges)) < 0) 2336 goto fixup_failed; 2337 } 2338 } 2339 2340 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2341 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2342 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2343 &size_cells) == 0) { 2344 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2345 size_cells); 2346 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2347 tuples_count = len / tuple_size; 2348 /* Unexpected settings are not supported */ 2349 if (tuples_count != 1) 2350 goto fixup_failed; 2351 2352 base = fdt_data_get((void *)®[0], par_addr_cells); 2353 base &= ~0xFF000000; 2354 base |= fdt_immr_pa; 2355 reg[0] = cpu_to_fdt32(base); 2356 if (OF_setprop(node, "reg", (void *)®[0], 2357 sizeof(reg)) < 0) 2358 goto fixup_failed; 2359 } 2360 } 2361 /* Fix-up succeeded. May return and continue */ 2362 return; 2363 2364 fixup_failed: 2365 while (1) { 2366 /* 2367 * In case of any error while fixing ranges just hang. 2368 * 1. No message can be displayed yet since console 2369 * is not initialized. 2370 * 2. Going further will cause failure on bus_space_map() 2371 * relying on the wrong ranges or data abort when 2372 * accessing PCIe registers. 2373 */ 2374 } 2375 } 2376 2377 struct fdt_fixup_entry fdt_fixup_table[] = { 2378 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2379 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2380 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2381 { NULL, NULL } 2382 }; 2383 2384 #ifndef INTRNG 2385 static int 2386 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2387 int *pol) 2388 { 2389 2390 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2391 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2392 return (ENXIO); 2393 2394 *interrupt = fdt32_to_cpu(intr[0]); 2395 *trig = INTR_TRIGGER_CONFORM; 2396 *pol = INTR_POLARITY_CONFORM; 2397 2398 return (0); 2399 } 2400 2401 fdt_pic_decode_t fdt_pic_table[] = { 2402 #ifdef SOC_MV_ARMADA38X 2403 &gic_decode_fdt, 2404 #endif 2405 &fdt_pic_decode_ic, 2406 NULL 2407 }; 2408 #endif 2409 2410 uint64_t 2411 get_sar_value(void) 2412 { 2413 uint32_t sar_low, sar_high; 2414 2415 #if defined(SOC_MV_ARMADAXP) 2416 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2417 SAMPLE_AT_RESET_HI); 2418 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2419 SAMPLE_AT_RESET_LO); 2420 #elif defined(SOC_MV_ARMADA38X) 2421 sar_high = 0; 2422 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2423 SAMPLE_AT_RESET); 2424 #else 2425 /* 2426 * TODO: Add getting proper values for other SoC configurations 2427 */ 2428 sar_high = 0; 2429 sar_low = 0; 2430 #endif 2431 2432 return (((uint64_t)sar_high << 32) | sar_low); 2433 } 2434