1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cesa_valid(void); 80 static int decode_win_cpu_valid(void); 81 static int decode_win_usb_valid(void); 82 static int decode_win_usb3_valid(void); 83 static int decode_win_eth_valid(void); 84 static int decode_win_pcie_valid(void); 85 static int decode_win_sata_valid(void); 86 static int decode_win_sdhci_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 static void decode_win_cpu_setup(void); 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_cesa_setup(u_long); 96 static void decode_win_usb_setup(u_long); 97 static void decode_win_usb3_setup(u_long); 98 static void decode_win_eth_setup(u_long); 99 static void decode_win_neta_setup(u_long); 100 static void decode_win_sata_setup(u_long); 101 static void decode_win_ahci_setup(u_long); 102 static void decode_win_sdhci_setup(u_long); 103 104 static void decode_win_idma_setup(u_long); 105 static void decode_win_xor_setup(u_long); 106 107 static void decode_win_cesa_dump(u_long); 108 static void decode_win_usb_dump(u_long); 109 static void decode_win_usb3_dump(u_long); 110 static void decode_win_eth_dump(u_long base); 111 static void decode_win_neta_dump(u_long base); 112 static void decode_win_idma_dump(u_long base); 113 static void decode_win_xor_dump(u_long base); 114 static void decode_win_ahci_dump(u_long base); 115 static void decode_win_sdhci_dump(u_long); 116 static void decode_win_pcie_dump(u_long); 117 118 static int fdt_get_ranges(const char *, void *, int, int *, int *); 119 #ifdef SOC_MV_ARMADA38X 120 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 121 int *trig, int *pol); 122 #endif 123 124 static int win_cpu_from_dt(void); 125 static int fdt_win_setup(void); 126 127 static uint32_t dev_mask = 0; 128 static int cpu_wins_no = 0; 129 static int eth_port = 0; 130 static int usb_port = 0; 131 132 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 133 134 const struct decode_win *cpu_wins = cpu_win_tbl; 135 136 typedef void (*decode_win_setup_t)(u_long); 137 typedef void (*dump_win_t)(u_long); 138 139 /* 140 * The power status of device feature is only supported on 141 * Kirkwood and Discovery SoCs. 142 */ 143 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 144 #define SOC_MV_POWER_STAT_SUPPORTED 1 145 #else 146 #define SOC_MV_POWER_STAT_SUPPORTED 0 147 #endif 148 149 struct soc_node_spec { 150 const char *compat; 151 decode_win_setup_t decode_handler; 152 dump_win_t dump_handler; 153 }; 154 155 static struct soc_node_spec soc_nodes[] = { 156 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 157 { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump }, 158 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 159 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 160 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 161 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 162 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, 163 { "mrvl,sata", &decode_win_sata_setup, NULL }, 164 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 165 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 166 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, 167 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump }, 168 { NULL, NULL, NULL }, 169 }; 170 171 struct fdt_pm_mask_entry { 172 char *compat; 173 uint32_t mask; 174 }; 175 176 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 177 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 178 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 179 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 180 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 181 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 182 { "mrvl,xor", CPU_PM_CTRL_XOR }, 183 { "mrvl,sata", CPU_PM_CTRL_SATA }, 184 185 { NULL, 0 } 186 }; 187 188 static __inline int 189 pm_is_disabled(uint32_t mask) 190 { 191 #if SOC_MV_POWER_STAT_SUPPORTED 192 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 193 #else 194 return (0); 195 #endif 196 } 197 198 /* 199 * Disable device using power management register. 200 * 1 - Device Power On 201 * 0 - Device Power Off 202 * Mask can be set in loader. 203 * EXAMPLE: 204 * loader> set hw.pm-disable-mask=0x2 205 * 206 * Common mask: 207 * |-------------------------------| 208 * | Device | Kirkwood | Discovery | 209 * |-------------------------------| 210 * | USB0 | 0x00008 | 0x020000 | 211 * |-------------------------------| 212 * | USB1 | - | 0x040000 | 213 * |-------------------------------| 214 * | USB2 | - | 0x080000 | 215 * |-------------------------------| 216 * | GE0 | 0x00001 | 0x000002 | 217 * |-------------------------------| 218 * | GE1 | - | 0x000004 | 219 * |-------------------------------| 220 * | IDMA | - | 0x100000 | 221 * |-------------------------------| 222 * | XOR | 0x10000 | 0x200000 | 223 * |-------------------------------| 224 * | CESA | 0x20000 | 0x400000 | 225 * |-------------------------------| 226 * | SATA | 0x04000 | 0x004000 | 227 * --------------------------------| 228 * This feature can be used only on Kirkwood and Discovery 229 * machines. 230 */ 231 static __inline void 232 pm_disable_device(int mask) 233 { 234 #ifdef DIAGNOSTIC 235 uint32_t reg; 236 237 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 238 printf("Power Management Register: 0%x\n", reg); 239 240 reg &= ~mask; 241 soc_power_ctrl_set(reg); 242 printf("Device %x is disabled\n", mask); 243 244 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 245 printf("Power Management Register: 0%x\n", reg); 246 #endif 247 } 248 249 int 250 fdt_pm(phandle_t node) 251 { 252 uint32_t cpu_pm_ctrl; 253 int i, ena, compat; 254 255 ena = 1; 256 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 257 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 258 if (dev_mask & (1 << i)) 259 continue; 260 261 compat = ofw_bus_node_is_compatible(node, 262 fdt_pm_mask_table[i].compat); 263 #if defined(SOC_MV_KIRKWOOD) 264 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 265 dev_mask |= (1 << i); 266 ena = 0; 267 break; 268 } else if (compat) { 269 dev_mask |= (1 << i); 270 break; 271 } 272 #else 273 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 274 dev_mask |= (1 << i); 275 ena = 0; 276 break; 277 } else if (compat) { 278 dev_mask |= (1 << i); 279 break; 280 } 281 #endif 282 } 283 284 return (ena); 285 } 286 287 uint32_t 288 read_cpu_ctrl(uint32_t reg) 289 { 290 291 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 292 } 293 294 void 295 write_cpu_ctrl(uint32_t reg, uint32_t val) 296 { 297 298 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 299 } 300 301 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 302 uint32_t 303 read_cpu_mp_clocks(uint32_t reg) 304 { 305 306 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 307 } 308 309 void 310 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 311 { 312 313 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 314 } 315 316 uint32_t 317 read_cpu_misc(uint32_t reg) 318 { 319 320 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 321 } 322 323 void 324 write_cpu_misc(uint32_t reg, uint32_t val) 325 { 326 327 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 328 } 329 #endif 330 331 void 332 cpu_reset(void) 333 { 334 335 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 336 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 337 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 338 #else 339 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 340 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 341 #endif 342 while (1); 343 } 344 345 uint32_t 346 cpu_extra_feat(void) 347 { 348 uint32_t dev, rev; 349 uint32_t ef = 0; 350 351 soc_id(&dev, &rev); 352 353 switch (dev) { 354 case MV_DEV_88F6281: 355 case MV_DEV_88F6282: 356 case MV_DEV_88RC8180: 357 case MV_DEV_MV78100_Z0: 358 case MV_DEV_MV78100: 359 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 360 break; 361 case MV_DEV_88F5182: 362 case MV_DEV_88F5281: 363 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 364 break; 365 default: 366 if (bootverbose) 367 printf("This ARM Core does not support any extra features\n"); 368 } 369 370 return (ef); 371 } 372 373 /* 374 * Get the power status of device. This feature is only supported on 375 * Kirkwood and Discovery SoCs. 376 */ 377 uint32_t 378 soc_power_ctrl_get(uint32_t mask) 379 { 380 381 #if SOC_MV_POWER_STAT_SUPPORTED 382 if (mask != CPU_PM_CTRL_NONE) 383 mask &= read_cpu_ctrl(CPU_PM_CTRL); 384 385 return (mask); 386 #else 387 return (mask); 388 #endif 389 } 390 391 /* 392 * Set the power status of device. This feature is only supported on 393 * Kirkwood and Discovery SoCs. 394 */ 395 void 396 soc_power_ctrl_set(uint32_t mask) 397 { 398 399 #if !defined(SOC_MV_ORION) 400 if (mask != CPU_PM_CTRL_NONE) 401 write_cpu_ctrl(CPU_PM_CTRL, mask); 402 #endif 403 } 404 405 void 406 soc_id(uint32_t *dev, uint32_t *rev) 407 { 408 409 /* 410 * Notice: system identifiers are available in the registers range of 411 * PCIE controller, so using this function is only allowed (and 412 * possible) after the internal registers range has been mapped in via 413 * devmap_bootstrap(). 414 */ 415 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 416 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 417 } 418 419 static void 420 soc_identify(void) 421 { 422 uint32_t d, r, size, mode; 423 const char *dev; 424 const char *rev; 425 426 soc_id(&d, &r); 427 428 printf("SOC: "); 429 if (bootverbose) 430 printf("(0x%4x:0x%02x) ", d, r); 431 432 rev = ""; 433 switch (d) { 434 case MV_DEV_88F5181: 435 dev = "Marvell 88F5181"; 436 if (r == 3) 437 rev = "B1"; 438 break; 439 case MV_DEV_88F5182: 440 dev = "Marvell 88F5182"; 441 if (r == 2) 442 rev = "A2"; 443 break; 444 case MV_DEV_88F5281: 445 dev = "Marvell 88F5281"; 446 if (r == 4) 447 rev = "D0"; 448 else if (r == 5) 449 rev = "D1"; 450 else if (r == 6) 451 rev = "D2"; 452 break; 453 case MV_DEV_88F6281: 454 dev = "Marvell 88F6281"; 455 if (r == 0) 456 rev = "Z0"; 457 else if (r == 2) 458 rev = "A0"; 459 else if (r == 3) 460 rev = "A1"; 461 break; 462 case MV_DEV_88RC8180: 463 dev = "Marvell 88RC8180"; 464 break; 465 case MV_DEV_88RC9480: 466 dev = "Marvell 88RC9480"; 467 break; 468 case MV_DEV_88RC9580: 469 dev = "Marvell 88RC9580"; 470 break; 471 case MV_DEV_88F6781: 472 dev = "Marvell 88F6781"; 473 if (r == 2) 474 rev = "Y0"; 475 break; 476 case MV_DEV_88F6282: 477 dev = "Marvell 88F6282"; 478 if (r == 0) 479 rev = "A0"; 480 else if (r == 1) 481 rev = "A1"; 482 break; 483 case MV_DEV_88F6828: 484 dev = "Marvell 88F6828"; 485 break; 486 case MV_DEV_88F6820: 487 dev = "Marvell 88F6820"; 488 break; 489 case MV_DEV_88F6810: 490 dev = "Marvell 88F6810"; 491 break; 492 case MV_DEV_MV78100_Z0: 493 dev = "Marvell MV78100 Z0"; 494 break; 495 case MV_DEV_MV78100: 496 dev = "Marvell MV78100"; 497 break; 498 case MV_DEV_MV78160: 499 dev = "Marvell MV78160"; 500 break; 501 case MV_DEV_MV78260: 502 dev = "Marvell MV78260"; 503 break; 504 case MV_DEV_MV78460: 505 dev = "Marvell MV78460"; 506 break; 507 default: 508 dev = "UNKNOWN"; 509 break; 510 } 511 512 printf("%s", dev); 513 if (*rev != '\0') 514 printf(" rev %s", rev); 515 printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); 516 517 mode = read_cpu_ctrl(CPU_CONFIG); 518 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 519 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 520 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 521 522 switch (d) { 523 case MV_DEV_88F6281: 524 case MV_DEV_88F6282: 525 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 526 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 527 mode ? "write-through" : "write-back"); 528 break; 529 case MV_DEV_MV78100: 530 mode = read_cpu_ctrl(CPU_CONTROL); 531 size = mode & CPU_CONTROL_L2_SIZE; 532 mode = mode & CPU_CONTROL_L2_MODE; 533 printf(" %s set-associative %s unified L2 cache\n", 534 size ? "256KB 4-way" : "512KB 8-way", 535 mode ? "write-through" : "write-back"); 536 break; 537 default: 538 break; 539 } 540 } 541 542 static void 543 platform_identify(void *dummy) 544 { 545 546 soc_identify(); 547 548 /* 549 * XXX Board identification e.g. read out from FPGA or similar should 550 * go here 551 */ 552 } 553 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 554 NULL); 555 556 #ifdef KDB 557 static void 558 mv_enter_debugger(void *dummy) 559 { 560 561 if (boothowto & RB_KDB) 562 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 563 } 564 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 565 #endif 566 567 int 568 soc_decode_win(void) 569 { 570 uint32_t dev, rev; 571 int mask, err; 572 573 mask = 0; 574 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 575 576 if (mask != 0) 577 pm_disable_device(mask); 578 579 /* Retrieve data about physical addresses from device tree. */ 580 if ((err = win_cpu_from_dt()) != 0) 581 return (err); 582 583 /* Retrieve our ID: some windows facilities vary between SoC models */ 584 soc_id(&dev, &rev); 585 586 #ifdef SOC_MV_ARMADAXP 587 if ((err = decode_win_sdram_fixup()) != 0) 588 return(err); 589 #endif 590 591 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 592 !decode_win_eth_valid() || !decode_win_idma_valid() || 593 !decode_win_pcie_valid() || !decode_win_sata_valid() || 594 !decode_win_xor_valid() || !decode_win_usb3_valid() || 595 !decode_win_sdhci_valid() || !decode_win_cesa_valid()) 596 return (EINVAL); 597 598 decode_win_cpu_setup(); 599 if (MV_DUMP_WIN) 600 soc_dump_decode_win(); 601 602 eth_port = 0; 603 usb_port = 0; 604 if ((err = fdt_win_setup()) != 0) 605 return (err); 606 607 return (0); 608 } 609 610 /************************************************************************** 611 * Decode windows registers accessors 612 **************************************************************************/ 613 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 614 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 615 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 616 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 617 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 618 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 619 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 620 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 621 622 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 623 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 624 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 625 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 626 627 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 628 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 629 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 630 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 631 632 #ifdef SOC_MV_ARMADA38X 633 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 634 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 635 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 636 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 637 #endif 638 639 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 640 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 641 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 642 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 643 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 644 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 645 646 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 647 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 648 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 649 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 650 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 651 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 652 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 653 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 654 655 WIN_REG_BASE_RD(win_eth, bare, 0x290) 656 WIN_REG_BASE_RD(win_eth, epap, 0x294) 657 WIN_REG_BASE_WR(win_eth, bare, 0x290) 658 WIN_REG_BASE_WR(win_eth, epap, 0x294) 659 660 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 661 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 662 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 663 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 664 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 665 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 666 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 667 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 668 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); 669 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 670 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 671 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 672 673 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 674 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 675 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 676 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 677 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 678 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 679 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 680 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 681 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 682 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 683 684 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 685 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 686 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 687 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 688 #if defined(SOC_MV_ARMADA38X) 689 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 690 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 691 #endif 692 693 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 694 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 695 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 696 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 697 698 #ifndef SOC_MV_DOVE 699 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 700 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 701 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 702 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 703 #else 704 /* 705 * On 88F6781 (Dove) SoC DDR Controller is accessed through 706 * single MBUS <-> AXI bridge. In this case we provide emulated 707 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 708 * with common decoding windows setup code. 709 */ 710 711 static inline uint32_t ddr_br_read(int i) 712 { 713 uint32_t mmap; 714 715 /* Read Memory Address Map Register for CS i */ 716 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 717 718 /* Return CS i base address */ 719 return (mmap & 0xFF000000); 720 } 721 722 static inline uint32_t ddr_sz_read(int i) 723 { 724 uint32_t mmap, size; 725 726 /* Read Memory Address Map Register for CS i */ 727 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 728 729 /* Extract size of CS space in 64kB units */ 730 size = (1 << ((mmap >> 16) & 0x0F)); 731 732 /* Return CS size and enable/disable status */ 733 return (((size - 1) << 16) | (mmap & 0x01)); 734 } 735 #endif 736 737 /************************************************************************** 738 * Decode windows helper routines 739 **************************************************************************/ 740 void 741 soc_dump_decode_win(void) 742 { 743 uint32_t dev, rev; 744 int i; 745 746 soc_id(&dev, &rev); 747 748 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 749 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 750 win_cpu_cr_read(i), 751 win_cpu_br_read(i)); 752 753 if (win_cpu_can_remap(i)) 754 printf(", rl 0x%08x, rh 0x%08x", 755 win_cpu_remap_l_read(i), 756 win_cpu_remap_h_read(i)); 757 758 printf("\n"); 759 } 760 printf("Internal regs base: 0x%08x\n", 761 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 762 763 for (i = 0; i < MV_WIN_DDR_MAX; i++) 764 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 765 ddr_br_read(i), ddr_sz_read(i)); 766 } 767 768 /************************************************************************** 769 * CPU windows routines 770 **************************************************************************/ 771 int 772 win_cpu_can_remap(int i) 773 { 774 uint32_t dev, rev; 775 776 soc_id(&dev, &rev); 777 778 /* Depending on the SoC certain windows have remap capability */ 779 if ((dev == MV_DEV_88F5182 && i < 2) || 780 (dev == MV_DEV_88F5281 && i < 4) || 781 (dev == MV_DEV_88F6281 && i < 4) || 782 (dev == MV_DEV_88F6282 && i < 4) || 783 (dev == MV_DEV_88F6828 && i < 20) || 784 (dev == MV_DEV_88F6820 && i < 20) || 785 (dev == MV_DEV_88F6810 && i < 20) || 786 (dev == MV_DEV_88RC8180 && i < 2) || 787 (dev == MV_DEV_88F6781 && i < 4) || 788 (dev == MV_DEV_MV78100_Z0 && i < 8) || 789 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 790 return (1); 791 792 return (0); 793 } 794 795 /* XXX This should check for overlapping remap fields too.. */ 796 int 797 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 798 { 799 const struct decode_win *tab; 800 int i; 801 802 tab = wintab; 803 804 for (i = 0; i < win_no; i++, tab++) { 805 if (i == win) 806 /* Skip self */ 807 continue; 808 809 if ((tab->base + tab->size - 1) < (wintab + win)->base) 810 continue; 811 812 else if (((wintab + win)->base + (wintab + win)->size - 1) < 813 tab->base) 814 continue; 815 else 816 return (i); 817 } 818 819 return (-1); 820 } 821 822 static int 823 decode_win_cpu_valid(void) 824 { 825 int i, j, rv; 826 uint32_t b, e, s; 827 828 if (cpu_wins_no > MV_WIN_CPU_MAX) { 829 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 830 return (0); 831 } 832 833 rv = 1; 834 for (i = 0; i < cpu_wins_no; i++) { 835 836 if (cpu_wins[i].target == 0) { 837 printf("CPU window#%d: DDR target window is not " 838 "supposed to be reprogrammed!\n", i); 839 rv = 0; 840 } 841 842 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 843 printf("CPU window#%d: not capable of remapping, but " 844 "val 0x%08x defined\n", i, cpu_wins[i].remap); 845 rv = 0; 846 } 847 848 s = cpu_wins[i].size; 849 b = cpu_wins[i].base; 850 e = b + s - 1; 851 if (s > (0xFFFFFFFF - b + 1)) { 852 /* 853 * XXX this boundary check should account for 64bit 854 * and remapping.. 855 */ 856 printf("CPU window#%d: no space for size 0x%08x at " 857 "0x%08x\n", i, s, b); 858 rv = 0; 859 continue; 860 } 861 862 if (b != rounddown2(b, s)) { 863 printf("CPU window#%d: address 0x%08x is not aligned " 864 "to 0x%08x\n", i, b, s); 865 rv = 0; 866 continue; 867 } 868 869 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 870 if (j >= 0) { 871 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 872 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 873 cpu_wins[j].base, 874 cpu_wins[j].base + cpu_wins[j].size - 1); 875 rv = 0; 876 } 877 } 878 879 return (rv); 880 } 881 882 int 883 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 884 vm_paddr_t remap) 885 { 886 uint32_t br, cr; 887 int win, i; 888 889 if (remap == ~0) { 890 win = MV_WIN_CPU_MAX - 1; 891 i = -1; 892 } else { 893 win = 0; 894 i = 1; 895 } 896 897 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 898 cr = win_cpu_cr_read(win); 899 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 900 break; 901 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 902 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 903 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 904 (target << MV_WIN_CPU_TARGET_SHIFT))) 905 break; 906 win += i; 907 } 908 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 909 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 910 return (-1); 911 912 br = base & 0xffff0000; 913 win_cpu_br_write(win, br); 914 915 if (win_cpu_can_remap(win)) { 916 if (remap != ~0) { 917 win_cpu_remap_l_write(win, remap & 0xffff0000); 918 win_cpu_remap_h_write(win, 0); 919 } else { 920 /* 921 * Remap function is not used for a given window 922 * (capable of remapping) - set remap field with the 923 * same value as base. 924 */ 925 win_cpu_remap_l_write(win, base & 0xffff0000); 926 win_cpu_remap_h_write(win, 0); 927 } 928 } 929 930 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 931 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 932 win_cpu_cr_write(win, cr); 933 934 return (0); 935 } 936 937 static void 938 decode_win_cpu_setup(void) 939 { 940 int i; 941 942 /* Disable all CPU windows */ 943 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 944 win_cpu_cr_write(i, 0); 945 win_cpu_br_write(i, 0); 946 if (win_cpu_can_remap(i)) { 947 win_cpu_remap_l_write(i, 0); 948 win_cpu_remap_h_write(i, 0); 949 } 950 } 951 952 for (i = 0; i < cpu_wins_no; i++) 953 if (cpu_wins[i].target > 0) 954 decode_win_cpu_set(cpu_wins[i].target, 955 cpu_wins[i].attr, cpu_wins[i].base, 956 cpu_wins[i].size, cpu_wins[i].remap); 957 958 } 959 960 #ifdef SOC_MV_ARMADAXP 961 static int 962 decode_win_sdram_fixup(void) 963 { 964 struct mem_region mr[FDT_MEM_REGIONS]; 965 uint8_t window_valid[MV_WIN_DDR_MAX]; 966 int mr_cnt, err, i, j; 967 uint32_t valid_win_num = 0; 968 969 /* Grab physical memory regions information from device tree. */ 970 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 971 if (err != 0) 972 return (err); 973 974 for (i = 0; i < MV_WIN_DDR_MAX; i++) 975 window_valid[i] = 0; 976 977 /* Try to match entries from device tree with settings from u-boot */ 978 for (i = 0; i < mr_cnt; i++) { 979 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 980 if (ddr_is_active(j) && 981 (ddr_base(j) == mr[i].mr_start) && 982 (ddr_size(j) == mr[i].mr_size)) { 983 window_valid[j] = 1; 984 valid_win_num++; 985 } 986 } 987 } 988 989 if (mr_cnt != valid_win_num) 990 return (EINVAL); 991 992 /* Destroy windows without corresponding device tree entry */ 993 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 994 if (ddr_is_active(j) && (window_valid[j] != 1)) { 995 printf("Disabling SDRAM decoding window: %d\n", j); 996 ddr_disable(j); 997 } 998 } 999 1000 return (0); 1001 } 1002 #endif 1003 /* 1004 * Check if we're able to cover all active DDR banks. 1005 */ 1006 static int 1007 decode_win_can_cover_ddr(int max) 1008 { 1009 int i, c; 1010 1011 c = 0; 1012 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1013 if (ddr_is_active(i)) 1014 c++; 1015 1016 if (c > max) { 1017 printf("Unable to cover all active DDR banks: " 1018 "%d, available windows: %d\n", c, max); 1019 return (0); 1020 } 1021 1022 return (1); 1023 } 1024 1025 /************************************************************************** 1026 * DDR windows routines 1027 **************************************************************************/ 1028 int 1029 ddr_is_active(int i) 1030 { 1031 1032 if (ddr_sz_read(i) & 0x1) 1033 return (1); 1034 1035 return (0); 1036 } 1037 1038 void 1039 ddr_disable(int i) 1040 { 1041 1042 ddr_sz_write(i, 0); 1043 ddr_br_write(i, 0); 1044 } 1045 1046 uint32_t 1047 ddr_base(int i) 1048 { 1049 1050 return (ddr_br_read(i) & 0xff000000); 1051 } 1052 1053 uint32_t 1054 ddr_size(int i) 1055 { 1056 1057 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1058 } 1059 1060 uint32_t 1061 ddr_attr(int i) 1062 { 1063 uint32_t dev, rev; 1064 1065 soc_id(&dev, &rev); 1066 if (dev == MV_DEV_88RC8180) 1067 return ((ddr_sz_read(i) & 0xf0) >> 4); 1068 if (dev == MV_DEV_88F6781) 1069 return (0); 1070 1071 return (i == 0 ? 0xe : 1072 (i == 1 ? 0xd : 1073 (i == 2 ? 0xb : 1074 (i == 3 ? 0x7 : 0xff)))); 1075 } 1076 1077 uint32_t 1078 ddr_target(int i) 1079 { 1080 uint32_t dev, rev; 1081 1082 soc_id(&dev, &rev); 1083 if (dev == MV_DEV_88RC8180) { 1084 i = (ddr_sz_read(i) & 0xf0) >> 4; 1085 return (i == 0xe ? 0xc : 1086 (i == 0xd ? 0xd : 1087 (i == 0xb ? 0xe : 1088 (i == 0x7 ? 0xf : 0xc)))); 1089 } 1090 1091 /* 1092 * On SOCs other than 88RC8180 Mbus unit ID for 1093 * DDR SDRAM controller is always 0x0. 1094 */ 1095 return (0); 1096 } 1097 1098 /************************************************************************** 1099 * CESA windows routines 1100 **************************************************************************/ 1101 static int 1102 decode_win_cesa_valid(void) 1103 { 1104 1105 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1106 } 1107 1108 static void 1109 decode_win_cesa_dump(u_long base) 1110 { 1111 int i; 1112 1113 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1114 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1115 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1116 } 1117 1118 /* 1119 * Set CESA decode windows. 1120 */ 1121 static void 1122 decode_win_cesa_setup(u_long base) 1123 { 1124 uint32_t br, cr; 1125 uint64_t size; 1126 int i, j; 1127 1128 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1129 win_cesa_cr_write(base, i, 0); 1130 win_cesa_br_write(base, i, 0); 1131 } 1132 1133 /* Only access to active DRAM banks is required */ 1134 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1135 if (ddr_is_active(i)) { 1136 br = ddr_base(i); 1137 1138 size = ddr_size(i); 1139 #ifdef SOC_MV_ARMADA38X 1140 /* 1141 * Armada 38x SoC's equipped with 4GB DRAM 1142 * suffer freeze during CESA operation, if 1143 * MBUS window opened at given DRAM CS reaches 1144 * end of the address space. Apply a workaround 1145 * by setting the window size to the closest possible 1146 * value, i.e. divide it by 2. 1147 */ 1148 if (size + ddr_base(i) == 0x100000000ULL) 1149 size /= 2; 1150 #endif 1151 1152 cr = (((size - 1) & 0xffff0000) | 1153 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1154 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1155 IO_WIN_ENA_MASK); 1156 1157 /* Set the first free CESA window */ 1158 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1159 if (win_cesa_cr_read(base, j) & 0x1) 1160 continue; 1161 1162 win_cesa_br_write(base, j, br); 1163 win_cesa_cr_write(base, j, cr); 1164 break; 1165 } 1166 } 1167 } 1168 } 1169 1170 /************************************************************************** 1171 * USB windows routines 1172 **************************************************************************/ 1173 static int 1174 decode_win_usb_valid(void) 1175 { 1176 1177 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1178 } 1179 1180 static void 1181 decode_win_usb_dump(u_long base) 1182 { 1183 int i; 1184 1185 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1186 return; 1187 1188 for (i = 0; i < MV_WIN_USB_MAX; i++) 1189 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1190 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1191 } 1192 1193 /* 1194 * Set USB decode windows. 1195 */ 1196 static void 1197 decode_win_usb_setup(u_long base) 1198 { 1199 uint32_t br, cr; 1200 int i, j; 1201 1202 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1203 return; 1204 1205 usb_port++; 1206 1207 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1208 win_usb_cr_write(base, i, 0); 1209 win_usb_br_write(base, i, 0); 1210 } 1211 1212 /* Only access to active DRAM banks is required */ 1213 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1214 if (ddr_is_active(i)) { 1215 br = ddr_base(i); 1216 /* 1217 * XXX for 6281 we should handle Mbus write 1218 * burst limit field in the ctrl reg 1219 */ 1220 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1221 (ddr_attr(i) << 8) | 1222 (ddr_target(i) << 4) | 1); 1223 1224 /* Set the first free USB window */ 1225 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1226 if (win_usb_cr_read(base, j) & 0x1) 1227 continue; 1228 1229 win_usb_br_write(base, j, br); 1230 win_usb_cr_write(base, j, cr); 1231 break; 1232 } 1233 } 1234 } 1235 } 1236 1237 /************************************************************************** 1238 * USB3 windows routines 1239 **************************************************************************/ 1240 #ifdef SOC_MV_ARMADA38X 1241 static int 1242 decode_win_usb3_valid(void) 1243 { 1244 1245 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1246 } 1247 1248 static void 1249 decode_win_usb3_dump(u_long base) 1250 { 1251 int i; 1252 1253 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1254 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1255 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1256 } 1257 1258 /* 1259 * Set USB3 decode windows 1260 */ 1261 static void 1262 decode_win_usb3_setup(u_long base) 1263 { 1264 uint32_t br, cr; 1265 int i, j; 1266 1267 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1268 win_usb3_cr_write(base, i, 0); 1269 win_usb3_br_write(base, i, 0); 1270 } 1271 1272 /* Only access to active DRAM banks is required */ 1273 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1274 if (ddr_is_active(i)) { 1275 br = ddr_base(i); 1276 cr = (((ddr_size(i) - 1) & 1277 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1278 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1279 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1280 IO_WIN_ENA_MASK); 1281 1282 /* Set the first free USB3.0 window */ 1283 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1284 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1285 continue; 1286 1287 win_usb3_br_write(base, j, br); 1288 win_usb3_cr_write(base, j, cr); 1289 break; 1290 } 1291 } 1292 } 1293 } 1294 #else 1295 /* 1296 * Provide dummy functions to satisfy the build 1297 * for SoCs not equipped with USB3 1298 */ 1299 static int 1300 decode_win_usb3_valid(void) 1301 { 1302 1303 return (1); 1304 } 1305 1306 static void 1307 decode_win_usb3_setup(u_long base) 1308 { 1309 } 1310 1311 static void 1312 decode_win_usb3_dump(u_long base) 1313 { 1314 } 1315 #endif 1316 /************************************************************************** 1317 * ETH windows routines 1318 **************************************************************************/ 1319 1320 static int 1321 win_eth_can_remap(int i) 1322 { 1323 1324 /* ETH encode windows 0-3 have remap capability */ 1325 if (i < 4) 1326 return (1); 1327 1328 return (0); 1329 } 1330 1331 static int 1332 eth_bare_read(uint32_t base, int i) 1333 { 1334 uint32_t v; 1335 1336 v = win_eth_bare_read(base); 1337 v &= (1 << i); 1338 1339 return (v >> i); 1340 } 1341 1342 static void 1343 eth_bare_write(uint32_t base, int i, int val) 1344 { 1345 uint32_t v; 1346 1347 v = win_eth_bare_read(base); 1348 v &= ~(1 << i); 1349 v |= (val << i); 1350 win_eth_bare_write(base, v); 1351 } 1352 1353 static void 1354 eth_epap_write(uint32_t base, int i, int val) 1355 { 1356 uint32_t v; 1357 1358 v = win_eth_epap_read(base); 1359 v &= ~(0x3 << (i * 2)); 1360 v |= (val << (i * 2)); 1361 win_eth_epap_write(base, v); 1362 } 1363 1364 static void 1365 decode_win_eth_dump(u_long base) 1366 { 1367 int i; 1368 1369 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1370 return; 1371 1372 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1373 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1374 win_eth_br_read(base, i), 1375 win_eth_sz_read(base, i)); 1376 1377 if (win_eth_can_remap(i)) 1378 printf(", ha 0x%08x", 1379 win_eth_har_read(base, i)); 1380 1381 printf("\n"); 1382 } 1383 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1384 win_eth_bare_read(base), 1385 win_eth_epap_read(base)); 1386 } 1387 1388 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1389 1390 static void 1391 decode_win_eth_setup(u_long base) 1392 { 1393 uint32_t br, sz; 1394 int i, j; 1395 1396 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1397 return; 1398 1399 eth_port++; 1400 1401 /* Disable, clear and revoke protection for all ETH windows */ 1402 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1403 1404 eth_bare_write(base, i, 1); 1405 eth_epap_write(base, i, 0); 1406 win_eth_br_write(base, i, 0); 1407 win_eth_sz_write(base, i, 0); 1408 if (win_eth_can_remap(i)) 1409 win_eth_har_write(base, i, 0); 1410 } 1411 1412 /* Only access to active DRAM banks is required */ 1413 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1414 if (ddr_is_active(i)) { 1415 1416 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1417 sz = ((ddr_size(i) - 1) & 0xffff0000); 1418 1419 /* Set the first free ETH window */ 1420 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1421 if (eth_bare_read(base, j) == 0) 1422 continue; 1423 1424 win_eth_br_write(base, j, br); 1425 win_eth_sz_write(base, j, sz); 1426 1427 /* XXX remapping ETH windows not supported */ 1428 1429 /* Set protection RW */ 1430 eth_epap_write(base, j, 0x3); 1431 1432 /* Enable window */ 1433 eth_bare_write(base, j, 0); 1434 break; 1435 } 1436 } 1437 } 1438 1439 static void 1440 decode_win_neta_dump(u_long base) 1441 { 1442 1443 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); 1444 } 1445 1446 static void 1447 decode_win_neta_setup(u_long base) 1448 { 1449 1450 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); 1451 } 1452 1453 static int 1454 decode_win_eth_valid(void) 1455 { 1456 1457 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1458 } 1459 1460 /************************************************************************** 1461 * PCIE windows routines 1462 **************************************************************************/ 1463 static void 1464 decode_win_pcie_dump(u_long base) 1465 { 1466 int i; 1467 1468 printf("PCIE windows base 0x%08lx\n", base); 1469 for (i = 0; i < MV_WIN_PCIE_MAX; i++) 1470 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", 1471 i, win_pcie_cr_read(base, i), 1472 win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); 1473 1474 for (i = 0; i < MV_PCIE_BAR_MAX; i++) 1475 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", 1476 i, pcie_bar_cr_read(base, i), 1477 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); 1478 } 1479 1480 void 1481 decode_win_pcie_setup(u_long base) 1482 { 1483 uint32_t size = 0, ddrbase = ~0; 1484 uint32_t cr, br; 1485 int i, j; 1486 1487 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1488 pcie_bar_br_write(base, i, 1489 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1490 if (i < 3) 1491 pcie_bar_brh_write(base, i, 0); 1492 if (i > 0) 1493 pcie_bar_cr_write(base, i, 0); 1494 } 1495 1496 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1497 win_pcie_cr_write(base, i, 0); 1498 win_pcie_br_write(base, i, 0); 1499 win_pcie_remap_write(base, i, 0); 1500 } 1501 1502 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1503 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1504 & MV_PCIE_ROOT_CMPLX) == 0) { 1505 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1506 return; 1507 } 1508 1509 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1510 if (ddr_is_active(i)) { 1511 /* Map DDR to BAR 1 */ 1512 cr = (ddr_size(i) - 1) & 0xffff0000; 1513 size += ddr_size(i) & 0xffff0000; 1514 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1515 br = ddr_base(i); 1516 if (br < ddrbase) 1517 ddrbase = br; 1518 1519 /* Use the first available PCIE window */ 1520 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1521 if (win_pcie_cr_read(base, j) != 0) 1522 continue; 1523 1524 win_pcie_br_write(base, j, br); 1525 win_pcie_cr_write(base, j, cr); 1526 break; 1527 } 1528 } 1529 } 1530 1531 /* 1532 * Upper 16 bits in BAR register is interpreted as BAR size 1533 * (in 64 kB units) plus 64kB, so subtract 0x10000 1534 * form value passed to register to get correct value. 1535 */ 1536 size -= 0x10000; 1537 pcie_bar_cr_write(base, 1, size | 1); 1538 pcie_bar_br_write(base, 1, ddrbase | 1539 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1540 pcie_bar_br_write(base, 0, fdt_immr_pa | 1541 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1542 } 1543 1544 static int 1545 decode_win_pcie_valid(void) 1546 { 1547 1548 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1549 } 1550 1551 /************************************************************************** 1552 * IDMA windows routines 1553 **************************************************************************/ 1554 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1555 static int 1556 idma_bare_read(u_long base, int i) 1557 { 1558 uint32_t v; 1559 1560 v = win_idma_bare_read(base); 1561 v &= (1 << i); 1562 1563 return (v >> i); 1564 } 1565 1566 static void 1567 idma_bare_write(u_long base, int i, int val) 1568 { 1569 uint32_t v; 1570 1571 v = win_idma_bare_read(base); 1572 v &= ~(1 << i); 1573 v |= (val << i); 1574 win_idma_bare_write(base, v); 1575 } 1576 1577 /* 1578 * Sets channel protection 'val' for window 'w' on channel 'c' 1579 */ 1580 static void 1581 idma_cap_write(u_long base, int c, int w, int val) 1582 { 1583 uint32_t v; 1584 1585 v = win_idma_cap_read(base, c); 1586 v &= ~(0x3 << (w * 2)); 1587 v |= (val << (w * 2)); 1588 win_idma_cap_write(base, c, v); 1589 } 1590 1591 /* 1592 * Set protection 'val' on all channels for window 'w' 1593 */ 1594 static void 1595 idma_set_prot(u_long base, int w, int val) 1596 { 1597 int c; 1598 1599 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1600 idma_cap_write(base, c, w, val); 1601 } 1602 1603 static int 1604 win_idma_can_remap(int i) 1605 { 1606 1607 /* IDMA decode windows 0-3 have remap capability */ 1608 if (i < 4) 1609 return (1); 1610 1611 return (0); 1612 } 1613 1614 void 1615 decode_win_idma_setup(u_long base) 1616 { 1617 uint32_t br, sz; 1618 int i, j; 1619 1620 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1621 return; 1622 /* 1623 * Disable and clear all IDMA windows, revoke protection for all channels 1624 */ 1625 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1626 1627 idma_bare_write(base, i, 1); 1628 win_idma_br_write(base, i, 0); 1629 win_idma_sz_write(base, i, 0); 1630 if (win_idma_can_remap(i) == 1) 1631 win_idma_har_write(base, i, 0); 1632 } 1633 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1634 win_idma_cap_write(base, i, 0); 1635 1636 /* 1637 * Set up access to all active DRAM banks 1638 */ 1639 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1640 if (ddr_is_active(i)) { 1641 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1642 sz = ((ddr_size(i) - 1) & 0xffff0000); 1643 1644 /* Place DDR entries in non-remapped windows */ 1645 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1646 if (win_idma_can_remap(j) != 1 && 1647 idma_bare_read(base, j) == 1) { 1648 1649 /* Configure window */ 1650 win_idma_br_write(base, j, br); 1651 win_idma_sz_write(base, j, sz); 1652 1653 /* Set protection RW on all channels */ 1654 idma_set_prot(base, j, 0x3); 1655 1656 /* Enable window */ 1657 idma_bare_write(base, j, 0); 1658 break; 1659 } 1660 } 1661 1662 /* 1663 * Remaining targets -- from statically defined table 1664 */ 1665 for (i = 0; i < idma_wins_no; i++) 1666 if (idma_wins[i].target > 0) { 1667 br = (idma_wins[i].base & 0xffff0000) | 1668 (idma_wins[i].attr << 8) | idma_wins[i].target; 1669 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1670 1671 /* Set the first free IDMA window */ 1672 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1673 if (idma_bare_read(base, j) == 0) 1674 continue; 1675 1676 /* Configure window */ 1677 win_idma_br_write(base, j, br); 1678 win_idma_sz_write(base, j, sz); 1679 if (win_idma_can_remap(j) && 1680 idma_wins[j].remap >= 0) 1681 win_idma_har_write(base, j, 1682 idma_wins[j].remap); 1683 1684 /* Set protection RW on all channels */ 1685 idma_set_prot(base, j, 0x3); 1686 1687 /* Enable window */ 1688 idma_bare_write(base, j, 0); 1689 break; 1690 } 1691 } 1692 } 1693 1694 int 1695 decode_win_idma_valid(void) 1696 { 1697 const struct decode_win *wintab; 1698 int c, i, j, rv; 1699 uint32_t b, e, s; 1700 1701 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1702 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1703 return (0); 1704 } 1705 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1706 if (ddr_is_active(i)) 1707 c++; 1708 1709 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1710 printf("IDMA windows: too many entries: %d, available: %d\n", 1711 idma_wins_no, MV_WIN_IDMA_MAX - c); 1712 return (0); 1713 } 1714 1715 wintab = idma_wins; 1716 rv = 1; 1717 for (i = 0; i < idma_wins_no; i++, wintab++) { 1718 1719 if (wintab->target == 0) { 1720 printf("IDMA window#%d: DDR target window is not " 1721 "supposed to be reprogrammed!\n", i); 1722 rv = 0; 1723 } 1724 1725 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1726 printf("IDMA window#%d: not capable of remapping, but " 1727 "val 0x%08x defined\n", i, wintab->remap); 1728 rv = 0; 1729 } 1730 1731 s = wintab->size; 1732 b = wintab->base; 1733 e = b + s - 1; 1734 if (s > (0xFFFFFFFF - b + 1)) { 1735 /* XXX this boundary check should account for 64bit and 1736 * remapping.. */ 1737 printf("IDMA window#%d: no space for size 0x%08x at " 1738 "0x%08x\n", i, s, b); 1739 rv = 0; 1740 continue; 1741 } 1742 1743 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1744 if (j >= 0) { 1745 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1746 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1747 idma_wins[j].base, 1748 idma_wins[j].base + idma_wins[j].size - 1); 1749 rv = 0; 1750 } 1751 } 1752 1753 return (rv); 1754 } 1755 1756 void 1757 decode_win_idma_dump(u_long base) 1758 { 1759 int i; 1760 1761 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1762 return; 1763 1764 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1765 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1766 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1767 1768 if (win_idma_can_remap(i)) 1769 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1770 1771 printf("\n"); 1772 } 1773 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1774 printf("IDMA channel#%d: ap 0x%08x\n", i, 1775 win_idma_cap_read(base, i)); 1776 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1777 } 1778 #else 1779 1780 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1781 int 1782 decode_win_idma_valid(void) 1783 { 1784 1785 return (1); 1786 } 1787 1788 void 1789 decode_win_idma_setup(u_long base) 1790 { 1791 } 1792 1793 void 1794 decode_win_idma_dump(u_long base) 1795 { 1796 } 1797 #endif 1798 1799 /************************************************************************** 1800 * XOR windows routines 1801 **************************************************************************/ 1802 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1803 static int 1804 xor_ctrl_read(u_long base, int i, int c, int e) 1805 { 1806 uint32_t v; 1807 v = win_xor_ctrl_read(base, c, e); 1808 v &= (1 << i); 1809 1810 return (v >> i); 1811 } 1812 1813 static void 1814 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1815 { 1816 uint32_t v; 1817 1818 v = win_xor_ctrl_read(base, c, e); 1819 v &= ~(1 << i); 1820 v |= (val << i); 1821 win_xor_ctrl_write(base, c, e, v); 1822 } 1823 1824 /* 1825 * Set channel protection 'val' for window 'w' on channel 'c' 1826 */ 1827 static void 1828 xor_chan_write(u_long base, int c, int e, int w, int val) 1829 { 1830 uint32_t v; 1831 1832 v = win_xor_ctrl_read(base, c, e); 1833 v &= ~(0x3 << (w * 2 + 16)); 1834 v |= (val << (w * 2 + 16)); 1835 win_xor_ctrl_write(base, c, e, v); 1836 } 1837 1838 /* 1839 * Set protection 'val' on all channels for window 'w' on engine 'e' 1840 */ 1841 static void 1842 xor_set_prot(u_long base, int w, int e, int val) 1843 { 1844 int c; 1845 1846 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1847 xor_chan_write(base, c, e, w, val); 1848 } 1849 1850 static int 1851 win_xor_can_remap(int i) 1852 { 1853 1854 /* XOR decode windows 0-3 have remap capability */ 1855 if (i < 4) 1856 return (1); 1857 1858 return (0); 1859 } 1860 1861 static int 1862 xor_max_eng(void) 1863 { 1864 uint32_t dev, rev; 1865 1866 soc_id(&dev, &rev); 1867 switch (dev) { 1868 case MV_DEV_88F6281: 1869 case MV_DEV_88F6282: 1870 case MV_DEV_MV78130: 1871 case MV_DEV_MV78160: 1872 case MV_DEV_MV78230: 1873 case MV_DEV_MV78260: 1874 case MV_DEV_MV78460: 1875 return (2); 1876 case MV_DEV_MV78100: 1877 case MV_DEV_MV78100_Z0: 1878 return (1); 1879 default: 1880 return (0); 1881 } 1882 } 1883 1884 static void 1885 xor_active_dram(u_long base, int c, int e, int *window) 1886 { 1887 uint32_t br, sz; 1888 int i, m, w; 1889 1890 /* 1891 * Set up access to all active DRAM banks 1892 */ 1893 m = xor_max_eng(); 1894 for (i = 0; i < m; i++) 1895 if (ddr_is_active(i)) { 1896 br = ddr_base(i) | (ddr_attr(i) << 8) | 1897 ddr_target(i); 1898 sz = ((ddr_size(i) - 1) & 0xffff0000); 1899 1900 /* Place DDR entries in non-remapped windows */ 1901 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1902 if (win_xor_can_remap(w) != 1 && 1903 (xor_ctrl_read(base, w, c, e) == 0) && 1904 w > *window) { 1905 /* Configure window */ 1906 win_xor_br_write(base, w, e, br); 1907 win_xor_sz_write(base, w, e, sz); 1908 1909 /* Set protection RW on all channels */ 1910 xor_set_prot(base, w, e, 0x3); 1911 1912 /* Enable window */ 1913 xor_ctrl_write(base, w, c, e, 1); 1914 (*window)++; 1915 break; 1916 } 1917 } 1918 } 1919 1920 void 1921 decode_win_xor_setup(u_long base) 1922 { 1923 uint32_t br, sz; 1924 int i, j, z, e = 1, m, window; 1925 1926 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1927 return; 1928 1929 /* 1930 * Disable and clear all XOR windows, revoke protection for all 1931 * channels 1932 */ 1933 m = xor_max_eng(); 1934 for (j = 0; j < m; j++, e--) { 1935 1936 /* Number of non-remaped windows */ 1937 window = MV_XOR_NON_REMAP - 1; 1938 1939 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1940 win_xor_br_write(base, i, e, 0); 1941 win_xor_sz_write(base, i, e, 0); 1942 } 1943 1944 if (win_xor_can_remap(i) == 1) 1945 win_xor_har_write(base, i, e, 0); 1946 1947 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1948 win_xor_ctrl_write(base, i, e, 0); 1949 xor_active_dram(base, i, e, &window); 1950 } 1951 1952 /* 1953 * Remaining targets -- from a statically defined table 1954 */ 1955 for (i = 0; i < xor_wins_no; i++) 1956 if (xor_wins[i].target > 0) { 1957 br = (xor_wins[i].base & 0xffff0000) | 1958 (xor_wins[i].attr << 8) | 1959 xor_wins[i].target; 1960 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1961 1962 /* Set the first free XOR window */ 1963 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1964 if (xor_ctrl_read(base, z, 0, e) && 1965 xor_ctrl_read(base, z, 1, e)) 1966 continue; 1967 1968 /* Configure window */ 1969 win_xor_br_write(base, z, e, br); 1970 win_xor_sz_write(base, z, e, sz); 1971 if (win_xor_can_remap(z) && 1972 xor_wins[z].remap >= 0) 1973 win_xor_har_write(base, z, e, 1974 xor_wins[z].remap); 1975 1976 /* Set protection RW on all channels */ 1977 xor_set_prot(base, z, e, 0x3); 1978 1979 /* Enable window */ 1980 xor_ctrl_write(base, z, 0, e, 1); 1981 xor_ctrl_write(base, z, 1, e, 1); 1982 break; 1983 } 1984 } 1985 } 1986 } 1987 1988 int 1989 decode_win_xor_valid(void) 1990 { 1991 const struct decode_win *wintab; 1992 int c, i, j, rv; 1993 uint32_t b, e, s; 1994 1995 if (xor_wins_no > MV_WIN_XOR_MAX) { 1996 printf("XOR windows: too many entries: %d\n", xor_wins_no); 1997 return (0); 1998 } 1999 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 2000 if (ddr_is_active(i)) 2001 c++; 2002 2003 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 2004 printf("XOR windows: too many entries: %d, available: %d\n", 2005 xor_wins_no, MV_WIN_IDMA_MAX - c); 2006 return (0); 2007 } 2008 2009 wintab = xor_wins; 2010 rv = 1; 2011 for (i = 0; i < xor_wins_no; i++, wintab++) { 2012 2013 if (wintab->target == 0) { 2014 printf("XOR window#%d: DDR target window is not " 2015 "supposed to be reprogrammed!\n", i); 2016 rv = 0; 2017 } 2018 2019 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 2020 printf("XOR window#%d: not capable of remapping, but " 2021 "val 0x%08x defined\n", i, wintab->remap); 2022 rv = 0; 2023 } 2024 2025 s = wintab->size; 2026 b = wintab->base; 2027 e = b + s - 1; 2028 if (s > (0xFFFFFFFF - b + 1)) { 2029 /* 2030 * XXX this boundary check should account for 64bit 2031 * and remapping.. 2032 */ 2033 printf("XOR window#%d: no space for size 0x%08x at " 2034 "0x%08x\n", i, s, b); 2035 rv = 0; 2036 continue; 2037 } 2038 2039 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 2040 if (j >= 0) { 2041 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 2042 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2043 xor_wins[j].base, 2044 xor_wins[j].base + xor_wins[j].size - 1); 2045 rv = 0; 2046 } 2047 } 2048 2049 return (rv); 2050 } 2051 2052 void 2053 decode_win_xor_dump(u_long base) 2054 { 2055 int i, j; 2056 int e = 1; 2057 2058 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2059 return; 2060 2061 for (j = 0; j < xor_max_eng(); j++, e--) { 2062 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2063 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2064 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2065 2066 if (win_xor_can_remap(i)) 2067 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2068 2069 printf("\n"); 2070 } 2071 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2072 printf("XOR control#%d: 0x%08x\n", i, 2073 win_xor_ctrl_read(base, i, e)); 2074 } 2075 } 2076 2077 #else 2078 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2079 static int 2080 decode_win_xor_valid(void) 2081 { 2082 2083 return (1); 2084 } 2085 2086 static void 2087 decode_win_xor_setup(u_long base) 2088 { 2089 } 2090 2091 static void 2092 decode_win_xor_dump(u_long base) 2093 { 2094 } 2095 #endif 2096 2097 /************************************************************************** 2098 * SATA windows routines 2099 **************************************************************************/ 2100 static void 2101 decode_win_sata_setup(u_long base) 2102 { 2103 uint32_t cr, br; 2104 int i, j; 2105 2106 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2107 return; 2108 2109 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2110 win_sata_cr_write(base, i, 0); 2111 win_sata_br_write(base, i, 0); 2112 } 2113 2114 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2115 if (ddr_is_active(i)) { 2116 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2117 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2118 br = ddr_base(i); 2119 2120 /* Use the first available SATA window */ 2121 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2122 if ((win_sata_cr_read(base, j) & 1) != 0) 2123 continue; 2124 2125 win_sata_br_write(base, j, br); 2126 win_sata_cr_write(base, j, cr); 2127 break; 2128 } 2129 } 2130 } 2131 2132 #ifdef SOC_MV_ARMADA38X 2133 /* 2134 * Configure AHCI decoding windows 2135 */ 2136 static void 2137 decode_win_ahci_setup(u_long base) 2138 { 2139 uint32_t br, cr, sz; 2140 int i, j; 2141 2142 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2143 win_sata_cr_write(base, i, 0); 2144 win_sata_br_write(base, i, 0); 2145 win_sata_sz_write(base, i, 0); 2146 } 2147 2148 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2149 if (ddr_is_active(i)) { 2150 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2151 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2152 IO_WIN_ENA_MASK; 2153 br = ddr_base(i); 2154 sz = (ddr_size(i) - 1) & 2155 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2156 2157 /* Use first available SATA window */ 2158 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2159 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2160 continue; 2161 2162 /* BASE is set to DRAM base (0x00000000) */ 2163 win_sata_br_write(base, j, br); 2164 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2165 win_sata_cr_write(base, j, cr); 2166 /* SIZE is set to 16MB - max value */ 2167 win_sata_sz_write(base, j, sz); 2168 break; 2169 } 2170 } 2171 } 2172 } 2173 2174 static void 2175 decode_win_ahci_dump(u_long base) 2176 { 2177 int i; 2178 2179 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2180 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2181 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2182 win_sata_sz_read(base,i)); 2183 } 2184 2185 #else 2186 /* 2187 * Provide dummy functions to satisfy the build 2188 * for SoC's not equipped with AHCI controller 2189 */ 2190 static void 2191 decode_win_ahci_setup(u_long base) 2192 { 2193 } 2194 2195 static void 2196 decode_win_ahci_dump(u_long base) 2197 { 2198 } 2199 #endif 2200 2201 static int 2202 decode_win_sata_valid(void) 2203 { 2204 uint32_t dev, rev; 2205 2206 soc_id(&dev, &rev); 2207 if (dev == MV_DEV_88F5281) 2208 return (1); 2209 2210 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2211 } 2212 2213 static void 2214 decode_win_sdhci_setup(u_long base) 2215 { 2216 uint32_t cr, br; 2217 int i, j; 2218 2219 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2220 win_sdhci_cr_write(base, i, 0); 2221 win_sdhci_br_write(base, i, 0); 2222 } 2223 2224 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2225 if (ddr_is_active(i)) { 2226 br = ddr_base(i); 2227 cr = (((ddr_size(i) - 1) & 2228 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2229 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2230 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2231 IO_WIN_ENA_MASK); 2232 2233 /* Use the first available SDHCI window */ 2234 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2235 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2236 continue; 2237 2238 win_sdhci_cr_write(base, j, cr); 2239 win_sdhci_br_write(base, j, br); 2240 break; 2241 } 2242 } 2243 } 2244 2245 static void 2246 decode_win_sdhci_dump(u_long base) 2247 { 2248 int i; 2249 2250 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2251 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2252 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2253 } 2254 2255 static int 2256 decode_win_sdhci_valid(void) 2257 { 2258 2259 #ifdef SOC_MV_ARMADA38X 2260 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2261 #endif 2262 2263 /* Satisfy platforms not equipped with this controller. */ 2264 return (1); 2265 } 2266 2267 /************************************************************************** 2268 * FDT parsing routines. 2269 **************************************************************************/ 2270 2271 static int 2272 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2273 int *tuplesize) 2274 { 2275 phandle_t node; 2276 pcell_t addr_cells, par_addr_cells, size_cells; 2277 int len, tuple_size, tuples_count; 2278 2279 node = OF_finddevice(nodename); 2280 if (node == -1) 2281 return (EINVAL); 2282 2283 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2284 return (ENXIO); 2285 2286 par_addr_cells = fdt_parent_addr_cells(node); 2287 if (par_addr_cells > 2) 2288 return (ERANGE); 2289 2290 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2291 size_cells); 2292 2293 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2294 len = OF_getprop(node, "ranges", buf, size); 2295 2296 /* 2297 * XXX this does not handle the empty 'ranges;' case, which is 2298 * legitimate and should be allowed. 2299 */ 2300 tuples_count = len / tuple_size; 2301 if (tuples_count <= 0) 2302 return (ERANGE); 2303 2304 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2305 return (ERANGE); 2306 2307 *tuples = tuples_count; 2308 *tuplesize = tuple_size; 2309 return (0); 2310 } 2311 2312 static int 2313 win_cpu_from_dt(void) 2314 { 2315 pcell_t ranges[48]; 2316 phandle_t node; 2317 int i, entry_size, err, t, tuple_size, tuples; 2318 u_long sram_base, sram_size; 2319 2320 t = 0; 2321 /* Retrieve 'ranges' property of '/localbus' node. */ 2322 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2323 &tuples, &tuple_size)) == 0) { 2324 /* 2325 * Fill CPU decode windows table. 2326 */ 2327 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2328 2329 entry_size = tuple_size / sizeof(pcell_t); 2330 cpu_wins_no = tuples; 2331 2332 /* Check range */ 2333 if (tuples > nitems(cpu_win_tbl)) { 2334 debugf("too many tuples to fit into cpu_win_tbl\n"); 2335 return (ENOMEM); 2336 } 2337 2338 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2339 cpu_win_tbl[t].target = 1; 2340 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2341 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2342 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2343 cpu_win_tbl[t].remap = ~0; 2344 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2345 "size = 0x%0x remap = 0x%0x\n", 2346 cpu_win_tbl[t].target, 2347 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2348 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2349 } 2350 } 2351 2352 /* 2353 * Retrieve CESA SRAM data. 2354 */ 2355 if ((node = OF_finddevice("sram")) != -1) 2356 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2357 goto moveon; 2358 2359 if ((node = OF_finddevice("/")) == 0) 2360 return (ENXIO); 2361 2362 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2363 /* SRAM block is not always present. */ 2364 return (0); 2365 moveon: 2366 sram_base = sram_size = 0; 2367 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2368 return (EINVAL); 2369 2370 /* Check range */ 2371 if (t >= nitems(cpu_win_tbl)) { 2372 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2373 return (ENOMEM); 2374 } 2375 2376 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2377 #ifdef SOC_MV_ARMADA38X 2378 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2379 #else 2380 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2381 #endif 2382 cpu_win_tbl[t].base = sram_base; 2383 cpu_win_tbl[t].size = sram_size; 2384 cpu_win_tbl[t].remap = ~0; 2385 cpu_wins_no++; 2386 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2387 2388 /* Check if there is a second CESA node */ 2389 while ((node = OF_peer(node)) != 0) { 2390 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2391 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2392 return (EINVAL); 2393 break; 2394 } 2395 } 2396 2397 if (node == 0) 2398 return (0); 2399 2400 t++; 2401 if (t >= nitems(cpu_win_tbl)) { 2402 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2403 return (ENOMEM); 2404 } 2405 2406 /* Configure window for CESA1 */ 2407 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2408 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2409 cpu_win_tbl[t].base = sram_base; 2410 cpu_win_tbl[t].size = sram_size; 2411 cpu_win_tbl[t].remap = ~0; 2412 cpu_wins_no++; 2413 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2414 2415 return (0); 2416 } 2417 2418 static int 2419 fdt_win_process(phandle_t child) 2420 { 2421 int i; 2422 struct soc_node_spec *soc_node; 2423 int addr_cells, size_cells; 2424 pcell_t reg[8]; 2425 u_long size, base; 2426 2427 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2428 2429 soc_node = &soc_nodes[i]; 2430 2431 /* Setup only for enabled devices */ 2432 if (ofw_bus_node_status_okay(child) == 0) 2433 continue; 2434 2435 if (!ofw_bus_node_is_compatible(child, soc_node->compat)) 2436 continue; 2437 2438 if (fdt_addrsize_cells(OF_parent(child), &addr_cells, 2439 &size_cells)) 2440 return (ENXIO); 2441 2442 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) 2443 return (ENOMEM); 2444 2445 if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) 2446 return (EINVAL); 2447 2448 if (addr_cells <= 2) 2449 base = fdt_data_get(®[0], addr_cells); 2450 else 2451 base = fdt_data_get(®[addr_cells - 2], 2); 2452 size = fdt_data_get(®[addr_cells], size_cells); 2453 2454 base = (base & 0x000fffff) | fdt_immr_va; 2455 if (soc_node->decode_handler != NULL) 2456 soc_node->decode_handler(base); 2457 else 2458 return (ENXIO); 2459 2460 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2461 soc_node->dump_handler(base); 2462 } 2463 2464 return (0); 2465 } 2466 static int 2467 fdt_win_setup(void) 2468 { 2469 phandle_t node, child, sb; 2470 phandle_t child_pci; 2471 int err; 2472 2473 sb = 0; 2474 node = OF_finddevice("/"); 2475 if (node == -1) 2476 panic("fdt_win_setup: no root node"); 2477 2478 /* 2479 * Traverse through all children of root and simple-bus nodes. 2480 * For each found device retrieve decode windows data (if applicable). 2481 */ 2482 child = OF_child(node); 2483 while (child != 0) { 2484 /* Lookup for callback and run */ 2485 err = fdt_win_process(child); 2486 if (err != 0) 2487 return (err); 2488 2489 /* Process Marvell Armada-XP/38x PCIe controllers */ 2490 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { 2491 child_pci = OF_child(child); 2492 while (child_pci != 0) { 2493 err = fdt_win_process(child_pci); 2494 if (err != 0) 2495 return (err); 2496 2497 child_pci = OF_peer(child_pci); 2498 } 2499 } 2500 2501 /* 2502 * Once done with root-level children let's move down to 2503 * simple-bus and its children. 2504 */ 2505 child = OF_peer(child); 2506 if ((child == 0) && (node == OF_finddevice("/"))) { 2507 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2508 if (node == 0) 2509 return (ENXIO); 2510 child = OF_child(node); 2511 } 2512 /* 2513 * Next, move one more level down to internal-regs node (if 2514 * it is present) and its children. This node also have 2515 * "simple-bus" compatible. 2516 */ 2517 if ((child == 0) && (node == sb)) { 2518 node = fdt_find_compatible(node, "simple-bus", 0); 2519 if (node == 0) 2520 return (0); 2521 child = OF_child(node); 2522 } 2523 } 2524 2525 return (0); 2526 } 2527 2528 static void 2529 fdt_fixup_busfreq(phandle_t root) 2530 { 2531 phandle_t sb; 2532 pcell_t freq; 2533 2534 freq = cpu_to_fdt32(get_tclk()); 2535 2536 /* 2537 * Fix bus speed in cpu node 2538 */ 2539 if ((sb = OF_finddevice("cpu")) != 0) 2540 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2541 OF_setprop(sb, "bus-frequency", (void *)&freq, 2542 sizeof(freq)); 2543 2544 /* 2545 * This fixup sets the simple-bus bus-frequency property. 2546 */ 2547 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2548 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2549 } 2550 2551 static void 2552 fdt_fixup_ranges(phandle_t root) 2553 { 2554 phandle_t node; 2555 pcell_t par_addr_cells, addr_cells, size_cells; 2556 pcell_t ranges[3], reg[2], *rangesptr; 2557 int len, tuple_size, tuples_count; 2558 uint32_t base; 2559 2560 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2561 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2562 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2563 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2564 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2565 addr_cells + size_cells); 2566 len = OF_getprop(node, "ranges", ranges, 2567 sizeof(ranges)); 2568 tuples_count = len / tuple_size; 2569 /* Unexpected settings are not supported */ 2570 if (tuples_count != 1) 2571 goto fixup_failed; 2572 2573 rangesptr = &ranges[0]; 2574 rangesptr += par_addr_cells; 2575 base = fdt_data_get((void *)rangesptr, addr_cells); 2576 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2577 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2578 sizeof(ranges)) < 0) 2579 goto fixup_failed; 2580 } 2581 } 2582 2583 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2584 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2585 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2586 &size_cells) == 0) { 2587 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2588 size_cells); 2589 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2590 tuples_count = len / tuple_size; 2591 /* Unexpected settings are not supported */ 2592 if (tuples_count != 1) 2593 goto fixup_failed; 2594 2595 base = fdt_data_get((void *)®[0], par_addr_cells); 2596 base &= ~0xFF000000; 2597 base |= fdt_immr_pa; 2598 reg[0] = cpu_to_fdt32(base); 2599 if (OF_setprop(node, "reg", (void *)®[0], 2600 sizeof(reg)) < 0) 2601 goto fixup_failed; 2602 } 2603 } 2604 /* Fix-up succeeded. May return and continue */ 2605 return; 2606 2607 fixup_failed: 2608 while (1) { 2609 /* 2610 * In case of any error while fixing ranges just hang. 2611 * 1. No message can be displayed yet since console 2612 * is not initialized. 2613 * 2. Going further will cause failure on bus_space_map() 2614 * relying on the wrong ranges or data abort when 2615 * accessing PCIe registers. 2616 */ 2617 } 2618 } 2619 2620 struct fdt_fixup_entry fdt_fixup_table[] = { 2621 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2622 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2623 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2624 { NULL, NULL } 2625 }; 2626 2627 #ifndef INTRNG 2628 static int 2629 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2630 int *pol) 2631 { 2632 2633 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2634 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2635 return (ENXIO); 2636 2637 *interrupt = fdt32_to_cpu(intr[0]); 2638 *trig = INTR_TRIGGER_CONFORM; 2639 *pol = INTR_POLARITY_CONFORM; 2640 2641 return (0); 2642 } 2643 2644 fdt_pic_decode_t fdt_pic_table[] = { 2645 #ifdef SOC_MV_ARMADA38X 2646 &gic_decode_fdt, 2647 #endif 2648 &fdt_pic_decode_ic, 2649 NULL 2650 }; 2651 #endif 2652 2653 uint64_t 2654 get_sar_value(void) 2655 { 2656 uint32_t sar_low, sar_high; 2657 2658 #if defined(SOC_MV_ARMADAXP) 2659 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2660 SAMPLE_AT_RESET_HI); 2661 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2662 SAMPLE_AT_RESET_LO); 2663 #elif defined(SOC_MV_ARMADA38X) 2664 sar_high = 0; 2665 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2666 SAMPLE_AT_RESET); 2667 #else 2668 /* 2669 * TODO: Add getting proper values for other SoC configurations 2670 */ 2671 sar_high = 0; 2672 sar_low = 0; 2673 #endif 2674 2675 return (((uint64_t)sar_high << 32) | sar_low); 2676 } 2677