1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of MARVELL nor the names of contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/malloc.h> 42 #include <sys/kdb.h> 43 #include <sys/reboot.h> 44 45 #include <dev/fdt/fdt_common.h> 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <machine/bus.h> 50 #include <machine/fdt.h> 51 #include <machine/vmparam.h> 52 #include <machine/intr.h> 53 54 #include <arm/mv/mvreg.h> 55 #include <arm/mv/mvvar.h> 56 #include <arm/mv/mvwin.h> 57 58 59 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 60 61 #define IDMA_DEBUG 62 #undef IDMA_DEBUG 63 64 #define MAX_CPU_WIN 5 65 66 #ifdef DEBUG 67 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 68 printf(fmt,##args); } while (0) 69 #else 70 #define debugf(fmt, args...) 71 #endif 72 73 #ifdef DEBUG 74 #define MV_DUMP_WIN 1 75 #else 76 #define MV_DUMP_WIN 0 77 #endif 78 79 struct soc_node_spec; 80 81 static enum soc_family soc_family; 82 83 static int mv_win_cesa_attr(int wng_sel); 84 static int mv_win_cesa_attr_armv5(int eng_sel); 85 static int mv_win_cesa_attr_armada38x(int eng_sel); 86 static int mv_win_cesa_attr_armadaxp(int eng_sel); 87 88 uint32_t read_cpu_ctrl_armv5(uint32_t reg); 89 uint32_t read_cpu_ctrl_armv7(uint32_t reg); 90 91 void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val); 92 void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val); 93 94 static int win_eth_can_remap(int i); 95 96 static int decode_win_cesa_valid(void); 97 static int decode_win_cpu_valid(void); 98 static int decode_win_usb_valid(void); 99 static int decode_win_usb3_valid(void); 100 static int decode_win_eth_valid(void); 101 static int decode_win_pcie_valid(void); 102 static int decode_win_sata_valid(void); 103 static int decode_win_sdhci_valid(void); 104 105 static int decode_win_idma_valid(void); 106 static int decode_win_xor_valid(void); 107 108 static void decode_win_cpu_setup(void); 109 static int decode_win_sdram_fixup(void); 110 static void decode_win_cesa_setup(u_long); 111 static void decode_win_a38x_cesa_setup(u_long); 112 static void decode_win_usb_setup(u_long); 113 static void decode_win_usb3_setup(u_long); 114 static void decode_win_eth_setup(u_long); 115 static void decode_win_neta_setup(u_long); 116 static void decode_win_sata_setup(u_long); 117 static void decode_win_ahci_setup(u_long); 118 static void decode_win_sdhci_setup(u_long); 119 120 static void decode_win_idma_setup(u_long); 121 static void decode_win_xor_setup(u_long); 122 123 static void decode_win_cesa_dump(u_long); 124 static void decode_win_a38x_cesa_dump(u_long); 125 static void decode_win_usb_dump(u_long); 126 static void decode_win_usb3_dump(u_long); 127 static void decode_win_eth_dump(u_long base); 128 static void decode_win_neta_dump(u_long base); 129 static void decode_win_idma_dump(u_long base); 130 static void decode_win_xor_dump(u_long base); 131 static void decode_win_ahci_dump(u_long base); 132 static void decode_win_sdhci_dump(u_long); 133 static void decode_win_pcie_dump(u_long); 134 135 static uint32_t win_cpu_cr_read(int); 136 static uint32_t win_cpu_armv5_cr_read(int); 137 static uint32_t win_cpu_armv7_cr_read(int); 138 static uint32_t win_cpu_br_read(int); 139 static uint32_t win_cpu_armv5_br_read(int); 140 static uint32_t win_cpu_armv7_br_read(int); 141 static uint32_t win_cpu_remap_l_read(int); 142 static uint32_t win_cpu_armv5_remap_l_read(int); 143 static uint32_t win_cpu_armv7_remap_l_read(int); 144 static uint32_t win_cpu_remap_h_read(int); 145 static uint32_t win_cpu_armv5_remap_h_read(int); 146 static uint32_t win_cpu_armv7_remap_h_read(int); 147 148 static void win_cpu_cr_write(int, uint32_t); 149 static void win_cpu_armv5_cr_write(int, uint32_t); 150 static void win_cpu_armv7_cr_write(int, uint32_t); 151 static void win_cpu_br_write(int, uint32_t); 152 static void win_cpu_armv5_br_write(int, uint32_t); 153 static void win_cpu_armv7_br_write(int, uint32_t); 154 static void win_cpu_remap_l_write(int, uint32_t); 155 static void win_cpu_armv5_remap_l_write(int, uint32_t); 156 static void win_cpu_armv7_remap_l_write(int, uint32_t); 157 static void win_cpu_remap_h_write(int, uint32_t); 158 static void win_cpu_armv5_remap_h_write(int, uint32_t); 159 static void win_cpu_armv7_remap_h_write(int, uint32_t); 160 161 static uint32_t ddr_br_read(int); 162 static uint32_t ddr_sz_read(int); 163 static uint32_t ddr_armv5_br_read(int); 164 static uint32_t ddr_armv5_sz_read(int); 165 static uint32_t ddr_armv7_br_read(int); 166 static uint32_t ddr_armv7_sz_read(int); 167 static void ddr_br_write(int, uint32_t); 168 static void ddr_sz_write(int, uint32_t); 169 static void ddr_armv5_br_write(int, uint32_t); 170 static void ddr_armv5_sz_write(int, uint32_t); 171 static void ddr_armv7_br_write(int, uint32_t); 172 static void ddr_armv7_sz_write(int, uint32_t); 173 174 static int fdt_get_ranges(const char *, void *, int, int *, int *); 175 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 176 int *trig, int *pol); 177 178 static int win_cpu_from_dt(void); 179 static int fdt_win_setup(void); 180 181 static int fdt_win_process_child(phandle_t, struct soc_node_spec *, const char*); 182 183 static uint32_t dev_mask = 0; 184 static int cpu_wins_no = 0; 185 static int eth_port = 0; 186 static int usb_port = 0; 187 static boolean_t platform_io_coherent = false; 188 189 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 190 191 const struct decode_win *cpu_wins = cpu_win_tbl; 192 193 typedef void (*decode_win_setup_t)(u_long); 194 typedef void (*dump_win_t)(u_long); 195 typedef int (*valid_t)(void); 196 197 /* 198 * The power status of device feature is only supported on 199 * Kirkwood and Discovery SoCs. 200 */ 201 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 202 #define SOC_MV_POWER_STAT_SUPPORTED 1 203 #else 204 #define SOC_MV_POWER_STAT_SUPPORTED 0 205 #endif 206 207 struct soc_node_spec { 208 const char *compat; 209 decode_win_setup_t decode_handler; 210 dump_win_t dump_handler; 211 valid_t valid_handler; 212 }; 213 214 static struct soc_node_spec soc_nodes[] = { 215 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump, &decode_win_eth_valid}, 216 { "marvell,armada-370-neta", &decode_win_neta_setup, 217 &decode_win_neta_dump, NULL }, 218 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid}, 219 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid }, 220 { "marvell,armada-380-xhci", &decode_win_usb3_setup, 221 &decode_win_usb3_dump, &decode_win_usb3_valid }, 222 { "marvell,armada-380-ahci", &decode_win_ahci_setup, 223 &decode_win_ahci_dump, NULL }, 224 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, 225 &decode_win_sdhci_dump, &decode_win_sdhci_valid}, 226 { "mrvl,sata", &decode_win_sata_setup, NULL, &decode_win_sata_valid}, 227 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump, &decode_win_xor_valid}, 228 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump, &decode_win_idma_valid}, 229 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump, &decode_win_cesa_valid}, 230 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump, &decode_win_pcie_valid}, 231 { "marvell,armada-38x-crypto", &decode_win_a38x_cesa_setup, 232 &decode_win_a38x_cesa_dump, &decode_win_cesa_valid}, 233 { NULL, NULL, NULL, NULL }, 234 }; 235 236 #define SOC_NODE_PCIE_ENTRY_IDX 11 237 238 typedef uint32_t(*read_cpu_ctrl_t)(uint32_t); 239 typedef void(*write_cpu_ctrl_t)(uint32_t, uint32_t); 240 typedef uint32_t (*win_read_t)(int); 241 typedef void (*win_write_t)(int, uint32_t); 242 typedef int (*win_cesa_attr_t)(int); 243 typedef uint32_t (*get_t)(void); 244 245 struct decode_win_spec { 246 read_cpu_ctrl_t read_cpu_ctrl; 247 write_cpu_ctrl_t write_cpu_ctrl; 248 win_read_t cr_read; 249 win_read_t br_read; 250 win_read_t remap_l_read; 251 win_read_t remap_h_read; 252 win_write_t cr_write; 253 win_write_t br_write; 254 win_write_t remap_l_write; 255 win_write_t remap_h_write; 256 uint32_t mv_win_cpu_max; 257 win_cesa_attr_t win_cesa_attr; 258 int win_cesa_target; 259 win_read_t ddr_br_read; 260 win_read_t ddr_sz_read; 261 win_write_t ddr_br_write; 262 win_write_t ddr_sz_write; 263 #if __ARM_ARCH >= 6 264 get_t get_tclk; 265 get_t get_cpu_freq; 266 #endif 267 }; 268 269 struct decode_win_spec *soc_decode_win_spec; 270 271 static struct decode_win_spec decode_win_specs[] = 272 { 273 { 274 &read_cpu_ctrl_armv7, 275 &write_cpu_ctrl_armv7, 276 &win_cpu_armv7_cr_read, 277 &win_cpu_armv7_br_read, 278 &win_cpu_armv7_remap_l_read, 279 &win_cpu_armv7_remap_h_read, 280 &win_cpu_armv7_cr_write, 281 &win_cpu_armv7_br_write, 282 &win_cpu_armv7_remap_l_write, 283 &win_cpu_armv7_remap_h_write, 284 MV_WIN_CPU_MAX_ARMV7, 285 &mv_win_cesa_attr_armada38x, 286 MV_WIN_CESA_TARGET_ARMADA38X, 287 &ddr_armv7_br_read, 288 &ddr_armv7_sz_read, 289 &ddr_armv7_br_write, 290 &ddr_armv7_sz_write, 291 #if __ARM_ARCH >= 6 292 &get_tclk_armada38x, 293 &get_cpu_freq_armada38x, 294 #endif 295 }, 296 { 297 &read_cpu_ctrl_armv7, 298 &write_cpu_ctrl_armv7, 299 &win_cpu_armv7_cr_read, 300 &win_cpu_armv7_br_read, 301 &win_cpu_armv7_remap_l_read, 302 &win_cpu_armv7_remap_h_read, 303 &win_cpu_armv7_cr_write, 304 &win_cpu_armv7_br_write, 305 &win_cpu_armv7_remap_l_write, 306 &win_cpu_armv7_remap_h_write, 307 MV_WIN_CPU_MAX_ARMV7, 308 &mv_win_cesa_attr_armadaxp, 309 MV_WIN_CESA_TARGET_ARMADAXP, 310 &ddr_armv7_br_read, 311 &ddr_armv7_sz_read, 312 &ddr_armv7_br_write, 313 &ddr_armv7_sz_write, 314 #if __ARM_ARCH >= 6 315 &get_tclk_armadaxp, 316 &get_cpu_freq_armadaxp, 317 #endif 318 }, 319 { 320 &read_cpu_ctrl_armv5, 321 &write_cpu_ctrl_armv5, 322 &win_cpu_armv5_cr_read, 323 &win_cpu_armv5_br_read, 324 &win_cpu_armv5_remap_l_read, 325 &win_cpu_armv5_remap_h_read, 326 &win_cpu_armv5_cr_write, 327 &win_cpu_armv5_br_write, 328 &win_cpu_armv5_remap_l_write, 329 &win_cpu_armv5_remap_h_write, 330 MV_WIN_CPU_MAX, 331 &mv_win_cesa_attr_armv5, 332 MV_WIN_CESA_TARGET, 333 &ddr_armv5_br_read, 334 &ddr_armv5_sz_read, 335 &ddr_armv5_br_write, 336 &ddr_armv5_sz_write, 337 #if __ARM_ARCH >= 6 338 NULL, 339 NULL, 340 #endif 341 }, 342 }; 343 344 struct fdt_pm_mask_entry { 345 char *compat; 346 uint32_t mask; 347 }; 348 349 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 350 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 351 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 352 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 353 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 354 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 355 { "mrvl,xor", CPU_PM_CTRL_XOR }, 356 { "mrvl,sata", CPU_PM_CTRL_SATA }, 357 358 { NULL, 0 } 359 }; 360 361 static __inline int 362 pm_is_disabled(uint32_t mask) 363 { 364 #if SOC_MV_POWER_STAT_SUPPORTED 365 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 366 #else 367 return (0); 368 #endif 369 } 370 371 /* 372 * Disable device using power management register. 373 * 1 - Device Power On 374 * 0 - Device Power Off 375 * Mask can be set in loader. 376 * EXAMPLE: 377 * loader> set hw.pm-disable-mask=0x2 378 * 379 * Common mask: 380 * |-------------------------------| 381 * | Device | Kirkwood | Discovery | 382 * |-------------------------------| 383 * | USB0 | 0x00008 | 0x020000 | 384 * |-------------------------------| 385 * | USB1 | - | 0x040000 | 386 * |-------------------------------| 387 * | USB2 | - | 0x080000 | 388 * |-------------------------------| 389 * | GE0 | 0x00001 | 0x000002 | 390 * |-------------------------------| 391 * | GE1 | - | 0x000004 | 392 * |-------------------------------| 393 * | IDMA | - | 0x100000 | 394 * |-------------------------------| 395 * | XOR | 0x10000 | 0x200000 | 396 * |-------------------------------| 397 * | CESA | 0x20000 | 0x400000 | 398 * |-------------------------------| 399 * | SATA | 0x04000 | 0x004000 | 400 * --------------------------------| 401 * This feature can be used only on Kirkwood and Discovery 402 * machines. 403 */ 404 405 static int mv_win_cesa_attr(int eng_sel) 406 { 407 408 if (soc_decode_win_spec->win_cesa_attr != NULL) 409 return (soc_decode_win_spec->win_cesa_attr(eng_sel)); 410 411 return (-1); 412 } 413 414 static int mv_win_cesa_attr_armv5(int eng_sel) 415 { 416 417 return MV_WIN_CESA_ATTR(eng_sel); 418 } 419 420 static int mv_win_cesa_attr_armada38x(int eng_sel) 421 { 422 423 return MV_WIN_CESA_ATTR_ARMADA38X(eng_sel); 424 } 425 426 static int mv_win_cesa_attr_armadaxp(int eng_sel) 427 { 428 429 return MV_WIN_CESA_ATTR_ARMADAXP(eng_sel); 430 } 431 432 enum soc_family 433 mv_check_soc_family() 434 { 435 uint32_t dev, rev; 436 437 soc_id(&dev, &rev); 438 switch (dev) { 439 case MV_DEV_MV78230: 440 case MV_DEV_MV78260: 441 case MV_DEV_MV78460: 442 soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_XP]; 443 soc_family = MV_SOC_ARMADA_XP; 444 return (MV_SOC_ARMADA_XP); 445 case MV_DEV_88F6828: 446 case MV_DEV_88F6820: 447 case MV_DEV_88F6810: 448 soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_38X]; 449 soc_family = MV_SOC_ARMADA_38X; 450 return (MV_SOC_ARMADA_38X); 451 case MV_DEV_88F5181: 452 case MV_DEV_88F5182: 453 case MV_DEV_88F5281: 454 case MV_DEV_88F6281: 455 case MV_DEV_88RC8180: 456 case MV_DEV_88RC9480: 457 case MV_DEV_88RC9580: 458 case MV_DEV_88F6781: 459 case MV_DEV_88F6282: 460 case MV_DEV_MV78100_Z0: 461 case MV_DEV_MV78100: 462 case MV_DEV_MV78160: 463 soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMV5]; 464 soc_family = MV_SOC_ARMV5; 465 return (MV_SOC_ARMV5); 466 default: 467 soc_family = MV_SOC_UNSUPPORTED; 468 return (MV_SOC_UNSUPPORTED); 469 } 470 } 471 472 static __inline void 473 pm_disable_device(int mask) 474 { 475 #ifdef DIAGNOSTIC 476 uint32_t reg; 477 478 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 479 printf("Power Management Register: 0%x\n", reg); 480 481 reg &= ~mask; 482 soc_power_ctrl_set(reg); 483 printf("Device %x is disabled\n", mask); 484 485 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 486 printf("Power Management Register: 0%x\n", reg); 487 #endif 488 } 489 490 int 491 mv_fdt_is_type(phandle_t node, const char *typestr) 492 { 493 #define FDT_TYPE_LEN 64 494 char type[FDT_TYPE_LEN]; 495 496 if (OF_getproplen(node, "device_type") <= 0) 497 return (0); 498 499 if (OF_getprop(node, "device_type", type, FDT_TYPE_LEN) < 0) 500 return (0); 501 502 if (strncasecmp(type, typestr, FDT_TYPE_LEN) == 0) 503 /* This fits. */ 504 return (1); 505 506 return (0); 507 #undef FDT_TYPE_LEN 508 } 509 510 int 511 mv_fdt_pm(phandle_t node) 512 { 513 uint32_t cpu_pm_ctrl; 514 int i, ena, compat; 515 516 ena = 1; 517 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 518 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 519 if (dev_mask & (1 << i)) 520 continue; 521 522 compat = ofw_bus_node_is_compatible(node, 523 fdt_pm_mask_table[i].compat); 524 #if defined(SOC_MV_KIRKWOOD) 525 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 526 dev_mask |= (1 << i); 527 ena = 0; 528 break; 529 } else if (compat) { 530 dev_mask |= (1 << i); 531 break; 532 } 533 #else 534 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 535 dev_mask |= (1 << i); 536 ena = 0; 537 break; 538 } else if (compat) { 539 dev_mask |= (1 << i); 540 break; 541 } 542 #endif 543 } 544 545 return (ena); 546 } 547 548 uint32_t 549 read_cpu_ctrl(uint32_t reg) 550 { 551 552 if (soc_decode_win_spec->read_cpu_ctrl != NULL) 553 return (soc_decode_win_spec->read_cpu_ctrl(reg)); 554 return (-1); 555 } 556 557 uint32_t 558 read_cpu_ctrl_armv5(uint32_t reg) 559 { 560 561 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 562 } 563 564 uint32_t 565 read_cpu_ctrl_armv7(uint32_t reg) 566 { 567 568 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg)); 569 } 570 571 void 572 write_cpu_ctrl(uint32_t reg, uint32_t val) 573 { 574 575 if (soc_decode_win_spec->write_cpu_ctrl != NULL) 576 soc_decode_win_spec->write_cpu_ctrl(reg, val); 577 } 578 579 void 580 write_cpu_ctrl_armv5(uint32_t reg, uint32_t val) 581 { 582 583 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 584 } 585 586 void 587 write_cpu_ctrl_armv7(uint32_t reg, uint32_t val) 588 { 589 590 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg, val); 591 } 592 593 uint32_t 594 read_cpu_mp_clocks(uint32_t reg) 595 { 596 597 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 598 } 599 600 void 601 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 602 { 603 604 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 605 } 606 607 uint32_t 608 read_cpu_misc(uint32_t reg) 609 { 610 611 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 612 } 613 614 void 615 write_cpu_misc(uint32_t reg, uint32_t val) 616 { 617 618 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 619 } 620 621 uint32_t 622 cpu_extra_feat(void) 623 { 624 uint32_t dev, rev; 625 uint32_t ef = 0; 626 627 soc_id(&dev, &rev); 628 629 switch (dev) { 630 case MV_DEV_88F6281: 631 case MV_DEV_88F6282: 632 case MV_DEV_88RC8180: 633 case MV_DEV_MV78100_Z0: 634 case MV_DEV_MV78100: 635 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 636 break; 637 case MV_DEV_88F5182: 638 case MV_DEV_88F5281: 639 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 640 break; 641 default: 642 if (bootverbose) 643 printf("This ARM Core does not support any extra features\n"); 644 } 645 646 return (ef); 647 } 648 649 /* 650 * Get the power status of device. This feature is only supported on 651 * Kirkwood and Discovery SoCs. 652 */ 653 uint32_t 654 soc_power_ctrl_get(uint32_t mask) 655 { 656 657 #if SOC_MV_POWER_STAT_SUPPORTED 658 if (mask != CPU_PM_CTRL_NONE) 659 mask &= read_cpu_ctrl(CPU_PM_CTRL); 660 661 return (mask); 662 #else 663 return (mask); 664 #endif 665 } 666 667 /* 668 * Set the power status of device. This feature is only supported on 669 * Kirkwood and Discovery SoCs. 670 */ 671 void 672 soc_power_ctrl_set(uint32_t mask) 673 { 674 675 #if !defined(SOC_MV_ORION) 676 if (mask != CPU_PM_CTRL_NONE) 677 write_cpu_ctrl(CPU_PM_CTRL, mask); 678 #endif 679 } 680 681 void 682 soc_id(uint32_t *dev, uint32_t *rev) 683 { 684 uint64_t mv_pcie_base = MV_PCIE_BASE; 685 phandle_t node; 686 687 /* 688 * Notice: system identifiers are available in the registers range of 689 * PCIE controller, so using this function is only allowed (and 690 * possible) after the internal registers range has been mapped in via 691 * devmap_bootstrap(). 692 */ 693 *dev = 0; 694 *rev = 0; 695 if ((node = OF_finddevice("/")) == -1) 696 return; 697 if (ofw_bus_node_is_compatible(node, "marvell,armada380")) 698 mv_pcie_base = MV_PCIE_BASE_ARMADA38X; 699 700 *dev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 0) >> 16; 701 *rev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 8) & 0xff; 702 } 703 704 static void 705 soc_identify(void) 706 { 707 uint32_t d, r, size, mode, freq; 708 const char *dev; 709 const char *rev; 710 711 soc_id(&d, &r); 712 713 printf("SOC: "); 714 if (bootverbose) 715 printf("(0x%4x:0x%02x) ", d, r); 716 717 rev = ""; 718 switch (d) { 719 case MV_DEV_88F5181: 720 dev = "Marvell 88F5181"; 721 if (r == 3) 722 rev = "B1"; 723 break; 724 case MV_DEV_88F5182: 725 dev = "Marvell 88F5182"; 726 if (r == 2) 727 rev = "A2"; 728 break; 729 case MV_DEV_88F5281: 730 dev = "Marvell 88F5281"; 731 if (r == 4) 732 rev = "D0"; 733 else if (r == 5) 734 rev = "D1"; 735 else if (r == 6) 736 rev = "D2"; 737 break; 738 case MV_DEV_88F6281: 739 dev = "Marvell 88F6281"; 740 if (r == 0) 741 rev = "Z0"; 742 else if (r == 2) 743 rev = "A0"; 744 else if (r == 3) 745 rev = "A1"; 746 break; 747 case MV_DEV_88RC8180: 748 dev = "Marvell 88RC8180"; 749 break; 750 case MV_DEV_88RC9480: 751 dev = "Marvell 88RC9480"; 752 break; 753 case MV_DEV_88RC9580: 754 dev = "Marvell 88RC9580"; 755 break; 756 case MV_DEV_88F6781: 757 dev = "Marvell 88F6781"; 758 if (r == 2) 759 rev = "Y0"; 760 break; 761 case MV_DEV_88F6282: 762 dev = "Marvell 88F6282"; 763 if (r == 0) 764 rev = "A0"; 765 else if (r == 1) 766 rev = "A1"; 767 break; 768 case MV_DEV_88F6828: 769 dev = "Marvell 88F6828"; 770 break; 771 case MV_DEV_88F6820: 772 dev = "Marvell 88F6820"; 773 break; 774 case MV_DEV_88F6810: 775 dev = "Marvell 88F6810"; 776 break; 777 case MV_DEV_MV78100_Z0: 778 dev = "Marvell MV78100 Z0"; 779 break; 780 case MV_DEV_MV78100: 781 dev = "Marvell MV78100"; 782 break; 783 case MV_DEV_MV78160: 784 dev = "Marvell MV78160"; 785 break; 786 case MV_DEV_MV78260: 787 dev = "Marvell MV78260"; 788 break; 789 case MV_DEV_MV78460: 790 dev = "Marvell MV78460"; 791 break; 792 default: 793 dev = "UNKNOWN"; 794 break; 795 } 796 797 printf("%s", dev); 798 if (*rev != '\0') 799 printf(" rev %s", rev); 800 printf(", TClock %dMHz", get_tclk() / 1000 / 1000); 801 freq = get_cpu_freq(); 802 if (freq != 0) 803 printf(", Frequency %dMHz", freq / 1000 / 1000); 804 printf("\n"); 805 806 mode = read_cpu_ctrl(CPU_CONFIG); 807 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 808 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 809 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 810 811 switch (d) { 812 case MV_DEV_88F6281: 813 case MV_DEV_88F6282: 814 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 815 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 816 mode ? "write-through" : "write-back"); 817 break; 818 case MV_DEV_MV78100: 819 mode = read_cpu_ctrl(CPU_CONTROL); 820 size = mode & CPU_CONTROL_L2_SIZE; 821 mode = mode & CPU_CONTROL_L2_MODE; 822 printf(" %s set-associative %s unified L2 cache\n", 823 size ? "256KB 4-way" : "512KB 8-way", 824 mode ? "write-through" : "write-back"); 825 break; 826 default: 827 break; 828 } 829 } 830 831 static void 832 platform_identify(void *dummy) 833 { 834 835 soc_identify(); 836 837 /* 838 * XXX Board identification e.g. read out from FPGA or similar should 839 * go here 840 */ 841 } 842 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 843 NULL); 844 845 #ifdef KDB 846 static void 847 mv_enter_debugger(void *dummy) 848 { 849 850 if (boothowto & RB_KDB) 851 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 852 } 853 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 854 #endif 855 856 int 857 soc_decode_win(void) 858 { 859 uint32_t dev, rev; 860 int mask, err; 861 862 mask = 0; 863 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 864 865 if (mask != 0) 866 pm_disable_device(mask); 867 868 /* Retrieve data about physical addresses from device tree. */ 869 if ((err = win_cpu_from_dt()) != 0) 870 return (err); 871 872 /* Retrieve our ID: some windows facilities vary between SoC models */ 873 soc_id(&dev, &rev); 874 875 if (soc_family == MV_SOC_ARMADA_XP) 876 if ((err = decode_win_sdram_fixup()) != 0) 877 return(err); 878 879 880 decode_win_cpu_setup(); 881 if (MV_DUMP_WIN) 882 soc_dump_decode_win(); 883 884 eth_port = 0; 885 usb_port = 0; 886 if ((err = fdt_win_setup()) != 0) 887 return (err); 888 889 return (0); 890 } 891 892 /************************************************************************** 893 * Decode windows registers accessors 894 **************************************************************************/ 895 WIN_REG_IDX_RD(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE) 896 WIN_REG_IDX_RD(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE) 897 WIN_REG_IDX_RD(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE) 898 WIN_REG_IDX_RD(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE) 899 WIN_REG_IDX_WR(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE) 900 WIN_REG_IDX_WR(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE) 901 WIN_REG_IDX_WR(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE) 902 WIN_REG_IDX_WR(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE) 903 904 WIN_REG_IDX_RD(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE) 905 WIN_REG_IDX_RD(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE) 906 WIN_REG_IDX_RD(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE) 907 WIN_REG_IDX_RD(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE) 908 WIN_REG_IDX_WR(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE) 909 WIN_REG_IDX_WR(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE) 910 WIN_REG_IDX_WR(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE) 911 WIN_REG_IDX_WR(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE) 912 913 static uint32_t 914 win_cpu_cr_read(int i) 915 { 916 917 if (soc_decode_win_spec->cr_read != NULL) 918 return (soc_decode_win_spec->cr_read(i)); 919 return (-1); 920 } 921 922 static uint32_t 923 win_cpu_br_read(int i) 924 { 925 926 if (soc_decode_win_spec->br_read != NULL) 927 return (soc_decode_win_spec->br_read(i)); 928 return (-1); 929 } 930 931 static uint32_t 932 win_cpu_remap_l_read(int i) 933 { 934 935 if (soc_decode_win_spec->remap_l_read != NULL) 936 return (soc_decode_win_spec->remap_l_read(i)); 937 return (-1); 938 } 939 940 static uint32_t 941 win_cpu_remap_h_read(int i) 942 { 943 944 if (soc_decode_win_spec->remap_h_read != NULL) 945 return soc_decode_win_spec->remap_h_read(i); 946 return (-1); 947 } 948 949 static void 950 win_cpu_cr_write(int i, uint32_t val) 951 { 952 953 if (soc_decode_win_spec->cr_write != NULL) 954 soc_decode_win_spec->cr_write(i, val); 955 } 956 957 static void 958 win_cpu_br_write(int i, uint32_t val) 959 { 960 961 if (soc_decode_win_spec->br_write != NULL) 962 soc_decode_win_spec->br_write(i, val); 963 } 964 965 static void 966 win_cpu_remap_l_write(int i, uint32_t val) 967 { 968 969 if (soc_decode_win_spec->remap_l_write != NULL) 970 soc_decode_win_spec->remap_l_write(i, val); 971 } 972 973 static void 974 win_cpu_remap_h_write(int i, uint32_t val) 975 { 976 977 if (soc_decode_win_spec->remap_h_write != NULL) 978 soc_decode_win_spec->remap_h_write(i, val); 979 } 980 981 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 982 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 983 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 984 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 985 986 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 987 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 988 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 989 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 990 991 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 992 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 993 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 994 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 995 996 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 997 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 998 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 999 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 1000 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 1001 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 1002 1003 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 1004 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 1005 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 1006 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 1007 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 1008 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 1009 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 1010 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 1011 1012 WIN_REG_BASE_RD(win_eth, bare, 0x290) 1013 WIN_REG_BASE_RD(win_eth, epap, 0x294) 1014 WIN_REG_BASE_WR(win_eth, bare, 0x290) 1015 WIN_REG_BASE_WR(win_eth, epap, 0x294) 1016 1017 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 1018 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 1019 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 1020 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 1021 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 1022 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 1023 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 1024 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 1025 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); 1026 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 1027 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 1028 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 1029 1030 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 1031 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 1032 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 1033 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 1034 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 1035 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 1036 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 1037 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 1038 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 1039 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 1040 1041 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 1042 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 1043 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 1044 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 1045 1046 WIN_REG_BASE_IDX_RD(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X); 1047 WIN_REG_BASE_IDX_WR(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X); 1048 WIN_REG_BASE_IDX_RD(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X); 1049 WIN_REG_BASE_IDX_RD(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X); 1050 WIN_REG_BASE_IDX_WR(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X); 1051 WIN_REG_BASE_IDX_WR(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X); 1052 1053 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 1054 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 1055 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 1056 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 1057 1058 #ifndef SOC_MV_DOVE 1059 WIN_REG_IDX_RD(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 1060 WIN_REG_IDX_RD(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 1061 WIN_REG_IDX_WR(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 1062 WIN_REG_IDX_WR(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 1063 1064 WIN_REG_IDX_RD(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7) 1065 WIN_REG_IDX_RD(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7) 1066 WIN_REG_IDX_WR(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7) 1067 WIN_REG_IDX_WR(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7) 1068 1069 static inline uint32_t 1070 ddr_br_read(int i) 1071 { 1072 1073 if (soc_decode_win_spec->ddr_br_read != NULL) 1074 return (soc_decode_win_spec->ddr_br_read(i)); 1075 return (-1); 1076 } 1077 1078 static inline uint32_t 1079 ddr_sz_read(int i) 1080 { 1081 1082 if (soc_decode_win_spec->ddr_sz_read != NULL) 1083 return (soc_decode_win_spec->ddr_sz_read(i)); 1084 return (-1); 1085 } 1086 1087 static inline void 1088 ddr_br_write(int i, uint32_t val) 1089 { 1090 1091 if (soc_decode_win_spec->ddr_br_write != NULL) 1092 soc_decode_win_spec->ddr_br_write(i, val); 1093 } 1094 1095 static inline void 1096 ddr_sz_write(int i, uint32_t val) 1097 { 1098 1099 if (soc_decode_win_spec->ddr_sz_write != NULL) 1100 soc_decode_win_spec->ddr_sz_write(i, val); 1101 } 1102 #else 1103 /* 1104 * On 88F6781 (Dove) SoC DDR Controller is accessed through 1105 * single MBUS <-> AXI bridge. In this case we provide emulated 1106 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 1107 * with common decoding windows setup code. 1108 */ 1109 1110 static inline uint32_t ddr_br_read(int i) 1111 { 1112 uint32_t mmap; 1113 1114 /* Read Memory Address Map Register for CS i */ 1115 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 1116 1117 /* Return CS i base address */ 1118 return (mmap & 0xFF000000); 1119 } 1120 1121 static inline uint32_t ddr_sz_read(int i) 1122 { 1123 uint32_t mmap, size; 1124 1125 /* Read Memory Address Map Register for CS i */ 1126 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 1127 1128 /* Extract size of CS space in 64kB units */ 1129 size = (1 << ((mmap >> 16) & 0x0F)); 1130 1131 /* Return CS size and enable/disable status */ 1132 return (((size - 1) << 16) | (mmap & 0x01)); 1133 } 1134 #endif 1135 1136 /************************************************************************** 1137 * Decode windows helper routines 1138 **************************************************************************/ 1139 void 1140 soc_dump_decode_win(void) 1141 { 1142 int i; 1143 1144 for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { 1145 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 1146 win_cpu_cr_read(i), 1147 win_cpu_br_read(i)); 1148 1149 if (win_cpu_can_remap(i)) 1150 printf(", rl 0x%08x, rh 0x%08x", 1151 win_cpu_remap_l_read(i), 1152 win_cpu_remap_h_read(i)); 1153 1154 printf("\n"); 1155 } 1156 printf("Internal regs base: 0x%08x\n", 1157 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 1158 1159 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1160 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 1161 ddr_br_read(i), ddr_sz_read(i)); 1162 } 1163 1164 /************************************************************************** 1165 * CPU windows routines 1166 **************************************************************************/ 1167 int 1168 win_cpu_can_remap(int i) 1169 { 1170 uint32_t dev, rev; 1171 1172 soc_id(&dev, &rev); 1173 1174 /* Depending on the SoC certain windows have remap capability */ 1175 if ((dev == MV_DEV_88F5182 && i < 2) || 1176 (dev == MV_DEV_88F5281 && i < 4) || 1177 (dev == MV_DEV_88F6281 && i < 4) || 1178 (dev == MV_DEV_88F6282 && i < 4) || 1179 (dev == MV_DEV_88F6828 && i < 20) || 1180 (dev == MV_DEV_88F6820 && i < 20) || 1181 (dev == MV_DEV_88F6810 && i < 20) || 1182 (dev == MV_DEV_88RC8180 && i < 2) || 1183 (dev == MV_DEV_88F6781 && i < 4) || 1184 (dev == MV_DEV_MV78100_Z0 && i < 8) || 1185 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 1186 return (1); 1187 1188 return (0); 1189 } 1190 1191 /* XXX This should check for overlapping remap fields too.. */ 1192 int 1193 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 1194 { 1195 const struct decode_win *tab; 1196 int i; 1197 1198 tab = wintab; 1199 1200 for (i = 0; i < win_no; i++, tab++) { 1201 if (i == win) 1202 /* Skip self */ 1203 continue; 1204 1205 if ((tab->base + tab->size - 1) < (wintab + win)->base) 1206 continue; 1207 1208 else if (((wintab + win)->base + (wintab + win)->size - 1) < 1209 tab->base) 1210 continue; 1211 else 1212 return (i); 1213 } 1214 1215 return (-1); 1216 } 1217 1218 static int 1219 decode_win_cpu_valid(void) 1220 { 1221 int i, j, rv; 1222 uint32_t b, e, s; 1223 1224 if (cpu_wins_no > soc_decode_win_spec->mv_win_cpu_max) { 1225 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 1226 return (0); 1227 } 1228 1229 rv = 1; 1230 for (i = 0; i < cpu_wins_no; i++) { 1231 1232 if (cpu_wins[i].target == 0) { 1233 printf("CPU window#%d: DDR target window is not " 1234 "supposed to be reprogrammed!\n", i); 1235 rv = 0; 1236 } 1237 1238 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 1239 printf("CPU window#%d: not capable of remapping, but " 1240 "val 0x%08x defined\n", i, cpu_wins[i].remap); 1241 rv = 0; 1242 } 1243 1244 s = cpu_wins[i].size; 1245 b = cpu_wins[i].base; 1246 e = b + s - 1; 1247 if (s > (0xFFFFFFFF - b + 1)) { 1248 /* 1249 * XXX this boundary check should account for 64bit 1250 * and remapping.. 1251 */ 1252 printf("CPU window#%d: no space for size 0x%08x at " 1253 "0x%08x\n", i, s, b); 1254 rv = 0; 1255 continue; 1256 } 1257 1258 if (b != rounddown2(b, s)) { 1259 printf("CPU window#%d: address 0x%08x is not aligned " 1260 "to 0x%08x\n", i, b, s); 1261 rv = 0; 1262 continue; 1263 } 1264 1265 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 1266 if (j >= 0) { 1267 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 1268 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1269 cpu_wins[j].base, 1270 cpu_wins[j].base + cpu_wins[j].size - 1); 1271 rv = 0; 1272 } 1273 } 1274 1275 return (rv); 1276 } 1277 1278 int 1279 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 1280 vm_paddr_t remap) 1281 { 1282 uint32_t br, cr; 1283 int win, i; 1284 1285 if (remap == ~0) { 1286 win = soc_decode_win_spec->mv_win_cpu_max - 1; 1287 i = -1; 1288 } else { 1289 win = 0; 1290 i = 1; 1291 } 1292 1293 while ((win >= 0) && (win < soc_decode_win_spec->mv_win_cpu_max)) { 1294 cr = win_cpu_cr_read(win); 1295 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 1296 break; 1297 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 1298 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 1299 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 1300 (target << MV_WIN_CPU_TARGET_SHIFT))) 1301 break; 1302 win += i; 1303 } 1304 if ((win < 0) || (win >= soc_decode_win_spec->mv_win_cpu_max) || 1305 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 1306 return (-1); 1307 1308 br = base & 0xffff0000; 1309 win_cpu_br_write(win, br); 1310 1311 if (win_cpu_can_remap(win)) { 1312 if (remap != ~0) { 1313 win_cpu_remap_l_write(win, remap & 0xffff0000); 1314 win_cpu_remap_h_write(win, 0); 1315 } else { 1316 /* 1317 * Remap function is not used for a given window 1318 * (capable of remapping) - set remap field with the 1319 * same value as base. 1320 */ 1321 win_cpu_remap_l_write(win, base & 0xffff0000); 1322 win_cpu_remap_h_write(win, 0); 1323 } 1324 } 1325 1326 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 1327 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 1328 win_cpu_cr_write(win, cr); 1329 1330 return (0); 1331 } 1332 1333 static void 1334 decode_win_cpu_setup(void) 1335 { 1336 int i; 1337 1338 /* Disable all CPU windows */ 1339 for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { 1340 win_cpu_cr_write(i, 0); 1341 win_cpu_br_write(i, 0); 1342 if (win_cpu_can_remap(i)) { 1343 win_cpu_remap_l_write(i, 0); 1344 win_cpu_remap_h_write(i, 0); 1345 } 1346 } 1347 1348 for (i = 0; i < cpu_wins_no; i++) 1349 if (cpu_wins[i].target > 0) 1350 decode_win_cpu_set(cpu_wins[i].target, 1351 cpu_wins[i].attr, cpu_wins[i].base, 1352 cpu_wins[i].size, cpu_wins[i].remap); 1353 1354 } 1355 1356 static int 1357 decode_win_sdram_fixup(void) 1358 { 1359 struct mem_region mr[FDT_MEM_REGIONS]; 1360 uint8_t window_valid[MV_WIN_DDR_MAX]; 1361 int mr_cnt, err, i, j; 1362 uint32_t valid_win_num = 0; 1363 1364 /* Grab physical memory regions information from device tree. */ 1365 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 1366 if (err != 0) 1367 return (err); 1368 1369 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1370 window_valid[i] = 0; 1371 1372 /* Try to match entries from device tree with settings from u-boot */ 1373 for (i = 0; i < mr_cnt; i++) { 1374 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 1375 if (ddr_is_active(j) && 1376 (ddr_base(j) == mr[i].mr_start) && 1377 (ddr_size(j) == mr[i].mr_size)) { 1378 window_valid[j] = 1; 1379 valid_win_num++; 1380 } 1381 } 1382 } 1383 1384 if (mr_cnt != valid_win_num) 1385 return (EINVAL); 1386 1387 /* Destroy windows without corresponding device tree entry */ 1388 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 1389 if (ddr_is_active(j) && (window_valid[j] != 1)) { 1390 printf("Disabling SDRAM decoding window: %d\n", j); 1391 ddr_disable(j); 1392 } 1393 } 1394 1395 return (0); 1396 } 1397 /* 1398 * Check if we're able to cover all active DDR banks. 1399 */ 1400 static int 1401 decode_win_can_cover_ddr(int max) 1402 { 1403 int i, c; 1404 1405 c = 0; 1406 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1407 if (ddr_is_active(i)) 1408 c++; 1409 1410 if (c > max) { 1411 printf("Unable to cover all active DDR banks: " 1412 "%d, available windows: %d\n", c, max); 1413 return (0); 1414 } 1415 1416 return (1); 1417 } 1418 1419 /************************************************************************** 1420 * DDR windows routines 1421 **************************************************************************/ 1422 int 1423 ddr_is_active(int i) 1424 { 1425 1426 if (ddr_sz_read(i) & 0x1) 1427 return (1); 1428 1429 return (0); 1430 } 1431 1432 void 1433 ddr_disable(int i) 1434 { 1435 1436 ddr_sz_write(i, 0); 1437 ddr_br_write(i, 0); 1438 } 1439 1440 uint32_t 1441 ddr_base(int i) 1442 { 1443 1444 return (ddr_br_read(i) & 0xff000000); 1445 } 1446 1447 uint32_t 1448 ddr_size(int i) 1449 { 1450 1451 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1452 } 1453 1454 uint32_t 1455 ddr_attr(int i) 1456 { 1457 uint32_t dev, rev, attr; 1458 1459 soc_id(&dev, &rev); 1460 if (dev == MV_DEV_88RC8180) 1461 return ((ddr_sz_read(i) & 0xf0) >> 4); 1462 if (dev == MV_DEV_88F6781) 1463 return (0); 1464 1465 attr = (i == 0 ? 0xe : 1466 (i == 1 ? 0xd : 1467 (i == 2 ? 0xb : 1468 (i == 3 ? 0x7 : 0xff)))); 1469 if (platform_io_coherent) 1470 attr |= 0x10; 1471 1472 return (attr); 1473 } 1474 1475 uint32_t 1476 ddr_target(int i) 1477 { 1478 uint32_t dev, rev; 1479 1480 soc_id(&dev, &rev); 1481 if (dev == MV_DEV_88RC8180) { 1482 i = (ddr_sz_read(i) & 0xf0) >> 4; 1483 return (i == 0xe ? 0xc : 1484 (i == 0xd ? 0xd : 1485 (i == 0xb ? 0xe : 1486 (i == 0x7 ? 0xf : 0xc)))); 1487 } 1488 1489 /* 1490 * On SOCs other than 88RC8180 Mbus unit ID for 1491 * DDR SDRAM controller is always 0x0. 1492 */ 1493 return (0); 1494 } 1495 1496 /************************************************************************** 1497 * CESA windows routines 1498 **************************************************************************/ 1499 static int 1500 decode_win_cesa_valid(void) 1501 { 1502 1503 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1504 } 1505 1506 static void 1507 decode_win_cesa_dump(u_long base) 1508 { 1509 int i; 1510 1511 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1512 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1513 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1514 } 1515 1516 /* 1517 * Set CESA decode windows. 1518 */ 1519 static void 1520 decode_win_cesa_setup(u_long base) 1521 { 1522 uint32_t br, cr; 1523 uint64_t size; 1524 int i, j; 1525 1526 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1527 win_cesa_cr_write(base, i, 0); 1528 win_cesa_br_write(base, i, 0); 1529 } 1530 1531 /* Only access to active DRAM banks is required */ 1532 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1533 if (ddr_is_active(i)) { 1534 br = ddr_base(i); 1535 1536 size = ddr_size(i); 1537 /* 1538 * Armada 38x SoC's equipped with 4GB DRAM 1539 * suffer freeze during CESA operation, if 1540 * MBUS window opened at given DRAM CS reaches 1541 * end of the address space. Apply a workaround 1542 * by setting the window size to the closest possible 1543 * value, i.e. divide it by 2. 1544 */ 1545 if ((soc_family == MV_SOC_ARMADA_38X) && 1546 (size + ddr_base(i) == 0x100000000ULL)) 1547 size /= 2; 1548 1549 cr = (((size - 1) & 0xffff0000) | 1550 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1551 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1552 IO_WIN_ENA_MASK); 1553 1554 /* Set the first free CESA window */ 1555 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1556 if (win_cesa_cr_read(base, j) & 0x1) 1557 continue; 1558 1559 win_cesa_br_write(base, j, br); 1560 win_cesa_cr_write(base, j, cr); 1561 break; 1562 } 1563 } 1564 } 1565 } 1566 1567 static void 1568 decode_win_a38x_cesa_setup(u_long base) 1569 { 1570 decode_win_cesa_setup(base); 1571 decode_win_cesa_setup(base + MV_WIN_CESA_OFFSET); 1572 } 1573 1574 static void 1575 decode_win_a38x_cesa_dump(u_long base) 1576 { 1577 decode_win_cesa_dump(base); 1578 decode_win_cesa_dump(base + MV_WIN_CESA_OFFSET); 1579 } 1580 1581 /************************************************************************** 1582 * USB windows routines 1583 **************************************************************************/ 1584 static int 1585 decode_win_usb_valid(void) 1586 { 1587 1588 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1589 } 1590 1591 static void 1592 decode_win_usb_dump(u_long base) 1593 { 1594 int i; 1595 1596 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1597 return; 1598 1599 for (i = 0; i < MV_WIN_USB_MAX; i++) 1600 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1601 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1602 } 1603 1604 /* 1605 * Set USB decode windows. 1606 */ 1607 static void 1608 decode_win_usb_setup(u_long base) 1609 { 1610 uint32_t br, cr; 1611 int i, j; 1612 1613 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1614 return; 1615 1616 usb_port++; 1617 1618 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1619 win_usb_cr_write(base, i, 0); 1620 win_usb_br_write(base, i, 0); 1621 } 1622 1623 /* Only access to active DRAM banks is required */ 1624 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1625 if (ddr_is_active(i)) { 1626 br = ddr_base(i); 1627 /* 1628 * XXX for 6281 we should handle Mbus write 1629 * burst limit field in the ctrl reg 1630 */ 1631 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1632 (ddr_attr(i) << 8) | 1633 (ddr_target(i) << 4) | 1); 1634 1635 /* Set the first free USB window */ 1636 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1637 if (win_usb_cr_read(base, j) & 0x1) 1638 continue; 1639 1640 win_usb_br_write(base, j, br); 1641 win_usb_cr_write(base, j, cr); 1642 break; 1643 } 1644 } 1645 } 1646 } 1647 1648 /************************************************************************** 1649 * USB3 windows routines 1650 **************************************************************************/ 1651 static int 1652 decode_win_usb3_valid(void) 1653 { 1654 1655 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1656 } 1657 1658 static void 1659 decode_win_usb3_dump(u_long base) 1660 { 1661 int i; 1662 1663 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1664 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1665 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1666 } 1667 1668 /* 1669 * Set USB3 decode windows 1670 */ 1671 static void 1672 decode_win_usb3_setup(u_long base) 1673 { 1674 uint32_t br, cr; 1675 int i, j; 1676 1677 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1678 win_usb3_cr_write(base, i, 0); 1679 win_usb3_br_write(base, i, 0); 1680 } 1681 1682 /* Only access to active DRAM banks is required */ 1683 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1684 if (ddr_is_active(i)) { 1685 br = ddr_base(i); 1686 cr = (((ddr_size(i) - 1) & 1687 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1688 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1689 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1690 IO_WIN_ENA_MASK); 1691 1692 /* Set the first free USB3.0 window */ 1693 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1694 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1695 continue; 1696 1697 win_usb3_br_write(base, j, br); 1698 win_usb3_cr_write(base, j, cr); 1699 break; 1700 } 1701 } 1702 } 1703 } 1704 1705 1706 /************************************************************************** 1707 * ETH windows routines 1708 **************************************************************************/ 1709 1710 static int 1711 win_eth_can_remap(int i) 1712 { 1713 1714 /* ETH encode windows 0-3 have remap capability */ 1715 if (i < 4) 1716 return (1); 1717 1718 return (0); 1719 } 1720 1721 static int 1722 eth_bare_read(uint32_t base, int i) 1723 { 1724 uint32_t v; 1725 1726 v = win_eth_bare_read(base); 1727 v &= (1 << i); 1728 1729 return (v >> i); 1730 } 1731 1732 static void 1733 eth_bare_write(uint32_t base, int i, int val) 1734 { 1735 uint32_t v; 1736 1737 v = win_eth_bare_read(base); 1738 v &= ~(1 << i); 1739 v |= (val << i); 1740 win_eth_bare_write(base, v); 1741 } 1742 1743 static void 1744 eth_epap_write(uint32_t base, int i, int val) 1745 { 1746 uint32_t v; 1747 1748 v = win_eth_epap_read(base); 1749 v &= ~(0x3 << (i * 2)); 1750 v |= (val << (i * 2)); 1751 win_eth_epap_write(base, v); 1752 } 1753 1754 static void 1755 decode_win_eth_dump(u_long base) 1756 { 1757 int i; 1758 1759 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1760 return; 1761 1762 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1763 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1764 win_eth_br_read(base, i), 1765 win_eth_sz_read(base, i)); 1766 1767 if (win_eth_can_remap(i)) 1768 printf(", ha 0x%08x", 1769 win_eth_har_read(base, i)); 1770 1771 printf("\n"); 1772 } 1773 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1774 win_eth_bare_read(base), 1775 win_eth_epap_read(base)); 1776 } 1777 1778 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1779 1780 static void 1781 decode_win_eth_setup(u_long base) 1782 { 1783 uint32_t br, sz; 1784 int i, j; 1785 1786 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1787 return; 1788 1789 eth_port++; 1790 1791 /* Disable, clear and revoke protection for all ETH windows */ 1792 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1793 1794 eth_bare_write(base, i, 1); 1795 eth_epap_write(base, i, 0); 1796 win_eth_br_write(base, i, 0); 1797 win_eth_sz_write(base, i, 0); 1798 if (win_eth_can_remap(i)) 1799 win_eth_har_write(base, i, 0); 1800 } 1801 1802 /* Only access to active DRAM banks is required */ 1803 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1804 if (ddr_is_active(i)) { 1805 1806 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1807 sz = ((ddr_size(i) - 1) & 0xffff0000); 1808 1809 /* Set the first free ETH window */ 1810 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1811 if (eth_bare_read(base, j) == 0) 1812 continue; 1813 1814 win_eth_br_write(base, j, br); 1815 win_eth_sz_write(base, j, sz); 1816 1817 /* XXX remapping ETH windows not supported */ 1818 1819 /* Set protection RW */ 1820 eth_epap_write(base, j, 0x3); 1821 1822 /* Enable window */ 1823 eth_bare_write(base, j, 0); 1824 break; 1825 } 1826 } 1827 } 1828 1829 static void 1830 decode_win_neta_dump(u_long base) 1831 { 1832 1833 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); 1834 } 1835 1836 static void 1837 decode_win_neta_setup(u_long base) 1838 { 1839 1840 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); 1841 } 1842 1843 static int 1844 decode_win_eth_valid(void) 1845 { 1846 1847 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1848 } 1849 1850 /************************************************************************** 1851 * PCIE windows routines 1852 **************************************************************************/ 1853 static void 1854 decode_win_pcie_dump(u_long base) 1855 { 1856 int i; 1857 1858 printf("PCIE windows base 0x%08lx\n", base); 1859 for (i = 0; i < MV_WIN_PCIE_MAX; i++) 1860 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", 1861 i, win_pcie_cr_read(base, i), 1862 win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); 1863 1864 for (i = 0; i < MV_PCIE_BAR_MAX; i++) 1865 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", 1866 i, pcie_bar_cr_read(base, i), 1867 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); 1868 } 1869 1870 void 1871 decode_win_pcie_setup(u_long base) 1872 { 1873 uint32_t size = 0, ddrbase = ~0; 1874 uint32_t cr, br; 1875 int i, j; 1876 1877 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1878 pcie_bar_br_write(base, i, 1879 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1880 if (i < 3) 1881 pcie_bar_brh_write(base, i, 0); 1882 if (i > 0) 1883 pcie_bar_cr_write(base, i, 0); 1884 } 1885 1886 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1887 win_pcie_cr_write(base, i, 0); 1888 win_pcie_br_write(base, i, 0); 1889 win_pcie_remap_write(base, i, 0); 1890 } 1891 1892 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1893 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1894 & MV_PCIE_ROOT_CMPLX) == 0) { 1895 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1896 return; 1897 } 1898 1899 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1900 if (ddr_is_active(i)) { 1901 /* Map DDR to BAR 1 */ 1902 cr = (ddr_size(i) - 1) & 0xffff0000; 1903 size += ddr_size(i) & 0xffff0000; 1904 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1905 br = ddr_base(i); 1906 if (br < ddrbase) 1907 ddrbase = br; 1908 1909 /* Use the first available PCIE window */ 1910 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1911 if (win_pcie_cr_read(base, j) != 0) 1912 continue; 1913 1914 win_pcie_br_write(base, j, br); 1915 win_pcie_cr_write(base, j, cr); 1916 break; 1917 } 1918 } 1919 } 1920 1921 /* 1922 * Upper 16 bits in BAR register is interpreted as BAR size 1923 * (in 64 kB units) plus 64kB, so subtract 0x10000 1924 * form value passed to register to get correct value. 1925 */ 1926 size -= 0x10000; 1927 pcie_bar_cr_write(base, 1, size | 1); 1928 pcie_bar_br_write(base, 1, ddrbase | 1929 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1930 pcie_bar_br_write(base, 0, fdt_immr_pa | 1931 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1932 } 1933 1934 static int 1935 decode_win_pcie_valid(void) 1936 { 1937 1938 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1939 } 1940 1941 /************************************************************************** 1942 * IDMA windows routines 1943 **************************************************************************/ 1944 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1945 static int 1946 idma_bare_read(u_long base, int i) 1947 { 1948 uint32_t v; 1949 1950 v = win_idma_bare_read(base); 1951 v &= (1 << i); 1952 1953 return (v >> i); 1954 } 1955 1956 static void 1957 idma_bare_write(u_long base, int i, int val) 1958 { 1959 uint32_t v; 1960 1961 v = win_idma_bare_read(base); 1962 v &= ~(1 << i); 1963 v |= (val << i); 1964 win_idma_bare_write(base, v); 1965 } 1966 1967 /* 1968 * Sets channel protection 'val' for window 'w' on channel 'c' 1969 */ 1970 static void 1971 idma_cap_write(u_long base, int c, int w, int val) 1972 { 1973 uint32_t v; 1974 1975 v = win_idma_cap_read(base, c); 1976 v &= ~(0x3 << (w * 2)); 1977 v |= (val << (w * 2)); 1978 win_idma_cap_write(base, c, v); 1979 } 1980 1981 /* 1982 * Set protection 'val' on all channels for window 'w' 1983 */ 1984 static void 1985 idma_set_prot(u_long base, int w, int val) 1986 { 1987 int c; 1988 1989 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1990 idma_cap_write(base, c, w, val); 1991 } 1992 1993 static int 1994 win_idma_can_remap(int i) 1995 { 1996 1997 /* IDMA decode windows 0-3 have remap capability */ 1998 if (i < 4) 1999 return (1); 2000 2001 return (0); 2002 } 2003 2004 void 2005 decode_win_idma_setup(u_long base) 2006 { 2007 uint32_t br, sz; 2008 int i, j; 2009 2010 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 2011 return; 2012 /* 2013 * Disable and clear all IDMA windows, revoke protection for all channels 2014 */ 2015 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 2016 2017 idma_bare_write(base, i, 1); 2018 win_idma_br_write(base, i, 0); 2019 win_idma_sz_write(base, i, 0); 2020 if (win_idma_can_remap(i) == 1) 2021 win_idma_har_write(base, i, 0); 2022 } 2023 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 2024 win_idma_cap_write(base, i, 0); 2025 2026 /* 2027 * Set up access to all active DRAM banks 2028 */ 2029 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2030 if (ddr_is_active(i)) { 2031 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 2032 sz = ((ddr_size(i) - 1) & 0xffff0000); 2033 2034 /* Place DDR entries in non-remapped windows */ 2035 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 2036 if (win_idma_can_remap(j) != 1 && 2037 idma_bare_read(base, j) == 1) { 2038 2039 /* Configure window */ 2040 win_idma_br_write(base, j, br); 2041 win_idma_sz_write(base, j, sz); 2042 2043 /* Set protection RW on all channels */ 2044 idma_set_prot(base, j, 0x3); 2045 2046 /* Enable window */ 2047 idma_bare_write(base, j, 0); 2048 break; 2049 } 2050 } 2051 2052 /* 2053 * Remaining targets -- from statically defined table 2054 */ 2055 for (i = 0; i < idma_wins_no; i++) 2056 if (idma_wins[i].target > 0) { 2057 br = (idma_wins[i].base & 0xffff0000) | 2058 (idma_wins[i].attr << 8) | idma_wins[i].target; 2059 sz = ((idma_wins[i].size - 1) & 0xffff0000); 2060 2061 /* Set the first free IDMA window */ 2062 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 2063 if (idma_bare_read(base, j) == 0) 2064 continue; 2065 2066 /* Configure window */ 2067 win_idma_br_write(base, j, br); 2068 win_idma_sz_write(base, j, sz); 2069 if (win_idma_can_remap(j) && 2070 idma_wins[j].remap >= 0) 2071 win_idma_har_write(base, j, 2072 idma_wins[j].remap); 2073 2074 /* Set protection RW on all channels */ 2075 idma_set_prot(base, j, 0x3); 2076 2077 /* Enable window */ 2078 idma_bare_write(base, j, 0); 2079 break; 2080 } 2081 } 2082 } 2083 2084 int 2085 decode_win_idma_valid(void) 2086 { 2087 const struct decode_win *wintab; 2088 int c, i, j, rv; 2089 uint32_t b, e, s; 2090 2091 if (idma_wins_no > MV_WIN_IDMA_MAX) { 2092 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 2093 return (0); 2094 } 2095 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 2096 if (ddr_is_active(i)) 2097 c++; 2098 2099 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 2100 printf("IDMA windows: too many entries: %d, available: %d\n", 2101 idma_wins_no, MV_WIN_IDMA_MAX - c); 2102 return (0); 2103 } 2104 2105 wintab = idma_wins; 2106 rv = 1; 2107 for (i = 0; i < idma_wins_no; i++, wintab++) { 2108 2109 if (wintab->target == 0) { 2110 printf("IDMA window#%d: DDR target window is not " 2111 "supposed to be reprogrammed!\n", i); 2112 rv = 0; 2113 } 2114 2115 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 2116 printf("IDMA window#%d: not capable of remapping, but " 2117 "val 0x%08x defined\n", i, wintab->remap); 2118 rv = 0; 2119 } 2120 2121 s = wintab->size; 2122 b = wintab->base; 2123 e = b + s - 1; 2124 if (s > (0xFFFFFFFF - b + 1)) { 2125 /* XXX this boundary check should account for 64bit and 2126 * remapping.. */ 2127 printf("IDMA window#%d: no space for size 0x%08x at " 2128 "0x%08x\n", i, s, b); 2129 rv = 0; 2130 continue; 2131 } 2132 2133 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 2134 if (j >= 0) { 2135 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 2136 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2137 idma_wins[j].base, 2138 idma_wins[j].base + idma_wins[j].size - 1); 2139 rv = 0; 2140 } 2141 } 2142 2143 return (rv); 2144 } 2145 2146 void 2147 decode_win_idma_dump(u_long base) 2148 { 2149 int i; 2150 2151 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 2152 return; 2153 2154 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 2155 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 2156 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 2157 2158 if (win_idma_can_remap(i)) 2159 printf(", ha 0x%08x", win_idma_har_read(base, i)); 2160 2161 printf("\n"); 2162 } 2163 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 2164 printf("IDMA channel#%d: ap 0x%08x\n", i, 2165 win_idma_cap_read(base, i)); 2166 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 2167 } 2168 #else 2169 2170 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 2171 int 2172 decode_win_idma_valid(void) 2173 { 2174 2175 return (1); 2176 } 2177 2178 void 2179 decode_win_idma_setup(u_long base) 2180 { 2181 } 2182 2183 void 2184 decode_win_idma_dump(u_long base) 2185 { 2186 } 2187 #endif 2188 2189 /************************************************************************** 2190 * XOR windows routines 2191 **************************************************************************/ 2192 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 2193 static int 2194 xor_ctrl_read(u_long base, int i, int c, int e) 2195 { 2196 uint32_t v; 2197 v = win_xor_ctrl_read(base, c, e); 2198 v &= (1 << i); 2199 2200 return (v >> i); 2201 } 2202 2203 static void 2204 xor_ctrl_write(u_long base, int i, int c, int e, int val) 2205 { 2206 uint32_t v; 2207 2208 v = win_xor_ctrl_read(base, c, e); 2209 v &= ~(1 << i); 2210 v |= (val << i); 2211 win_xor_ctrl_write(base, c, e, v); 2212 } 2213 2214 /* 2215 * Set channel protection 'val' for window 'w' on channel 'c' 2216 */ 2217 static void 2218 xor_chan_write(u_long base, int c, int e, int w, int val) 2219 { 2220 uint32_t v; 2221 2222 v = win_xor_ctrl_read(base, c, e); 2223 v &= ~(0x3 << (w * 2 + 16)); 2224 v |= (val << (w * 2 + 16)); 2225 win_xor_ctrl_write(base, c, e, v); 2226 } 2227 2228 /* 2229 * Set protection 'val' on all channels for window 'w' on engine 'e' 2230 */ 2231 static void 2232 xor_set_prot(u_long base, int w, int e, int val) 2233 { 2234 int c; 2235 2236 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 2237 xor_chan_write(base, c, e, w, val); 2238 } 2239 2240 static int 2241 win_xor_can_remap(int i) 2242 { 2243 2244 /* XOR decode windows 0-3 have remap capability */ 2245 if (i < 4) 2246 return (1); 2247 2248 return (0); 2249 } 2250 2251 static int 2252 xor_max_eng(void) 2253 { 2254 uint32_t dev, rev; 2255 2256 soc_id(&dev, &rev); 2257 switch (dev) { 2258 case MV_DEV_88F6281: 2259 case MV_DEV_88F6282: 2260 case MV_DEV_MV78130: 2261 case MV_DEV_MV78160: 2262 case MV_DEV_MV78230: 2263 case MV_DEV_MV78260: 2264 case MV_DEV_MV78460: 2265 return (2); 2266 case MV_DEV_MV78100: 2267 case MV_DEV_MV78100_Z0: 2268 return (1); 2269 default: 2270 return (0); 2271 } 2272 } 2273 2274 static void 2275 xor_active_dram(u_long base, int c, int e, int *window) 2276 { 2277 uint32_t br, sz; 2278 int i, m, w; 2279 2280 /* 2281 * Set up access to all active DRAM banks 2282 */ 2283 m = xor_max_eng(); 2284 for (i = 0; i < m; i++) 2285 if (ddr_is_active(i)) { 2286 br = ddr_base(i) | (ddr_attr(i) << 8) | 2287 ddr_target(i); 2288 sz = ((ddr_size(i) - 1) & 0xffff0000); 2289 2290 /* Place DDR entries in non-remapped windows */ 2291 for (w = 0; w < MV_WIN_XOR_MAX; w++) 2292 if (win_xor_can_remap(w) != 1 && 2293 (xor_ctrl_read(base, w, c, e) == 0) && 2294 w > *window) { 2295 /* Configure window */ 2296 win_xor_br_write(base, w, e, br); 2297 win_xor_sz_write(base, w, e, sz); 2298 2299 /* Set protection RW on all channels */ 2300 xor_set_prot(base, w, e, 0x3); 2301 2302 /* Enable window */ 2303 xor_ctrl_write(base, w, c, e, 1); 2304 (*window)++; 2305 break; 2306 } 2307 } 2308 } 2309 2310 void 2311 decode_win_xor_setup(u_long base) 2312 { 2313 uint32_t br, sz; 2314 int i, j, z, e = 1, m, window; 2315 2316 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2317 return; 2318 2319 /* 2320 * Disable and clear all XOR windows, revoke protection for all 2321 * channels 2322 */ 2323 m = xor_max_eng(); 2324 for (j = 0; j < m; j++, e--) { 2325 2326 /* Number of non-remaped windows */ 2327 window = MV_XOR_NON_REMAP - 1; 2328 2329 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2330 win_xor_br_write(base, i, e, 0); 2331 win_xor_sz_write(base, i, e, 0); 2332 } 2333 2334 if (win_xor_can_remap(i) == 1) 2335 win_xor_har_write(base, i, e, 0); 2336 2337 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 2338 win_xor_ctrl_write(base, i, e, 0); 2339 xor_active_dram(base, i, e, &window); 2340 } 2341 2342 /* 2343 * Remaining targets -- from a statically defined table 2344 */ 2345 for (i = 0; i < xor_wins_no; i++) 2346 if (xor_wins[i].target > 0) { 2347 br = (xor_wins[i].base & 0xffff0000) | 2348 (xor_wins[i].attr << 8) | 2349 xor_wins[i].target; 2350 sz = ((xor_wins[i].size - 1) & 0xffff0000); 2351 2352 /* Set the first free XOR window */ 2353 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 2354 if (xor_ctrl_read(base, z, 0, e) && 2355 xor_ctrl_read(base, z, 1, e)) 2356 continue; 2357 2358 /* Configure window */ 2359 win_xor_br_write(base, z, e, br); 2360 win_xor_sz_write(base, z, e, sz); 2361 if (win_xor_can_remap(z) && 2362 xor_wins[z].remap >= 0) 2363 win_xor_har_write(base, z, e, 2364 xor_wins[z].remap); 2365 2366 /* Set protection RW on all channels */ 2367 xor_set_prot(base, z, e, 0x3); 2368 2369 /* Enable window */ 2370 xor_ctrl_write(base, z, 0, e, 1); 2371 xor_ctrl_write(base, z, 1, e, 1); 2372 break; 2373 } 2374 } 2375 } 2376 } 2377 2378 int 2379 decode_win_xor_valid(void) 2380 { 2381 const struct decode_win *wintab; 2382 int c, i, j, rv; 2383 uint32_t b, e, s; 2384 2385 if (xor_wins_no > MV_WIN_XOR_MAX) { 2386 printf("XOR windows: too many entries: %d\n", xor_wins_no); 2387 return (0); 2388 } 2389 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 2390 if (ddr_is_active(i)) 2391 c++; 2392 2393 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 2394 printf("XOR windows: too many entries: %d, available: %d\n", 2395 xor_wins_no, MV_WIN_IDMA_MAX - c); 2396 return (0); 2397 } 2398 2399 wintab = xor_wins; 2400 rv = 1; 2401 for (i = 0; i < xor_wins_no; i++, wintab++) { 2402 2403 if (wintab->target == 0) { 2404 printf("XOR window#%d: DDR target window is not " 2405 "supposed to be reprogrammed!\n", i); 2406 rv = 0; 2407 } 2408 2409 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 2410 printf("XOR window#%d: not capable of remapping, but " 2411 "val 0x%08x defined\n", i, wintab->remap); 2412 rv = 0; 2413 } 2414 2415 s = wintab->size; 2416 b = wintab->base; 2417 e = b + s - 1; 2418 if (s > (0xFFFFFFFF - b + 1)) { 2419 /* 2420 * XXX this boundary check should account for 64bit 2421 * and remapping.. 2422 */ 2423 printf("XOR window#%d: no space for size 0x%08x at " 2424 "0x%08x\n", i, s, b); 2425 rv = 0; 2426 continue; 2427 } 2428 2429 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 2430 if (j >= 0) { 2431 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 2432 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2433 xor_wins[j].base, 2434 xor_wins[j].base + xor_wins[j].size - 1); 2435 rv = 0; 2436 } 2437 } 2438 2439 return (rv); 2440 } 2441 2442 void 2443 decode_win_xor_dump(u_long base) 2444 { 2445 int i, j; 2446 int e = 1; 2447 2448 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2449 return; 2450 2451 for (j = 0; j < xor_max_eng(); j++, e--) { 2452 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2453 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2454 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2455 2456 if (win_xor_can_remap(i)) 2457 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2458 2459 printf("\n"); 2460 } 2461 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2462 printf("XOR control#%d: 0x%08x\n", i, 2463 win_xor_ctrl_read(base, i, e)); 2464 } 2465 } 2466 2467 #else 2468 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2469 static int 2470 decode_win_xor_valid(void) 2471 { 2472 2473 return (1); 2474 } 2475 2476 static void 2477 decode_win_xor_setup(u_long base) 2478 { 2479 } 2480 2481 static void 2482 decode_win_xor_dump(u_long base) 2483 { 2484 } 2485 #endif 2486 2487 /************************************************************************** 2488 * SATA windows routines 2489 **************************************************************************/ 2490 static void 2491 decode_win_sata_setup(u_long base) 2492 { 2493 uint32_t cr, br; 2494 int i, j; 2495 2496 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2497 return; 2498 2499 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2500 win_sata_cr_write(base, i, 0); 2501 win_sata_br_write(base, i, 0); 2502 } 2503 2504 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2505 if (ddr_is_active(i)) { 2506 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2507 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2508 br = ddr_base(i); 2509 2510 /* Use the first available SATA window */ 2511 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2512 if ((win_sata_cr_read(base, j) & 1) != 0) 2513 continue; 2514 2515 win_sata_br_write(base, j, br); 2516 win_sata_cr_write(base, j, cr); 2517 break; 2518 } 2519 } 2520 } 2521 2522 /* 2523 * Configure AHCI decoding windows 2524 */ 2525 static void 2526 decode_win_ahci_setup(u_long base) 2527 { 2528 uint32_t br, cr, sz; 2529 int i, j; 2530 2531 for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) { 2532 win_sata_armada38x_cr_write(base, i, 0); 2533 win_sata_armada38x_br_write(base, i, 0); 2534 win_sata_armada38x_sz_write(base, i, 0); 2535 } 2536 2537 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2538 if (ddr_is_active(i)) { 2539 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2540 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2541 IO_WIN_ENA_MASK; 2542 br = ddr_base(i); 2543 sz = (ddr_size(i) - 1) & 2544 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2545 2546 /* Use first available SATA window */ 2547 for (j = 0; j < MV_WIN_SATA_MAX_ARMADA38X; j++) { 2548 if (win_sata_armada38x_cr_read(base, j) & IO_WIN_ENA_MASK) 2549 continue; 2550 2551 /* BASE is set to DRAM base (0x00000000) */ 2552 win_sata_armada38x_br_write(base, j, br); 2553 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2554 win_sata_armada38x_cr_write(base, j, cr); 2555 /* SIZE is set to 16MB - max value */ 2556 win_sata_armada38x_sz_write(base, j, sz); 2557 break; 2558 } 2559 } 2560 } 2561 } 2562 2563 static void 2564 decode_win_ahci_dump(u_long base) 2565 { 2566 int i; 2567 2568 for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) 2569 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2570 win_sata_armada38x_cr_read(base, i), win_sata_br_read(base, i), 2571 win_sata_armada38x_sz_read(base,i)); 2572 } 2573 2574 static int 2575 decode_win_sata_valid(void) 2576 { 2577 uint32_t dev, rev; 2578 2579 soc_id(&dev, &rev); 2580 if (dev == MV_DEV_88F5281) 2581 return (1); 2582 2583 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2584 } 2585 2586 static void 2587 decode_win_sdhci_setup(u_long base) 2588 { 2589 uint32_t cr, br; 2590 int i, j; 2591 2592 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2593 win_sdhci_cr_write(base, i, 0); 2594 win_sdhci_br_write(base, i, 0); 2595 } 2596 2597 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2598 if (ddr_is_active(i)) { 2599 br = ddr_base(i); 2600 cr = (((ddr_size(i) - 1) & 2601 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2602 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2603 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2604 IO_WIN_ENA_MASK); 2605 2606 /* Use the first available SDHCI window */ 2607 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2608 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2609 continue; 2610 2611 win_sdhci_cr_write(base, j, cr); 2612 win_sdhci_br_write(base, j, br); 2613 break; 2614 } 2615 } 2616 } 2617 2618 static void 2619 decode_win_sdhci_dump(u_long base) 2620 { 2621 int i; 2622 2623 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2624 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2625 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2626 } 2627 2628 static int 2629 decode_win_sdhci_valid(void) 2630 { 2631 2632 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2633 } 2634 2635 /************************************************************************** 2636 * FDT parsing routines. 2637 **************************************************************************/ 2638 2639 static int 2640 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2641 int *tuplesize) 2642 { 2643 phandle_t node; 2644 pcell_t addr_cells, par_addr_cells, size_cells; 2645 int len, tuple_size, tuples_count; 2646 2647 node = OF_finddevice(nodename); 2648 if (node == -1) 2649 return (EINVAL); 2650 2651 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2652 return (ENXIO); 2653 2654 par_addr_cells = fdt_parent_addr_cells(node); 2655 if (par_addr_cells > 2) 2656 return (ERANGE); 2657 2658 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2659 size_cells); 2660 2661 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2662 len = OF_getprop(node, "ranges", buf, size); 2663 2664 /* 2665 * XXX this does not handle the empty 'ranges;' case, which is 2666 * legitimate and should be allowed. 2667 */ 2668 tuples_count = len / tuple_size; 2669 if (tuples_count <= 0) 2670 return (ERANGE); 2671 2672 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2673 return (ERANGE); 2674 2675 *tuples = tuples_count; 2676 *tuplesize = tuple_size; 2677 return (0); 2678 } 2679 2680 static int 2681 win_cpu_from_dt(void) 2682 { 2683 pcell_t ranges[48]; 2684 phandle_t node; 2685 int i, entry_size, err, t, tuple_size, tuples; 2686 u_long sram_base, sram_size; 2687 2688 t = 0; 2689 /* Retrieve 'ranges' property of '/localbus' node. */ 2690 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2691 &tuples, &tuple_size)) == 0) { 2692 /* 2693 * Fill CPU decode windows table. 2694 */ 2695 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2696 2697 entry_size = tuple_size / sizeof(pcell_t); 2698 cpu_wins_no = tuples; 2699 2700 /* Check range */ 2701 if (tuples > nitems(cpu_win_tbl)) { 2702 debugf("too many tuples to fit into cpu_win_tbl\n"); 2703 return (ENOMEM); 2704 } 2705 2706 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2707 cpu_win_tbl[t].target = 1; 2708 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2709 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2710 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2711 cpu_win_tbl[t].remap = ~0; 2712 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2713 "size = 0x%0x remap = 0x%0x\n", 2714 cpu_win_tbl[t].target, 2715 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2716 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2717 } 2718 } 2719 2720 /* 2721 * Retrieve CESA SRAM data. 2722 */ 2723 if ((node = OF_finddevice("sram")) != -1) 2724 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2725 goto moveon; 2726 2727 if ((node = OF_finddevice("/")) == -1) 2728 return (ENXIO); 2729 2730 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2731 /* SRAM block is not always present. */ 2732 return (0); 2733 moveon: 2734 sram_base = sram_size = 0; 2735 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2736 return (EINVAL); 2737 2738 /* Check range */ 2739 if (t >= nitems(cpu_win_tbl)) { 2740 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2741 return (ENOMEM); 2742 } 2743 2744 cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; 2745 if (soc_family == MV_SOC_ARMADA_38X) 2746 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(0); 2747 else 2748 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); 2749 cpu_win_tbl[t].base = sram_base; 2750 cpu_win_tbl[t].size = sram_size; 2751 cpu_win_tbl[t].remap = ~0; 2752 cpu_wins_no++; 2753 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2754 2755 /* Check if there is a second CESA node */ 2756 while ((node = OF_peer(node)) != 0) { 2757 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2758 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2759 return (EINVAL); 2760 break; 2761 } 2762 } 2763 2764 if (node == 0) 2765 return (0); 2766 2767 t++; 2768 if (t >= nitems(cpu_win_tbl)) { 2769 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2770 return (ENOMEM); 2771 } 2772 2773 /* Configure window for CESA1 */ 2774 cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; 2775 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); 2776 cpu_win_tbl[t].base = sram_base; 2777 cpu_win_tbl[t].size = sram_size; 2778 cpu_win_tbl[t].remap = ~0; 2779 cpu_wins_no++; 2780 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2781 2782 return (0); 2783 } 2784 2785 static int 2786 fdt_win_process(phandle_t child) 2787 { 2788 int i, ret; 2789 2790 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2791 /* Setup only for enabled devices */ 2792 if (ofw_bus_node_status_okay(child) == 0) 2793 continue; 2794 2795 if (!ofw_bus_node_is_compatible(child, soc_nodes[i].compat)) 2796 continue; 2797 2798 ret = fdt_win_process_child(child, &soc_nodes[i], "reg"); 2799 if (ret != 0) 2800 return (ret); 2801 } 2802 2803 return (0); 2804 } 2805 2806 static int 2807 fdt_win_process_child(phandle_t child, struct soc_node_spec *soc_node, 2808 const char* mimo_reg_source) 2809 { 2810 int addr_cells, size_cells; 2811 pcell_t reg[8]; 2812 u_long size, base; 2813 2814 if (fdt_addrsize_cells(OF_parent(child), &addr_cells, 2815 &size_cells)) 2816 return (ENXIO); 2817 2818 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) 2819 return (ENOMEM); 2820 if (OF_getprop(child, mimo_reg_source, ®, sizeof(reg)) <= 0) 2821 return (EINVAL); 2822 2823 if (addr_cells <= 2) 2824 base = fdt_data_get(®[0], addr_cells); 2825 else 2826 base = fdt_data_get(®[addr_cells - 2], 2); 2827 size = fdt_data_get(®[addr_cells], size_cells); 2828 2829 if (soc_node->valid_handler != NULL) 2830 if (!soc_node->valid_handler()) 2831 return (EINVAL); 2832 2833 base = (base & 0x000fffff) | fdt_immr_va; 2834 if (soc_node->decode_handler != NULL) 2835 soc_node->decode_handler(base); 2836 else 2837 return (ENXIO); 2838 2839 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2840 soc_node->dump_handler(base); 2841 2842 return (0); 2843 } 2844 2845 static int 2846 fdt_win_setup(void) 2847 { 2848 phandle_t node, child, sb; 2849 phandle_t child_pci; 2850 int err; 2851 2852 sb = 0; 2853 node = OF_finddevice("/"); 2854 if (node == -1) 2855 panic("fdt_win_setup: no root node"); 2856 2857 /* Allow for coherent transactions on the A38x MBUS */ 2858 if (ofw_bus_node_is_compatible(node, "marvell,armada380")) 2859 platform_io_coherent = true; 2860 2861 /* 2862 * Traverse through all children of root and simple-bus nodes. 2863 * For each found device retrieve decode windows data (if applicable). 2864 */ 2865 child = OF_child(node); 2866 while (child != 0) { 2867 /* Lookup for callback and run */ 2868 err = fdt_win_process(child); 2869 if (err != 0) 2870 return (err); 2871 2872 /* Process Marvell Armada-XP/38x PCIe controllers */ 2873 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { 2874 child_pci = OF_child(child); 2875 while (child_pci != 0) { 2876 err = fdt_win_process_child(child_pci, 2877 &soc_nodes[SOC_NODE_PCIE_ENTRY_IDX], 2878 "assigned-addresses"); 2879 if (err != 0) 2880 return (err); 2881 2882 child_pci = OF_peer(child_pci); 2883 } 2884 } 2885 2886 /* 2887 * Once done with root-level children let's move down to 2888 * simple-bus and its children. 2889 */ 2890 child = OF_peer(child); 2891 if ((child == 0) && (node == OF_finddevice("/"))) { 2892 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2893 if (node == 0) 2894 return (ENXIO); 2895 child = OF_child(node); 2896 } 2897 /* 2898 * Next, move one more level down to internal-regs node (if 2899 * it is present) and its children. This node also have 2900 * "simple-bus" compatible. 2901 */ 2902 if ((child == 0) && (node == sb)) { 2903 node = fdt_find_compatible(node, "simple-bus", 0); 2904 if (node == 0) 2905 return (0); 2906 child = OF_child(node); 2907 } 2908 } 2909 2910 return (0); 2911 } 2912 2913 static void 2914 fdt_fixup_busfreq(phandle_t root) 2915 { 2916 phandle_t sb; 2917 pcell_t freq; 2918 2919 freq = cpu_to_fdt32(get_tclk()); 2920 2921 /* 2922 * Fix bus speed in cpu node 2923 */ 2924 if ((sb = OF_finddevice("cpu")) != -1) 2925 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2926 OF_setprop(sb, "bus-frequency", (void *)&freq, 2927 sizeof(freq)); 2928 2929 /* 2930 * This fixup sets the simple-bus bus-frequency property. 2931 */ 2932 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2933 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2934 } 2935 2936 static void 2937 fdt_fixup_ranges(phandle_t root) 2938 { 2939 phandle_t node; 2940 pcell_t par_addr_cells, addr_cells, size_cells; 2941 pcell_t ranges[3], reg[2], *rangesptr; 2942 int len, tuple_size, tuples_count; 2943 uint32_t base; 2944 2945 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2946 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2947 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2948 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2949 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2950 addr_cells + size_cells); 2951 len = OF_getprop(node, "ranges", ranges, 2952 sizeof(ranges)); 2953 tuples_count = len / tuple_size; 2954 /* Unexpected settings are not supported */ 2955 if (tuples_count != 1) 2956 goto fixup_failed; 2957 2958 rangesptr = &ranges[0]; 2959 rangesptr += par_addr_cells; 2960 base = fdt_data_get((void *)rangesptr, addr_cells); 2961 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2962 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2963 sizeof(ranges)) < 0) 2964 goto fixup_failed; 2965 } 2966 } 2967 2968 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2969 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2970 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2971 &size_cells) == 0) { 2972 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2973 size_cells); 2974 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2975 tuples_count = len / tuple_size; 2976 /* Unexpected settings are not supported */ 2977 if (tuples_count != 1) 2978 goto fixup_failed; 2979 2980 base = fdt_data_get((void *)®[0], par_addr_cells); 2981 base &= ~0xFF000000; 2982 base |= fdt_immr_pa; 2983 reg[0] = cpu_to_fdt32(base); 2984 if (OF_setprop(node, "reg", (void *)®[0], 2985 sizeof(reg)) < 0) 2986 goto fixup_failed; 2987 } 2988 } 2989 /* Fix-up succeeded. May return and continue */ 2990 return; 2991 2992 fixup_failed: 2993 while (1) { 2994 /* 2995 * In case of any error while fixing ranges just hang. 2996 * 1. No message can be displayed yet since console 2997 * is not initialized. 2998 * 2. Going further will cause failure on bus_space_map() 2999 * relying on the wrong ranges or data abort when 3000 * accessing PCIe registers. 3001 */ 3002 } 3003 } 3004 3005 struct fdt_fixup_entry fdt_fixup_table[] = { 3006 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 3007 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 3008 { "mrvl,DB-78460", &fdt_fixup_ranges }, 3009 { NULL, NULL } 3010 }; 3011 3012 #if __ARM_ARCH >= 6 3013 uint32_t 3014 get_tclk(void) 3015 { 3016 3017 if (soc_decode_win_spec->get_tclk != NULL) 3018 return soc_decode_win_spec->get_tclk(); 3019 else 3020 return -1; 3021 } 3022 3023 uint32_t 3024 get_cpu_freq(void) 3025 { 3026 3027 if (soc_decode_win_spec->get_cpu_freq != NULL) 3028 return soc_decode_win_spec->get_cpu_freq(); 3029 else 3030 return -1; 3031 } 3032 #endif 3033 3034 #ifndef INTRNG 3035 static int 3036 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 3037 int *pol) 3038 { 3039 3040 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 3041 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 3042 return (ENXIO); 3043 3044 *interrupt = fdt32_to_cpu(intr[0]); 3045 *trig = INTR_TRIGGER_CONFORM; 3046 *pol = INTR_POLARITY_CONFORM; 3047 3048 return (0); 3049 } 3050 3051 fdt_pic_decode_t fdt_pic_table[] = { 3052 &fdt_pic_decode_ic, 3053 NULL 3054 }; 3055 #endif 3056