xref: /freebsd/sys/arm/mv/mv_common.c (revision 1f4bcc459a76b7aa664f3fd557684cd0ba6da352)
1 /*-
2  * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
3  * All rights reserved.
4  *
5  * Developed by Semihalf.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. Neither the name of MARVELL nor the names of contributors
16  *    may be used to endorse or promote products derived from this software
17  *    without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/kdb.h>
41 #include <sys/reboot.h>
42 
43 #include <dev/fdt/fdt_common.h>
44 #include <dev/ofw/openfirm.h>
45 
46 #include <machine/bus.h>
47 #include <machine/fdt.h>
48 #include <machine/vmparam.h>
49 #include <machine/intr.h>
50 
51 #include <arm/mv/mvreg.h>
52 #include <arm/mv/mvvar.h>
53 #include <arm/mv/mvwin.h>
54 
55 
56 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
57 
58 #define IDMA_DEBUG
59 #undef IDMA_DEBUG
60 
61 #define MAX_CPU_WIN	5
62 
63 #ifdef DEBUG
64 #define debugf(fmt, args...) do { printf("%s(): ", __func__);	\
65     printf(fmt,##args); } while (0)
66 #else
67 #define debugf(fmt, args...)
68 #endif
69 
70 #ifdef DEBUG
71 #define MV_DUMP_WIN	1
72 #else
73 #define MV_DUMP_WIN	0
74 #endif
75 
76 static int win_eth_can_remap(int i);
77 
78 #ifndef SOC_MV_FREY
79 static int decode_win_cpu_valid(void);
80 #endif
81 static int decode_win_usb_valid(void);
82 static int decode_win_eth_valid(void);
83 static int decode_win_pcie_valid(void);
84 static int decode_win_sata_valid(void);
85 
86 static int decode_win_idma_valid(void);
87 static int decode_win_xor_valid(void);
88 
89 #ifndef SOC_MV_FREY
90 static void decode_win_cpu_setup(void);
91 #endif
92 #ifdef SOC_MV_ARMADAXP
93 static int decode_win_sdram_fixup(void);
94 #endif
95 static void decode_win_usb_setup(u_long);
96 static void decode_win_eth_setup(u_long);
97 static void decode_win_sata_setup(u_long);
98 
99 static void decode_win_idma_setup(u_long);
100 static void decode_win_xor_setup(u_long);
101 
102 static void decode_win_usb_dump(u_long);
103 static void decode_win_eth_dump(u_long base);
104 static void decode_win_idma_dump(u_long base);
105 static void decode_win_xor_dump(u_long base);
106 
107 static int fdt_get_ranges(const char *, void *, int, int *, int *);
108 #ifdef SOC_MV_ARMADA38X
109 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
110     int *trig, int *pol);
111 #endif
112 
113 static int win_cpu_from_dt(void);
114 static int fdt_win_setup(void);
115 
116 static uint32_t dev_mask = 0;
117 static int cpu_wins_no = 0;
118 static int eth_port = 0;
119 static int usb_port = 0;
120 
121 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
122 
123 const struct decode_win *cpu_wins = cpu_win_tbl;
124 
125 typedef void (*decode_win_setup_t)(u_long);
126 typedef void (*dump_win_t)(u_long);
127 
128 struct soc_node_spec {
129 	const char		*compat;
130 	decode_win_setup_t	decode_handler;
131 	dump_win_t		dump_handler;
132 };
133 
134 static struct soc_node_spec soc_nodes[] = {
135 	{ "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
136 	{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
137 	{ "mrvl,sata", &decode_win_sata_setup, NULL },
138 	{ "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
139 	{ "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
140 	{ "mrvl,pcie", &decode_win_pcie_setup, NULL },
141 	{ NULL, NULL, NULL },
142 };
143 
144 struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
145 	{ "mrvl,ge",		CPU_PM_CTRL_GE(0) },
146 	{ "mrvl,ge",		CPU_PM_CTRL_GE(1) },
147 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(0) },
148 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(1) },
149 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(2) },
150 	{ "mrvl,xor",		CPU_PM_CTRL_XOR },
151 	{ "mrvl,sata",		CPU_PM_CTRL_SATA },
152 
153 	{ NULL, 0 }
154 };
155 
156 static __inline int
157 pm_is_disabled(uint32_t mask)
158 {
159 #if defined(SOC_MV_KIRKWOOD)
160 	return (soc_power_ctrl_get(mask) == mask);
161 #else
162 	return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
163 #endif
164 }
165 
166 /*
167  * Disable device using power management register.
168  * 1 - Device Power On
169  * 0 - Device Power Off
170  * Mask can be set in loader.
171  * EXAMPLE:
172  * loader> set hw.pm-disable-mask=0x2
173  *
174  * Common mask:
175  * |-------------------------------|
176  * | Device | Kirkwood | Discovery |
177  * |-------------------------------|
178  * | USB0   | 0x00008  | 0x020000  |
179  * |-------------------------------|
180  * | USB1   |     -    | 0x040000  |
181  * |-------------------------------|
182  * | USB2   |     -    | 0x080000  |
183  * |-------------------------------|
184  * | GE0    | 0x00001  | 0x000002  |
185  * |-------------------------------|
186  * | GE1    |     -    | 0x000004  |
187  * |-------------------------------|
188  * | IDMA   |     -    | 0x100000  |
189  * |-------------------------------|
190  * | XOR    | 0x10000  | 0x200000  |
191  * |-------------------------------|
192  * | CESA   | 0x20000  | 0x400000  |
193  * |-------------------------------|
194  * | SATA   | 0x04000  | 0x004000  |
195  * --------------------------------|
196  * This feature can be used only on Kirkwood and Discovery
197  * machines.
198  */
199 static __inline void
200 pm_disable_device(int mask)
201 {
202 #ifdef DIAGNOSTIC
203 	uint32_t reg;
204 
205 	reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
206 	printf("Power Management Register: 0%x\n", reg);
207 
208 	reg &= ~mask;
209 	soc_power_ctrl_set(reg);
210 	printf("Device %x is disabled\n", mask);
211 
212 	reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
213 	printf("Power Management Register: 0%x\n", reg);
214 #endif
215 }
216 
217 int
218 fdt_pm(phandle_t node)
219 {
220 	uint32_t cpu_pm_ctrl;
221 	int i, ena, compat;
222 
223 	ena = 1;
224 	cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);
225 	for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) {
226 		if (dev_mask & (1 << i))
227 			continue;
228 
229 		compat = fdt_is_compatible(node, fdt_pm_mask_table[i].compat);
230 #if defined(SOC_MV_KIRKWOOD)
231 		if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
232 			dev_mask |= (1 << i);
233 			ena = 0;
234 			break;
235 		} else if (compat) {
236 			dev_mask |= (1 << i);
237 			break;
238 		}
239 #else
240 		if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
241 			dev_mask |= (1 << i);
242 			ena = 0;
243 			break;
244 		} else if (compat) {
245 			dev_mask |= (1 << i);
246 			break;
247 		}
248 #endif
249 	}
250 
251 	return (ena);
252 }
253 
254 uint32_t
255 read_cpu_ctrl(uint32_t reg)
256 {
257 
258 	return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
259 }
260 
261 void
262 write_cpu_ctrl(uint32_t reg, uint32_t val)
263 {
264 
265 	bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
266 }
267 
268 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
269 uint32_t
270 read_cpu_mp_clocks(uint32_t reg)
271 {
272 
273 	return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
274 }
275 
276 void
277 write_cpu_mp_clocks(uint32_t reg, uint32_t val)
278 {
279 
280 	bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
281 }
282 
283 uint32_t
284 read_cpu_misc(uint32_t reg)
285 {
286 
287 	return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
288 }
289 
290 void
291 write_cpu_misc(uint32_t reg, uint32_t val)
292 {
293 
294 	bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
295 }
296 #endif
297 
298 void
299 cpu_reset(void)
300 {
301 
302 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
303 	write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
304 	write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
305 #else
306 	write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
307 	write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
308 #endif
309 	while (1);
310 }
311 
312 uint32_t
313 cpu_extra_feat(void)
314 {
315 	uint32_t dev, rev;
316 	uint32_t ef = 0;
317 
318 	soc_id(&dev, &rev);
319 
320 	switch (dev) {
321 	case MV_DEV_88F6281:
322 	case MV_DEV_88F6282:
323 	case MV_DEV_88RC8180:
324 	case MV_DEV_MV78100_Z0:
325 	case MV_DEV_MV78100:
326 		__asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
327 		break;
328 	case MV_DEV_88F5182:
329 	case MV_DEV_88F5281:
330 		__asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
331 		break;
332 	default:
333 		if (bootverbose)
334 			printf("This ARM Core does not support any extra features\n");
335 	}
336 
337 	return (ef);
338 }
339 
340 /*
341  * Get the power status of device. This feature is only supported on
342  * Kirkwood and Discovery SoCs.
343  */
344 uint32_t
345 soc_power_ctrl_get(uint32_t mask)
346 {
347 
348 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
349 	if (mask != CPU_PM_CTRL_NONE)
350 		mask &= read_cpu_ctrl(CPU_PM_CTRL);
351 
352 	return (mask);
353 #else
354 	return (mask);
355 #endif
356 }
357 
358 /*
359  * Set the power status of device. This feature is only supported on
360  * Kirkwood and Discovery SoCs.
361  */
362 void
363 soc_power_ctrl_set(uint32_t mask)
364 {
365 
366 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
367 	if (mask != CPU_PM_CTRL_NONE)
368 		write_cpu_ctrl(CPU_PM_CTRL, mask);
369 #endif
370 }
371 
372 void
373 soc_id(uint32_t *dev, uint32_t *rev)
374 {
375 
376 	/*
377 	 * Notice: system identifiers are available in the registers range of
378 	 * PCIE controller, so using this function is only allowed (and
379 	 * possible) after the internal registers range has been mapped in via
380 	 * arm_devmap_bootstrap().
381 	 */
382 	*dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
383 	*rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
384 }
385 
386 static void
387 soc_identify(void)
388 {
389 	uint32_t d, r, size, mode;
390 	const char *dev;
391 	const char *rev;
392 
393 	soc_id(&d, &r);
394 
395 	printf("SOC: ");
396 	if (bootverbose)
397 		printf("(0x%4x:0x%02x) ", d, r);
398 
399 	rev = "";
400 	switch (d) {
401 	case MV_DEV_88F5181:
402 		dev = "Marvell 88F5181";
403 		if (r == 3)
404 			rev = "B1";
405 		break;
406 	case MV_DEV_88F5182:
407 		dev = "Marvell 88F5182";
408 		if (r == 2)
409 			rev = "A2";
410 		break;
411 	case MV_DEV_88F5281:
412 		dev = "Marvell 88F5281";
413 		if (r == 4)
414 			rev = "D0";
415 		else if (r == 5)
416 			rev = "D1";
417 		else if (r == 6)
418 			rev = "D2";
419 		break;
420 	case MV_DEV_88F6281:
421 		dev = "Marvell 88F6281";
422 		if (r == 0)
423 			rev = "Z0";
424 		else if (r == 2)
425 			rev = "A0";
426 		else if (r == 3)
427 			rev = "A1";
428 		break;
429 	case MV_DEV_88RC8180:
430 		dev = "Marvell 88RC8180";
431 		break;
432 	case MV_DEV_88RC9480:
433 		dev = "Marvell 88RC9480";
434 		break;
435 	case MV_DEV_88RC9580:
436 		dev = "Marvell 88RC9580";
437 		break;
438 	case MV_DEV_88F6781:
439 		dev = "Marvell 88F6781";
440 		if (r == 2)
441 			rev = "Y0";
442 		break;
443 	case MV_DEV_88F6282:
444 		dev = "Marvell 88F6282";
445 		if (r == 0)
446 			rev = "A0";
447 		else if (r == 1)
448 			rev = "A1";
449 		break;
450 	case MV_DEV_88F6828:
451 		dev = "Marvell 88F6828";
452 		break;
453 	case MV_DEV_88F6820:
454 		dev = "Marvell 88F6820";
455 		break;
456 	case MV_DEV_88F6810:
457 		dev = "Marvell 88F6810";
458 		break;
459 	case MV_DEV_MV78100_Z0:
460 		dev = "Marvell MV78100 Z0";
461 		break;
462 	case MV_DEV_MV78100:
463 		dev = "Marvell MV78100";
464 		break;
465 	case MV_DEV_MV78160:
466 		dev = "Marvell MV78160";
467 		break;
468 	case MV_DEV_MV78260:
469 		dev = "Marvell MV78260";
470 		break;
471 	case MV_DEV_MV78460:
472 		dev = "Marvell MV78460";
473 		break;
474 	default:
475 		dev = "UNKNOWN";
476 		break;
477 	}
478 
479 	printf("%s", dev);
480 	if (*rev != '\0')
481 		printf(" rev %s", rev);
482 	printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
483 
484 	mode = read_cpu_ctrl(CPU_CONFIG);
485 	printf("  Instruction cache prefetch %s, data cache prefetch %s\n",
486 	    (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
487 	    (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
488 
489 	switch (d) {
490 	case MV_DEV_88F6281:
491 	case MV_DEV_88F6282:
492 		mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
493 		printf("  256KB 4-way set-associative %s unified L2 cache\n",
494 		    mode ? "write-through" : "write-back");
495 		break;
496 	case MV_DEV_MV78100:
497 		mode = read_cpu_ctrl(CPU_CONTROL);
498 		size = mode & CPU_CONTROL_L2_SIZE;
499 		mode = mode & CPU_CONTROL_L2_MODE;
500 		printf("  %s set-associative %s unified L2 cache\n",
501 		    size ? "256KB 4-way" : "512KB 8-way",
502 		    mode ? "write-through" : "write-back");
503 		break;
504 	default:
505 		break;
506 	}
507 }
508 
509 static void
510 platform_identify(void *dummy)
511 {
512 
513 	soc_identify();
514 
515 	/*
516 	 * XXX Board identification e.g. read out from FPGA or similar should
517 	 * go here
518 	 */
519 }
520 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
521     NULL);
522 
523 #ifdef KDB
524 static void
525 mv_enter_debugger(void *dummy)
526 {
527 
528 	if (boothowto & RB_KDB)
529 		kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
530 }
531 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
532 #endif
533 
534 int
535 soc_decode_win(void)
536 {
537 	uint32_t dev, rev;
538 	int mask, err;
539 
540 	mask = 0;
541 	TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);
542 
543 	if (mask != 0)
544 		pm_disable_device(mask);
545 
546 	/* Retrieve data about physical addresses from device tree. */
547 	if ((err = win_cpu_from_dt()) != 0)
548 		return (err);
549 
550 	/* Retrieve our ID: some windows facilities vary between SoC models */
551 	soc_id(&dev, &rev);
552 
553 #ifdef SOC_MV_ARMADAXP
554 	if ((err = decode_win_sdram_fixup()) != 0)
555 		return(err);
556 #endif
557 
558 #ifndef SOC_MV_FREY
559 	if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
560 	    !decode_win_eth_valid() || !decode_win_idma_valid() ||
561 	    !decode_win_pcie_valid() || !decode_win_sata_valid() ||
562 	    !decode_win_xor_valid())
563 		return (EINVAL);
564 
565 	decode_win_cpu_setup();
566 #else
567 	if (!decode_win_usb_valid() ||
568 	    !decode_win_eth_valid() || !decode_win_idma_valid() ||
569 	    !decode_win_pcie_valid() || !decode_win_sata_valid() ||
570 	    !decode_win_xor_valid())
571 		return (EINVAL);
572 #endif
573 	if (MV_DUMP_WIN)
574 		soc_dump_decode_win();
575 
576 	eth_port = 0;
577 	usb_port = 0;
578 	if ((err = fdt_win_setup()) != 0)
579 		return (err);
580 
581 	return (0);
582 }
583 
584 /**************************************************************************
585  * Decode windows registers accessors
586  **************************************************************************/
587 #if !defined(SOC_MV_FREY)
588 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
589 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
590 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
591 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
592 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
593 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
594 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
595 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
596 #endif
597 
598 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
599 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
600 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
601 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
602 
603 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
604 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
605 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
606 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
607 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
608 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
609 
610 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE)
611 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE)
612 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP)
613 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL)
614 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE)
615 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE)
616 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP)
617 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL)
618 
619 WIN_REG_BASE_RD(win_eth, bare, 0x290)
620 WIN_REG_BASE_RD(win_eth, epap, 0x294)
621 WIN_REG_BASE_WR(win_eth, bare, 0x290)
622 WIN_REG_BASE_WR(win_eth, epap, 0x294)
623 
624 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
625 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
626 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
627 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
628 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
629 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
630 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
631 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
632 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
633 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
634 
635 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
636 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
637 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP)
638 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP)
639 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE)
640 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE)
641 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP)
642 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
643 WIN_REG_BASE_RD(win_idma, bare, 0xa80)
644 WIN_REG_BASE_WR(win_idma, bare, 0xa80)
645 
646 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
647 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
648 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
649 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
650 #ifndef SOC_MV_DOVE
651 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
652 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
653 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
654 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
655 #else
656 /*
657  * On 88F6781 (Dove) SoC DDR Controller is accessed through
658  * single MBUS <-> AXI bridge. In this case we provide emulated
659  * ddr_br_read() and ddr_sz_read() functions to keep compatibility
660  * with common decoding windows setup code.
661  */
662 
663 static inline uint32_t ddr_br_read(int i)
664 {
665 	uint32_t mmap;
666 
667 	/* Read Memory Address Map Register for CS i */
668 	mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
669 
670 	/* Return CS i base address */
671 	return (mmap & 0xFF000000);
672 }
673 
674 static inline uint32_t ddr_sz_read(int i)
675 {
676 	uint32_t mmap, size;
677 
678 	/* Read Memory Address Map Register for CS i */
679 	mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
680 
681 	/* Extract size of CS space in 64kB units */
682 	size = (1 << ((mmap >> 16) & 0x0F));
683 
684 	/* Return CS size and enable/disable status */
685 	return (((size - 1) << 16) | (mmap & 0x01));
686 }
687 #endif
688 
689 #if !defined(SOC_MV_FREY)
690 /**************************************************************************
691  * Decode windows helper routines
692  **************************************************************************/
693 void
694 soc_dump_decode_win(void)
695 {
696 	uint32_t dev, rev;
697 	int i;
698 
699 	soc_id(&dev, &rev);
700 
701 	for (i = 0; i < MV_WIN_CPU_MAX; i++) {
702 		printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
703 		    win_cpu_cr_read(i),
704 		    win_cpu_br_read(i));
705 
706 		if (win_cpu_can_remap(i))
707 			printf(", rl 0x%08x, rh 0x%08x",
708 			    win_cpu_remap_l_read(i),
709 			    win_cpu_remap_h_read(i));
710 
711 		printf("\n");
712 	}
713 	printf("Internal regs base: 0x%08x\n",
714 	    bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
715 
716 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
717 		printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
718 		    ddr_br_read(i), ddr_sz_read(i));
719 }
720 
721 /**************************************************************************
722  * CPU windows routines
723  **************************************************************************/
724 int
725 win_cpu_can_remap(int i)
726 {
727 	uint32_t dev, rev;
728 
729 	soc_id(&dev, &rev);
730 
731 	/* Depending on the SoC certain windows have remap capability */
732 	if ((dev == MV_DEV_88F5182 && i < 2) ||
733 	    (dev == MV_DEV_88F5281 && i < 4) ||
734 	    (dev == MV_DEV_88F6281 && i < 4) ||
735 	    (dev == MV_DEV_88F6282 && i < 4) ||
736 	    (dev == MV_DEV_88F6828 && i < 20) ||
737 	    (dev == MV_DEV_88F6820 && i < 20) ||
738 	    (dev == MV_DEV_88F6810 && i < 20) ||
739 	    (dev == MV_DEV_88RC8180 && i < 2) ||
740 	    (dev == MV_DEV_88F6781 && i < 4) ||
741 	    (dev == MV_DEV_MV78100_Z0 && i < 8) ||
742 	    ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
743 		return (1);
744 
745 	return (0);
746 }
747 
748 /* XXX This should check for overlapping remap fields too.. */
749 int
750 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
751 {
752 	const struct decode_win *tab;
753 	int i;
754 
755 	tab = wintab;
756 
757 	for (i = 0; i < win_no; i++, tab++) {
758 		if (i == win)
759 			/* Skip self */
760 			continue;
761 
762 		if ((tab->base + tab->size - 1) < (wintab + win)->base)
763 			continue;
764 
765 		else if (((wintab + win)->base + (wintab + win)->size - 1) <
766 		    tab->base)
767 			continue;
768 		else
769 			return (i);
770 	}
771 
772 	return (-1);
773 }
774 
775 static int
776 decode_win_cpu_valid(void)
777 {
778 	int i, j, rv;
779 	uint32_t b, e, s;
780 
781 	if (cpu_wins_no > MV_WIN_CPU_MAX) {
782 		printf("CPU windows: too many entries: %d\n", cpu_wins_no);
783 		return (0);
784 	}
785 
786 	rv = 1;
787 	for (i = 0; i < cpu_wins_no; i++) {
788 
789 		if (cpu_wins[i].target == 0) {
790 			printf("CPU window#%d: DDR target window is not "
791 			    "supposed to be reprogrammed!\n", i);
792 			rv = 0;
793 		}
794 
795 		if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
796 			printf("CPU window#%d: not capable of remapping, but "
797 			    "val 0x%08x defined\n", i, cpu_wins[i].remap);
798 			rv = 0;
799 		}
800 
801 		s = cpu_wins[i].size;
802 		b = cpu_wins[i].base;
803 		e = b + s - 1;
804 		if (s > (0xFFFFFFFF - b + 1)) {
805 			/*
806 			 * XXX this boundary check should account for 64bit
807 			 * and remapping..
808 			 */
809 			printf("CPU window#%d: no space for size 0x%08x at "
810 			    "0x%08x\n", i, s, b);
811 			rv = 0;
812 			continue;
813 		}
814 
815 		if (b != (b & ~(s - 1))) {
816 			printf("CPU window#%d: address 0x%08x is not aligned "
817 			    "to 0x%08x\n", i, b, s);
818 			rv = 0;
819 			continue;
820 		}
821 
822 		j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
823 		if (j >= 0) {
824 			printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
825 			    "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
826 			    cpu_wins[j].base,
827 			    cpu_wins[j].base + cpu_wins[j].size - 1);
828 			rv = 0;
829 		}
830 	}
831 
832 	return (rv);
833 }
834 
835 int
836 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
837     vm_paddr_t remap)
838 {
839 	uint32_t br, cr;
840 	int win, i;
841 
842 	if (remap == ~0) {
843 		win = MV_WIN_CPU_MAX - 1;
844 		i = -1;
845 	} else {
846 		win = 0;
847 		i = 1;
848 	}
849 
850 	while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
851 		cr = win_cpu_cr_read(win);
852 		if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
853 			break;
854 		if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
855 		    (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
856 		    ((attr << MV_WIN_CPU_ATTR_SHIFT) |
857 		    (target << MV_WIN_CPU_TARGET_SHIFT)))
858 			break;
859 		win += i;
860 	}
861 	if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
862 	    ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
863 		return (-1);
864 
865 	br = base & 0xffff0000;
866 	win_cpu_br_write(win, br);
867 
868 	if (win_cpu_can_remap(win)) {
869 		if (remap != ~0) {
870 			win_cpu_remap_l_write(win, remap & 0xffff0000);
871 			win_cpu_remap_h_write(win, 0);
872 		} else {
873 			/*
874 			 * Remap function is not used for a given window
875 			 * (capable of remapping) - set remap field with the
876 			 * same value as base.
877 			 */
878 			win_cpu_remap_l_write(win, base & 0xffff0000);
879 			win_cpu_remap_h_write(win, 0);
880 		}
881 	}
882 
883 	cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
884 	    (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
885 	win_cpu_cr_write(win, cr);
886 
887 	return (0);
888 }
889 
890 static void
891 decode_win_cpu_setup(void)
892 {
893 	int i;
894 
895 	/* Disable all CPU windows */
896 	for (i = 0; i < MV_WIN_CPU_MAX; i++) {
897 		win_cpu_cr_write(i, 0);
898 		win_cpu_br_write(i, 0);
899 		if (win_cpu_can_remap(i)) {
900 			win_cpu_remap_l_write(i, 0);
901 			win_cpu_remap_h_write(i, 0);
902 		}
903 	}
904 
905 	for (i = 0; i < cpu_wins_no; i++)
906 		if (cpu_wins[i].target > 0)
907 			decode_win_cpu_set(cpu_wins[i].target,
908 			    cpu_wins[i].attr, cpu_wins[i].base,
909 			    cpu_wins[i].size, cpu_wins[i].remap);
910 
911 }
912 #endif
913 
914 #ifdef SOC_MV_ARMADAXP
915 static int
916 decode_win_sdram_fixup(void)
917 {
918 	struct mem_region mr[FDT_MEM_REGIONS];
919 	uint8_t window_valid[MV_WIN_DDR_MAX];
920 	int mr_cnt, memsize, err, i, j;
921 	uint32_t valid_win_num = 0;
922 
923 	/* Grab physical memory regions information from device tree. */
924 	err = fdt_get_mem_regions(mr, &mr_cnt, &memsize);
925 	if (err != 0)
926 		return (err);
927 
928 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
929 		window_valid[i] = 0;
930 
931 	/* Try to match entries from device tree with settings from u-boot */
932 	for (i = 0; i < mr_cnt; i++) {
933 		for (j = 0; j < MV_WIN_DDR_MAX; j++) {
934 			if (ddr_is_active(j) &&
935 			    (ddr_base(j) == mr[i].mr_start) &&
936 			    (ddr_size(j) == mr[i].mr_size)) {
937 				window_valid[j] = 1;
938 				valid_win_num++;
939 			}
940 		}
941 	}
942 
943 	if (mr_cnt != valid_win_num)
944 		return (EINVAL);
945 
946 	/* Destroy windows without corresponding device tree entry */
947 	for (j = 0; j < MV_WIN_DDR_MAX; j++) {
948 		if (ddr_is_active(j) && (window_valid[j] != 1)) {
949 			printf("Disabling SDRAM decoding window: %d\n", j);
950 			ddr_disable(j);
951 		}
952 	}
953 
954 	return (0);
955 }
956 #endif
957 /*
958  * Check if we're able to cover all active DDR banks.
959  */
960 static int
961 decode_win_can_cover_ddr(int max)
962 {
963 	int i, c;
964 
965 	c = 0;
966 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
967 		if (ddr_is_active(i))
968 			c++;
969 
970 	if (c > max) {
971 		printf("Unable to cover all active DDR banks: "
972 		    "%d, available windows: %d\n", c, max);
973 		return (0);
974 	}
975 
976 	return (1);
977 }
978 
979 /**************************************************************************
980  * DDR windows routines
981  **************************************************************************/
982 int
983 ddr_is_active(int i)
984 {
985 
986 	if (ddr_sz_read(i) & 0x1)
987 		return (1);
988 
989 	return (0);
990 }
991 
992 void
993 ddr_disable(int i)
994 {
995 
996 	ddr_sz_write(i, 0);
997 	ddr_br_write(i, 0);
998 }
999 
1000 uint32_t
1001 ddr_base(int i)
1002 {
1003 
1004 	return (ddr_br_read(i) & 0xff000000);
1005 }
1006 
1007 uint32_t
1008 ddr_size(int i)
1009 {
1010 
1011 	return ((ddr_sz_read(i) | 0x00ffffff) + 1);
1012 }
1013 
1014 uint32_t
1015 ddr_attr(int i)
1016 {
1017 	uint32_t dev, rev;
1018 
1019 	soc_id(&dev, &rev);
1020 	if (dev == MV_DEV_88RC8180)
1021 		return ((ddr_sz_read(i) & 0xf0) >> 4);
1022 	if (dev == MV_DEV_88F6781)
1023 		return (0);
1024 
1025 	return (i == 0 ? 0xe :
1026 	    (i == 1 ? 0xd :
1027 	    (i == 2 ? 0xb :
1028 	    (i == 3 ? 0x7 : 0xff))));
1029 }
1030 
1031 uint32_t
1032 ddr_target(int i)
1033 {
1034 	uint32_t dev, rev;
1035 
1036 	soc_id(&dev, &rev);
1037 	if (dev == MV_DEV_88RC8180) {
1038 		i = (ddr_sz_read(i) & 0xf0) >> 4;
1039 		return (i == 0xe ? 0xc :
1040 		    (i == 0xd ? 0xd :
1041 		    (i == 0xb ? 0xe :
1042 		    (i == 0x7 ? 0xf : 0xc))));
1043 	}
1044 
1045 	/*
1046 	 * On SOCs other than 88RC8180 Mbus unit ID for
1047 	 * DDR SDRAM controller is always 0x0.
1048 	 */
1049 	return (0);
1050 }
1051 
1052 /**************************************************************************
1053  * USB windows routines
1054  **************************************************************************/
1055 static int
1056 decode_win_usb_valid(void)
1057 {
1058 
1059 	return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
1060 }
1061 
1062 static void
1063 decode_win_usb_dump(u_long base)
1064 {
1065 	int i;
1066 
1067 	if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
1068 		return;
1069 
1070 	for (i = 0; i < MV_WIN_USB_MAX; i++)
1071 		printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
1072 		    win_usb_cr_read(base, i), win_usb_br_read(base, i));
1073 }
1074 
1075 /*
1076  * Set USB decode windows.
1077  */
1078 static void
1079 decode_win_usb_setup(u_long base)
1080 {
1081 	uint32_t br, cr;
1082 	int i, j;
1083 
1084 
1085 	if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
1086 		return;
1087 
1088 	usb_port++;
1089 
1090 	for (i = 0; i < MV_WIN_USB_MAX; i++) {
1091 		win_usb_cr_write(base, i, 0);
1092 		win_usb_br_write(base, i, 0);
1093 	}
1094 
1095 	/* Only access to active DRAM banks is required */
1096 	for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1097 		if (ddr_is_active(i)) {
1098 			br = ddr_base(i);
1099 			/*
1100 			 * XXX for 6281 we should handle Mbus write
1101 			 * burst limit field in the ctrl reg
1102 			 */
1103 			cr = (((ddr_size(i) - 1) & 0xffff0000) |
1104 			    (ddr_attr(i) << 8) |
1105 			    (ddr_target(i) << 4) | 1);
1106 
1107 			/* Set the first free USB window */
1108 			for (j = 0; j < MV_WIN_USB_MAX; j++) {
1109 				if (win_usb_cr_read(base, j) & 0x1)
1110 					continue;
1111 
1112 				win_usb_br_write(base, j, br);
1113 				win_usb_cr_write(base, j, cr);
1114 				break;
1115 			}
1116 		}
1117 	}
1118 }
1119 
1120 /**************************************************************************
1121  * ETH windows routines
1122  **************************************************************************/
1123 
1124 static int
1125 win_eth_can_remap(int i)
1126 {
1127 
1128 	/* ETH encode windows 0-3 have remap capability */
1129 	if (i < 4)
1130 		return (1);
1131 
1132 	return (0);
1133 }
1134 
1135 static int
1136 eth_bare_read(uint32_t base, int i)
1137 {
1138 	uint32_t v;
1139 
1140 	v = win_eth_bare_read(base);
1141 	v &= (1 << i);
1142 
1143 	return (v >> i);
1144 }
1145 
1146 static void
1147 eth_bare_write(uint32_t base, int i, int val)
1148 {
1149 	uint32_t v;
1150 
1151 	v = win_eth_bare_read(base);
1152 	v &= ~(1 << i);
1153 	v |= (val << i);
1154 	win_eth_bare_write(base, v);
1155 }
1156 
1157 static void
1158 eth_epap_write(uint32_t base, int i, int val)
1159 {
1160 	uint32_t v;
1161 
1162 	v = win_eth_epap_read(base);
1163 	v &= ~(0x3 << (i * 2));
1164 	v |= (val << (i * 2));
1165 	win_eth_epap_write(base, v);
1166 }
1167 
1168 static void
1169 decode_win_eth_dump(u_long base)
1170 {
1171 	int i;
1172 
1173 	if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
1174 		return;
1175 
1176 	for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1177 		printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
1178 		    win_eth_br_read(base, i),
1179 		    win_eth_sz_read(base, i));
1180 
1181 		if (win_eth_can_remap(i))
1182 			printf(", ha 0x%08x",
1183 			    win_eth_har_read(base, i));
1184 
1185 		printf("\n");
1186 	}
1187 	printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
1188 	    win_eth_bare_read(base),
1189 	    win_eth_epap_read(base));
1190 }
1191 
1192 #if defined(SOC_MV_LOKIPLUS)
1193 #define MV_WIN_ETH_DDR_TRGT(n)	0
1194 #else
1195 #define MV_WIN_ETH_DDR_TRGT(n)	ddr_target(n)
1196 #endif
1197 
1198 static void
1199 decode_win_eth_setup(u_long base)
1200 {
1201 	uint32_t br, sz;
1202 	int i, j;
1203 
1204 	if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
1205 		return;
1206 
1207 	eth_port++;
1208 
1209 	/* Disable, clear and revoke protection for all ETH windows */
1210 	for (i = 0; i < MV_WIN_ETH_MAX; i++) {
1211 
1212 		eth_bare_write(base, i, 1);
1213 		eth_epap_write(base, i, 0);
1214 		win_eth_br_write(base, i, 0);
1215 		win_eth_sz_write(base, i, 0);
1216 		if (win_eth_can_remap(i))
1217 			win_eth_har_write(base, i, 0);
1218 	}
1219 
1220 	/* Only access to active DRAM banks is required */
1221 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
1222 		if (ddr_is_active(i)) {
1223 
1224 			br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
1225 			sz = ((ddr_size(i) - 1) & 0xffff0000);
1226 
1227 			/* Set the first free ETH window */
1228 			for (j = 0; j < MV_WIN_ETH_MAX; j++) {
1229 				if (eth_bare_read(base, j) == 0)
1230 					continue;
1231 
1232 				win_eth_br_write(base, j, br);
1233 				win_eth_sz_write(base, j, sz);
1234 
1235 				/* XXX remapping ETH windows not supported */
1236 
1237 				/* Set protection RW */
1238 				eth_epap_write(base, j, 0x3);
1239 
1240 				/* Enable window */
1241 				eth_bare_write(base, j, 0);
1242 				break;
1243 			}
1244 		}
1245 }
1246 
1247 static int
1248 decode_win_eth_valid(void)
1249 {
1250 
1251 	return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
1252 }
1253 
1254 /**************************************************************************
1255  * PCIE windows routines
1256  **************************************************************************/
1257 
1258 void
1259 decode_win_pcie_setup(u_long base)
1260 {
1261 	uint32_t size = 0, ddrbase = ~0;
1262 	uint32_t cr, br;
1263 	int i, j;
1264 
1265 	for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
1266 		pcie_bar_br_write(base, i,
1267 		    MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1268 		if (i < 3)
1269 			pcie_bar_brh_write(base, i, 0);
1270 		if (i > 0)
1271 			pcie_bar_cr_write(base, i, 0);
1272 	}
1273 
1274 	for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
1275 		win_pcie_cr_write(base, i, 0);
1276 		win_pcie_br_write(base, i, 0);
1277 		win_pcie_remap_write(base, i, 0);
1278 	}
1279 
1280 	/* On End-Point only set BAR size to 1MB regardless of DDR size */
1281 	if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
1282 	    & MV_PCIE_ROOT_CMPLX) == 0) {
1283 		pcie_bar_cr_write(base, 1, 0xf0000 | 1);
1284 		return;
1285 	}
1286 
1287 	for (i = 0; i < MV_WIN_DDR_MAX; i++) {
1288 		if (ddr_is_active(i)) {
1289 			/* Map DDR to BAR 1 */
1290 			cr = (ddr_size(i) - 1) & 0xffff0000;
1291 			size += ddr_size(i) & 0xffff0000;
1292 			cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1293 			br = ddr_base(i);
1294 			if (br < ddrbase)
1295 				ddrbase = br;
1296 
1297 			/* Use the first available PCIE window */
1298 			for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
1299 				if (win_pcie_cr_read(base, j) != 0)
1300 					continue;
1301 
1302 				win_pcie_br_write(base, j, br);
1303 				win_pcie_cr_write(base, j, cr);
1304 				break;
1305 			}
1306 		}
1307 	}
1308 
1309 	/*
1310 	 * Upper 16 bits in BAR register is interpreted as BAR size
1311 	 * (in 64 kB units) plus 64kB, so substract 0x10000
1312 	 * form value passed to register to get correct value.
1313 	 */
1314 	size -= 0x10000;
1315 	pcie_bar_cr_write(base, 1, size | 1);
1316 	pcie_bar_br_write(base, 1, ddrbase |
1317 	    MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1318 	pcie_bar_br_write(base, 0, fdt_immr_pa |
1319 	    MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
1320 }
1321 
1322 static int
1323 decode_win_pcie_valid(void)
1324 {
1325 
1326 	return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
1327 }
1328 
1329 /**************************************************************************
1330  * IDMA windows routines
1331  **************************************************************************/
1332 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
1333 static int
1334 idma_bare_read(u_long base, int i)
1335 {
1336 	uint32_t v;
1337 
1338 	v = win_idma_bare_read(base);
1339 	v &= (1 << i);
1340 
1341 	return (v >> i);
1342 }
1343 
1344 static void
1345 idma_bare_write(u_long base, int i, int val)
1346 {
1347 	uint32_t v;
1348 
1349 	v = win_idma_bare_read(base);
1350 	v &= ~(1 << i);
1351 	v |= (val << i);
1352 	win_idma_bare_write(base, v);
1353 }
1354 
1355 /*
1356  * Sets channel protection 'val' for window 'w' on channel 'c'
1357  */
1358 static void
1359 idma_cap_write(u_long base, int c, int w, int val)
1360 {
1361 	uint32_t v;
1362 
1363 	v = win_idma_cap_read(base, c);
1364 	v &= ~(0x3 << (w * 2));
1365 	v |= (val << (w * 2));
1366 	win_idma_cap_write(base, c, v);
1367 }
1368 
1369 /*
1370  * Set protection 'val' on all channels for window 'w'
1371  */
1372 static void
1373 idma_set_prot(u_long base, int w, int val)
1374 {
1375 	int c;
1376 
1377 	for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
1378 		idma_cap_write(base, c, w, val);
1379 }
1380 
1381 static int
1382 win_idma_can_remap(int i)
1383 {
1384 
1385 	/* IDMA decode windows 0-3 have remap capability */
1386 	if (i < 4)
1387 		return (1);
1388 
1389 	return (0);
1390 }
1391 
1392 void
1393 decode_win_idma_setup(u_long base)
1394 {
1395 	uint32_t br, sz;
1396 	int i, j;
1397 
1398 	if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1399 		return;
1400 	/*
1401 	 * Disable and clear all IDMA windows, revoke protection for all channels
1402 	 */
1403 	for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1404 
1405 		idma_bare_write(base, i, 1);
1406 		win_idma_br_write(base, i, 0);
1407 		win_idma_sz_write(base, i, 0);
1408 		if (win_idma_can_remap(i) == 1)
1409 			win_idma_har_write(base, i, 0);
1410 	}
1411 	for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1412 		win_idma_cap_write(base, i, 0);
1413 
1414 	/*
1415 	 * Set up access to all active DRAM banks
1416 	 */
1417 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
1418 		if (ddr_is_active(i)) {
1419 			br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
1420 			sz = ((ddr_size(i) - 1) & 0xffff0000);
1421 
1422 			/* Place DDR entries in non-remapped windows */
1423 			for (j = 0; j < MV_WIN_IDMA_MAX; j++)
1424 				if (win_idma_can_remap(j) != 1 &&
1425 				    idma_bare_read(base, j) == 1) {
1426 
1427 					/* Configure window */
1428 					win_idma_br_write(base, j, br);
1429 					win_idma_sz_write(base, j, sz);
1430 
1431 					/* Set protection RW on all channels */
1432 					idma_set_prot(base, j, 0x3);
1433 
1434 					/* Enable window */
1435 					idma_bare_write(base, j, 0);
1436 					break;
1437 				}
1438 		}
1439 
1440 	/*
1441 	 * Remaining targets -- from statically defined table
1442 	 */
1443 	for (i = 0; i < idma_wins_no; i++)
1444 		if (idma_wins[i].target > 0) {
1445 			br = (idma_wins[i].base & 0xffff0000) |
1446 			    (idma_wins[i].attr << 8) | idma_wins[i].target;
1447 			sz = ((idma_wins[i].size - 1) & 0xffff0000);
1448 
1449 			/* Set the first free IDMA window */
1450 			for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
1451 				if (idma_bare_read(base, j) == 0)
1452 					continue;
1453 
1454 				/* Configure window */
1455 				win_idma_br_write(base, j, br);
1456 				win_idma_sz_write(base, j, sz);
1457 				if (win_idma_can_remap(j) &&
1458 				    idma_wins[j].remap >= 0)
1459 					win_idma_har_write(base, j,
1460 					    idma_wins[j].remap);
1461 
1462 				/* Set protection RW on all channels */
1463 				idma_set_prot(base, j, 0x3);
1464 
1465 				/* Enable window */
1466 				idma_bare_write(base, j, 0);
1467 				break;
1468 			}
1469 		}
1470 }
1471 
1472 int
1473 decode_win_idma_valid(void)
1474 {
1475 	const struct decode_win *wintab;
1476 	int c, i, j, rv;
1477 	uint32_t b, e, s;
1478 
1479 	if (idma_wins_no > MV_WIN_IDMA_MAX) {
1480 		printf("IDMA windows: too many entries: %d\n", idma_wins_no);
1481 		return (0);
1482 	}
1483 	for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1484 		if (ddr_is_active(i))
1485 			c++;
1486 
1487 	if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
1488 		printf("IDMA windows: too many entries: %d, available: %d\n",
1489 		    idma_wins_no, MV_WIN_IDMA_MAX - c);
1490 		return (0);
1491 	}
1492 
1493 	wintab = idma_wins;
1494 	rv = 1;
1495 	for (i = 0; i < idma_wins_no; i++, wintab++) {
1496 
1497 		if (wintab->target == 0) {
1498 			printf("IDMA window#%d: DDR target window is not "
1499 			    "supposed to be reprogrammed!\n", i);
1500 			rv = 0;
1501 		}
1502 
1503 		if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1504 			printf("IDMA window#%d: not capable of remapping, but "
1505 			    "val 0x%08x defined\n", i, wintab->remap);
1506 			rv = 0;
1507 		}
1508 
1509 		s = wintab->size;
1510 		b = wintab->base;
1511 		e = b + s - 1;
1512 		if (s > (0xFFFFFFFF - b + 1)) {
1513 			/* XXX this boundary check should account for 64bit and
1514 			 * remapping.. */
1515 			printf("IDMA window#%d: no space for size 0x%08x at "
1516 			    "0x%08x\n", i, s, b);
1517 			rv = 0;
1518 			continue;
1519 		}
1520 
1521 		j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
1522 		if (j >= 0) {
1523 			printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
1524 			    "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1525 			    idma_wins[j].base,
1526 			    idma_wins[j].base + idma_wins[j].size - 1);
1527 			rv = 0;
1528 		}
1529 	}
1530 
1531 	return (rv);
1532 }
1533 
1534 void
1535 decode_win_idma_dump(u_long base)
1536 {
1537 	int i;
1538 
1539 	if (pm_is_disabled(CPU_PM_CTRL_IDMA))
1540 		return;
1541 
1542 	for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1543 		printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
1544 		    win_idma_br_read(base, i), win_idma_sz_read(base, i));
1545 
1546 		if (win_idma_can_remap(i))
1547 			printf(", ha 0x%08x", win_idma_har_read(base, i));
1548 
1549 		printf("\n");
1550 	}
1551 	for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1552 		printf("IDMA channel#%d: ap 0x%08x\n", i,
1553 		    win_idma_cap_read(base, i));
1554 	printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
1555 }
1556 #else
1557 
1558 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
1559 int
1560 decode_win_idma_valid(void)
1561 {
1562 
1563 	return (1);
1564 }
1565 
1566 void
1567 decode_win_idma_setup(u_long base)
1568 {
1569 }
1570 
1571 void
1572 decode_win_idma_dump(u_long base)
1573 {
1574 }
1575 #endif
1576 
1577 /**************************************************************************
1578  * XOR windows routines
1579  **************************************************************************/
1580 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1581 static int
1582 xor_ctrl_read(u_long base, int i, int c, int e)
1583 {
1584 	uint32_t v;
1585 	v = win_xor_ctrl_read(base, c, e);
1586 	v &= (1 << i);
1587 
1588 	return (v >> i);
1589 }
1590 
1591 static void
1592 xor_ctrl_write(u_long base, int i, int c, int e, int val)
1593 {
1594 	uint32_t v;
1595 
1596 	v = win_xor_ctrl_read(base, c, e);
1597 	v &= ~(1 << i);
1598 	v |= (val << i);
1599 	win_xor_ctrl_write(base, c, e, v);
1600 }
1601 
1602 /*
1603  * Set channel protection 'val' for window 'w' on channel 'c'
1604  */
1605 static void
1606 xor_chan_write(u_long base, int c, int e, int w, int val)
1607 {
1608 	uint32_t v;
1609 
1610 	v = win_xor_ctrl_read(base, c, e);
1611 	v &= ~(0x3 << (w * 2 + 16));
1612 	v |= (val << (w * 2 + 16));
1613 	win_xor_ctrl_write(base, c, e, v);
1614 }
1615 
1616 /*
1617  * Set protection 'val' on all channels for window 'w' on engine 'e'
1618  */
1619 static void
1620 xor_set_prot(u_long base, int w, int e, int val)
1621 {
1622 	int c;
1623 
1624 	for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1625 		xor_chan_write(base, c, e, w, val);
1626 }
1627 
1628 static int
1629 win_xor_can_remap(int i)
1630 {
1631 
1632 	/* XOR decode windows 0-3 have remap capability */
1633 	if (i < 4)
1634 		return (1);
1635 
1636 	return (0);
1637 }
1638 
1639 static int
1640 xor_max_eng(void)
1641 {
1642 	uint32_t dev, rev;
1643 
1644 	soc_id(&dev, &rev);
1645 	switch (dev) {
1646 	case MV_DEV_88F6281:
1647 	case MV_DEV_88F6282:
1648 	case MV_DEV_MV78130:
1649 	case MV_DEV_MV78160:
1650 	case MV_DEV_MV78230:
1651 	case MV_DEV_MV78260:
1652 	case MV_DEV_MV78460:
1653 		return (2);
1654 	case MV_DEV_MV78100:
1655 	case MV_DEV_MV78100_Z0:
1656 		return (1);
1657 	default:
1658 		return (0);
1659 	}
1660 }
1661 
1662 static void
1663 xor_active_dram(u_long base, int c, int e, int *window)
1664 {
1665 	uint32_t br, sz;
1666 	int i, m, w;
1667 
1668 	/*
1669 	 * Set up access to all active DRAM banks
1670 	 */
1671 	m = xor_max_eng();
1672 	for (i = 0; i < m; i++)
1673 		if (ddr_is_active(i)) {
1674 			br = ddr_base(i) | (ddr_attr(i) << 8) |
1675 			    ddr_target(i);
1676 			sz = ((ddr_size(i) - 1) & 0xffff0000);
1677 
1678 			/* Place DDR entries in non-remapped windows */
1679 			for (w = 0; w < MV_WIN_XOR_MAX; w++)
1680 				if (win_xor_can_remap(w) != 1 &&
1681 				    (xor_ctrl_read(base, w, c, e) == 0) &&
1682 				    w > *window) {
1683 					/* Configure window */
1684 					win_xor_br_write(base, w, e, br);
1685 					win_xor_sz_write(base, w, e, sz);
1686 
1687 					/* Set protection RW on all channels */
1688 					xor_set_prot(base, w, e, 0x3);
1689 
1690 					/* Enable window */
1691 					xor_ctrl_write(base, w, c, e, 1);
1692 					(*window)++;
1693 					break;
1694 				}
1695 		}
1696 }
1697 
1698 void
1699 decode_win_xor_setup(u_long base)
1700 {
1701 	uint32_t br, sz;
1702 	int i, j, z, e = 1, m, window;
1703 
1704 	if (pm_is_disabled(CPU_PM_CTRL_XOR))
1705 		return;
1706 
1707 	/*
1708 	 * Disable and clear all XOR windows, revoke protection for all
1709 	 * channels
1710 	 */
1711 	m = xor_max_eng();
1712 	for (j = 0; j < m; j++, e--) {
1713 
1714 		/* Number of non-remaped windows */
1715 		window = MV_XOR_NON_REMAP - 1;
1716 
1717 		for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1718 			win_xor_br_write(base, i, e, 0);
1719 			win_xor_sz_write(base, i, e, 0);
1720 		}
1721 
1722 		if (win_xor_can_remap(i) == 1)
1723 			win_xor_har_write(base, i, e, 0);
1724 
1725 		for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1726 			win_xor_ctrl_write(base, i, e, 0);
1727 			xor_active_dram(base, i, e, &window);
1728 		}
1729 
1730 		/*
1731 		 * Remaining targets -- from a statically defined table
1732 		 */
1733 		for (i = 0; i < xor_wins_no; i++)
1734 			if (xor_wins[i].target > 0) {
1735 				br = (xor_wins[i].base & 0xffff0000) |
1736 				    (xor_wins[i].attr << 8) |
1737 				    xor_wins[i].target;
1738 				sz = ((xor_wins[i].size - 1) & 0xffff0000);
1739 
1740 				/* Set the first free XOR window */
1741 				for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1742 					if (xor_ctrl_read(base, z, 0, e) &&
1743 					    xor_ctrl_read(base, z, 1, e))
1744 						continue;
1745 
1746 					/* Configure window */
1747 					win_xor_br_write(base, z, e, br);
1748 					win_xor_sz_write(base, z, e, sz);
1749 					if (win_xor_can_remap(z) &&
1750 					    xor_wins[z].remap >= 0)
1751 						win_xor_har_write(base, z, e,
1752 						    xor_wins[z].remap);
1753 
1754 					/* Set protection RW on all channels */
1755 					xor_set_prot(base, z, e, 0x3);
1756 
1757 					/* Enable window */
1758 					xor_ctrl_write(base, z, 0, e, 1);
1759 					xor_ctrl_write(base, z, 1, e, 1);
1760 					break;
1761 				}
1762 			}
1763 	}
1764 }
1765 
1766 int
1767 decode_win_xor_valid(void)
1768 {
1769 	const struct decode_win *wintab;
1770 	int c, i, j, rv;
1771 	uint32_t b, e, s;
1772 
1773 	if (xor_wins_no > MV_WIN_XOR_MAX) {
1774 		printf("XOR windows: too many entries: %d\n", xor_wins_no);
1775 		return (0);
1776 	}
1777 	for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1778 		if (ddr_is_active(i))
1779 			c++;
1780 
1781 	if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
1782 		printf("XOR windows: too many entries: %d, available: %d\n",
1783 		    xor_wins_no, MV_WIN_IDMA_MAX - c);
1784 		return (0);
1785 	}
1786 
1787 	wintab = xor_wins;
1788 	rv = 1;
1789 	for (i = 0; i < xor_wins_no; i++, wintab++) {
1790 
1791 		if (wintab->target == 0) {
1792 			printf("XOR window#%d: DDR target window is not "
1793 			    "supposed to be reprogrammed!\n", i);
1794 			rv = 0;
1795 		}
1796 
1797 		if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1798 			printf("XOR window#%d: not capable of remapping, but "
1799 			    "val 0x%08x defined\n", i, wintab->remap);
1800 			rv = 0;
1801 		}
1802 
1803 		s = wintab->size;
1804 		b = wintab->base;
1805 		e = b + s - 1;
1806 		if (s > (0xFFFFFFFF - b + 1)) {
1807 			/*
1808 			 * XXX this boundary check should account for 64bit
1809 			 * and remapping..
1810 			 */
1811 			printf("XOR window#%d: no space for size 0x%08x at "
1812 			    "0x%08x\n", i, s, b);
1813 			rv = 0;
1814 			continue;
1815 		}
1816 
1817 		j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
1818 		if (j >= 0) {
1819 			printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
1820 			    "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1821 			    xor_wins[j].base,
1822 			    xor_wins[j].base + xor_wins[j].size - 1);
1823 			rv = 0;
1824 		}
1825 	}
1826 
1827 	return (rv);
1828 }
1829 
1830 void
1831 decode_win_xor_dump(u_long base)
1832 {
1833 	int i, j;
1834 	int e = 1;
1835 
1836 	if (pm_is_disabled(CPU_PM_CTRL_XOR))
1837 		return;
1838 
1839 	for (j = 0; j < xor_max_eng(); j++, e--) {
1840 		for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1841 			printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
1842 			    win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
1843 
1844 			if (win_xor_can_remap(i))
1845 				printf(", ha 0x%08x", win_xor_har_read(base, i, e));
1846 
1847 			printf("\n");
1848 		}
1849 		for (i = 0; i < MV_XOR_CHAN_MAX; i++)
1850 			printf("XOR control#%d: 0x%08x\n", i,
1851 			    win_xor_ctrl_read(base, i, e));
1852 	}
1853 }
1854 
1855 #else
1856 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
1857 static int
1858 decode_win_xor_valid(void)
1859 {
1860 
1861 	return (1);
1862 }
1863 
1864 static void
1865 decode_win_xor_setup(u_long base)
1866 {
1867 }
1868 
1869 static void
1870 decode_win_xor_dump(u_long base)
1871 {
1872 }
1873 #endif
1874 
1875 /**************************************************************************
1876  * SATA windows routines
1877  **************************************************************************/
1878 static void
1879 decode_win_sata_setup(u_long base)
1880 {
1881 	uint32_t cr, br;
1882 	int i, j;
1883 
1884 	if (pm_is_disabled(CPU_PM_CTRL_SATA))
1885 		return;
1886 
1887 	for (i = 0; i < MV_WIN_SATA_MAX; i++) {
1888 		win_sata_cr_write(base, i, 0);
1889 		win_sata_br_write(base, i, 0);
1890 	}
1891 
1892 	for (i = 0; i < MV_WIN_DDR_MAX; i++)
1893 		if (ddr_is_active(i)) {
1894 			cr = ((ddr_size(i) - 1) & 0xffff0000) |
1895 			    (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1896 			br = ddr_base(i);
1897 
1898 			/* Use the first available SATA window */
1899 			for (j = 0; j < MV_WIN_SATA_MAX; j++) {
1900 				if ((win_sata_cr_read(base, j) & 1) != 0)
1901 					continue;
1902 
1903 				win_sata_br_write(base, j, br);
1904 				win_sata_cr_write(base, j, cr);
1905 				break;
1906 			}
1907 		}
1908 }
1909 
1910 static int
1911 decode_win_sata_valid(void)
1912 {
1913 	uint32_t dev, rev;
1914 
1915 	soc_id(&dev, &rev);
1916 	if (dev == MV_DEV_88F5281)
1917 		return (1);
1918 
1919 	return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
1920 }
1921 
1922 /**************************************************************************
1923  * FDT parsing routines.
1924  **************************************************************************/
1925 
1926 static int
1927 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples,
1928     int *tuplesize)
1929 {
1930 	phandle_t node;
1931 	pcell_t addr_cells, par_addr_cells, size_cells;
1932 	int len, tuple_size, tuples_count;
1933 
1934 	node = OF_finddevice(nodename);
1935 	if (node == -1)
1936 		return (EINVAL);
1937 
1938 	if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
1939 		return (ENXIO);
1940 
1941 	par_addr_cells = fdt_parent_addr_cells(node);
1942 	if (par_addr_cells > 2)
1943 		return (ERANGE);
1944 
1945 	tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
1946 	    size_cells);
1947 
1948 	/* Note the OF_getprop_alloc() cannot be used at this early stage. */
1949 	len = OF_getprop(node, "ranges", buf, size);
1950 
1951 	/*
1952 	 * XXX this does not handle the empty 'ranges;' case, which is
1953 	 * legitimate and should be allowed.
1954 	 */
1955 	tuples_count = len / tuple_size;
1956 	if (tuples_count <= 0)
1957 		return (ERANGE);
1958 
1959 	if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2)
1960 		return (ERANGE);
1961 
1962 	*tuples = tuples_count;
1963 	*tuplesize = tuple_size;
1964 	return (0);
1965 }
1966 
1967 static int
1968 win_cpu_from_dt(void)
1969 {
1970 	pcell_t ranges[48];
1971 	phandle_t node;
1972 	int i, entry_size, err, t, tuple_size, tuples;
1973 	u_long sram_base, sram_size;
1974 
1975 	t = 0;
1976 	/* Retrieve 'ranges' property of '/localbus' node. */
1977 	if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
1978 	    &tuples, &tuple_size)) == 0) {
1979 		/*
1980 		 * Fill CPU decode windows table.
1981 		 */
1982 		bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
1983 
1984 		entry_size = tuple_size / sizeof(pcell_t);
1985 		cpu_wins_no = tuples;
1986 
1987 		for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
1988 			cpu_win_tbl[t].target = 1;
1989 			cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
1990 			cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
1991 			cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
1992 			cpu_win_tbl[t].remap = ~0;
1993 			debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
1994 			    "size = 0x%0x remap = 0x%0x\n",
1995 			    cpu_win_tbl[t].target,
1996 			    cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
1997 			    cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
1998 		}
1999 	}
2000 
2001 	/*
2002 	 * Retrieve CESA SRAM data.
2003 	 */
2004 	if ((node = OF_finddevice("sram")) != -1)
2005 		if (fdt_is_compatible(node, "mrvl,cesa-sram"))
2006 			goto moveon;
2007 
2008 	if ((node = OF_finddevice("/")) == 0)
2009 		return (ENXIO);
2010 
2011 	if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
2012 		/* SRAM block is not always present. */
2013 		return (0);
2014 moveon:
2015 	sram_base = sram_size = 0;
2016 	if (fdt_regsize(node, &sram_base, &sram_size) != 0)
2017 		return (EINVAL);
2018 
2019 	cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
2020 	cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
2021 	cpu_win_tbl[t].base = sram_base;
2022 	cpu_win_tbl[t].size = sram_size;
2023 	cpu_win_tbl[t].remap = ~0;
2024 	cpu_wins_no++;
2025 	debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
2026 
2027 	return (0);
2028 }
2029 
2030 static int
2031 fdt_win_setup(void)
2032 {
2033 	phandle_t node, child;
2034 	struct soc_node_spec *soc_node;
2035 	u_long size, base;
2036 	int err, i;
2037 
2038 	node = OF_finddevice("/");
2039 	if (node == -1)
2040 		panic("fdt_win_setup: no root node");
2041 
2042 	/*
2043 	 * Traverse through all children of root and simple-bus nodes.
2044 	 * For each found device retrieve decode windows data (if applicable).
2045 	 */
2046 	child = OF_child(node);
2047 	while (child != 0) {
2048 		for (i = 0; soc_nodes[i].compat != NULL; i++) {
2049 
2050 			soc_node = &soc_nodes[i];
2051 
2052 			if (!fdt_is_compatible(child, soc_node->compat))
2053 				continue;
2054 
2055 			err = fdt_regsize(child, &base, &size);
2056 			if (err != 0)
2057 				return (err);
2058 
2059 			base = (base & 0x000fffff) | fdt_immr_va;
2060 			if (soc_node->decode_handler != NULL)
2061 				soc_node->decode_handler(base);
2062 			else
2063 				return (ENXIO);
2064 
2065 			if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
2066 				soc_node->dump_handler(base);
2067 		}
2068 
2069 		/*
2070 		 * Once done with root-level children let's move down to
2071 		 * simple-bus and its children.
2072 		 */
2073 		child = OF_peer(child);
2074 		if ((child == 0) && (node == OF_finddevice("/"))) {
2075 			node = fdt_find_compatible(node, "simple-bus", 0);
2076 			if (node == 0)
2077 				return (ENXIO);
2078 			child = OF_child(node);
2079 		}
2080 	}
2081 
2082 	return (0);
2083 }
2084 
2085 static void
2086 fdt_fixup_busfreq(phandle_t root)
2087 {
2088 	phandle_t sb;
2089 	pcell_t freq;
2090 
2091 	freq = cpu_to_fdt32(get_tclk());
2092 
2093 	/*
2094 	 * Fix bus speed in cpu node
2095 	 */
2096 	if ((sb = OF_finddevice("cpu")) != 0)
2097 		if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
2098 			OF_setprop(sb, "bus-frequency", (void *)&freq,
2099 			    sizeof(freq));
2100 
2101 	/*
2102 	 * This fixup sets the simple-bus bus-frequency property.
2103 	 */
2104 	if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
2105 		OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
2106 }
2107 
2108 static void
2109 fdt_fixup_ranges(phandle_t root)
2110 {
2111 	phandle_t node;
2112 	pcell_t par_addr_cells, addr_cells, size_cells;
2113 	pcell_t ranges[3], reg[2], *rangesptr;
2114 	int len, tuple_size, tuples_count;
2115 	uint32_t base;
2116 
2117 	/* Fix-up SoC ranges according to real fdt_immr_pa */
2118 	if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
2119 		if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
2120 		    (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
2121 			tuple_size = sizeof(pcell_t) * (par_addr_cells +
2122 			   addr_cells + size_cells);
2123 			len = OF_getprop(node, "ranges", ranges,
2124 			    sizeof(ranges));
2125 			tuples_count = len / tuple_size;
2126 			/* Unexpected settings are not supported */
2127 			if (tuples_count != 1)
2128 				goto fixup_failed;
2129 
2130 			rangesptr = &ranges[0];
2131 			rangesptr += par_addr_cells;
2132 			base = fdt_data_get((void *)rangesptr, addr_cells);
2133 			*rangesptr = cpu_to_fdt32(fdt_immr_pa);
2134 			if (OF_setprop(node, "ranges", (void *)&ranges[0],
2135 			    sizeof(ranges)) < 0)
2136 				goto fixup_failed;
2137 		}
2138 	}
2139 
2140 	/* Fix-up PCIe reg according to real PCIe registers' PA */
2141 	if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
2142 		if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
2143 		    &size_cells) == 0) {
2144 			tuple_size = sizeof(pcell_t) * (par_addr_cells +
2145 			    size_cells);
2146 			len = OF_getprop(node, "reg", reg, sizeof(reg));
2147 			tuples_count = len / tuple_size;
2148 			/* Unexpected settings are not supported */
2149 			if (tuples_count != 1)
2150 				goto fixup_failed;
2151 
2152 			base = fdt_data_get((void *)&reg[0], par_addr_cells);
2153 			base &= ~0xFF000000;
2154 			base |= fdt_immr_pa;
2155 			reg[0] = cpu_to_fdt32(base);
2156 			if (OF_setprop(node, "reg", (void *)&reg[0],
2157 			    sizeof(reg)) < 0)
2158 				goto fixup_failed;
2159 		}
2160 	}
2161 	/* Fix-up succeeded. May return and continue */
2162 	return;
2163 
2164 fixup_failed:
2165 	while (1) {
2166 		/*
2167 		 * In case of any error while fixing ranges just hang.
2168 		 *	1. No message can be displayed yet since console
2169 		 *	   is not initialized.
2170 		 *	2. Going further will cause failure on bus_space_map()
2171 		 *	   relying on the wrong ranges or data abort when
2172 		 *	   accessing PCIe registers.
2173 		 */
2174 	}
2175 }
2176 
2177 struct fdt_fixup_entry fdt_fixup_table[] = {
2178 	{ "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2179 	{ "mrvl,DB-78460", &fdt_fixup_busfreq },
2180 	{ "mrvl,DB-78460", &fdt_fixup_ranges },
2181 	{ NULL, NULL }
2182 };
2183 
2184 static int
2185 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
2186     int *pol)
2187 {
2188 
2189 	if (!fdt_is_compatible(node, "mrvl,pic") &&
2190 	    !fdt_is_compatible(node, "mrvl,mpic"))
2191 		return (ENXIO);
2192 
2193 	*interrupt = fdt32_to_cpu(intr[0]);
2194 	*trig = INTR_TRIGGER_CONFORM;
2195 	*pol = INTR_POLARITY_CONFORM;
2196 
2197 	return (0);
2198 }
2199 
2200 fdt_pic_decode_t fdt_pic_table[] = {
2201 #ifdef SOC_MV_ARMADA38X
2202 	&gic_decode_fdt,
2203 #endif
2204 	&fdt_pic_decode_ic,
2205 	NULL
2206 };
2207 
2208 uint64_t
2209 get_sar_value(void)
2210 {
2211 	uint32_t sar_low, sar_high;
2212 
2213 #if defined(SOC_MV_ARMADAXP)
2214 	sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2215 	    SAMPLE_AT_RESET_HI);
2216 	sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2217 	    SAMPLE_AT_RESET_LO);
2218 #elif defined(SOC_MV_ARMADA38X)
2219 	sar_high = 0;
2220 	sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
2221 	    SAMPLE_AT_RESET);
2222 #else
2223 	/*
2224 	 * TODO: Add getting proper values for other SoC configurations
2225 	 */
2226 	sar_high = 0;
2227 	sar_low = 0;
2228 #endif
2229 
2230 	return (((uint64_t)sar_high << 32) | sar_low);
2231 }
2232