1 /*- 2 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/malloc.h> 40 #include <sys/kdb.h> 41 #include <sys/reboot.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 47 #include <machine/bus.h> 48 #include <machine/fdt.h> 49 #include <machine/vmparam.h> 50 #include <machine/intr.h> 51 52 #include <arm/mv/mvreg.h> 53 #include <arm/mv/mvvar.h> 54 #include <arm/mv/mvwin.h> 55 56 57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); 58 59 #define IDMA_DEBUG 60 #undef IDMA_DEBUG 61 62 #define MAX_CPU_WIN 5 63 64 #ifdef DEBUG 65 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 66 printf(fmt,##args); } while (0) 67 #else 68 #define debugf(fmt, args...) 69 #endif 70 71 #ifdef DEBUG 72 #define MV_DUMP_WIN 1 73 #else 74 #define MV_DUMP_WIN 0 75 #endif 76 77 static int win_eth_can_remap(int i); 78 79 static int decode_win_cesa_valid(void); 80 static int decode_win_cpu_valid(void); 81 static int decode_win_usb_valid(void); 82 static int decode_win_usb3_valid(void); 83 static int decode_win_eth_valid(void); 84 static int decode_win_pcie_valid(void); 85 static int decode_win_sata_valid(void); 86 static int decode_win_sdhci_valid(void); 87 88 static int decode_win_idma_valid(void); 89 static int decode_win_xor_valid(void); 90 91 static void decode_win_cpu_setup(void); 92 #ifdef SOC_MV_ARMADAXP 93 static int decode_win_sdram_fixup(void); 94 #endif 95 static void decode_win_cesa_setup(u_long); 96 static void decode_win_usb_setup(u_long); 97 static void decode_win_usb3_setup(u_long); 98 static void decode_win_eth_setup(u_long); 99 static void decode_win_neta_setup(u_long); 100 static void decode_win_sata_setup(u_long); 101 static void decode_win_ahci_setup(u_long); 102 static void decode_win_sdhci_setup(u_long); 103 104 static void decode_win_idma_setup(u_long); 105 static void decode_win_xor_setup(u_long); 106 107 static void decode_win_cesa_dump(u_long); 108 static void decode_win_usb_dump(u_long); 109 static void decode_win_usb3_dump(u_long); 110 static void decode_win_eth_dump(u_long base); 111 static void decode_win_neta_dump(u_long base); 112 static void decode_win_idma_dump(u_long base); 113 static void decode_win_xor_dump(u_long base); 114 static void decode_win_ahci_dump(u_long base); 115 static void decode_win_sdhci_dump(u_long); 116 static void decode_win_pcie_dump(u_long); 117 118 static int fdt_get_ranges(const char *, void *, int, int *, int *); 119 #ifdef SOC_MV_ARMADA38X 120 int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, 121 int *trig, int *pol); 122 #endif 123 124 static int win_cpu_from_dt(void); 125 static int fdt_win_setup(void); 126 127 static uint32_t dev_mask = 0; 128 static int cpu_wins_no = 0; 129 static int eth_port = 0; 130 static int usb_port = 0; 131 static boolean_t platform_io_coherent = false; 132 133 static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; 134 135 const struct decode_win *cpu_wins = cpu_win_tbl; 136 137 typedef void (*decode_win_setup_t)(u_long); 138 typedef void (*dump_win_t)(u_long); 139 140 /* 141 * The power status of device feature is only supported on 142 * Kirkwood and Discovery SoCs. 143 */ 144 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 145 #define SOC_MV_POWER_STAT_SUPPORTED 1 146 #else 147 #define SOC_MV_POWER_STAT_SUPPORTED 0 148 #endif 149 150 struct soc_node_spec { 151 const char *compat; 152 decode_win_setup_t decode_handler; 153 dump_win_t dump_handler; 154 }; 155 156 static struct soc_node_spec soc_nodes[] = { 157 { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, 158 { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump }, 159 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 160 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, 161 { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, 162 { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, 163 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, 164 { "mrvl,sata", &decode_win_sata_setup, NULL }, 165 { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, 166 { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, 167 { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, 168 { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump }, 169 { NULL, NULL, NULL }, 170 }; 171 172 struct fdt_pm_mask_entry { 173 char *compat; 174 uint32_t mask; 175 }; 176 177 static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { 178 { "mrvl,ge", CPU_PM_CTRL_GE(0) }, 179 { "mrvl,ge", CPU_PM_CTRL_GE(1) }, 180 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, 181 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, 182 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, 183 { "mrvl,xor", CPU_PM_CTRL_XOR }, 184 { "mrvl,sata", CPU_PM_CTRL_SATA }, 185 186 { NULL, 0 } 187 }; 188 189 static __inline int 190 pm_is_disabled(uint32_t mask) 191 { 192 #if SOC_MV_POWER_STAT_SUPPORTED 193 return (soc_power_ctrl_get(mask) == mask ? 0 : 1); 194 #else 195 return (0); 196 #endif 197 } 198 199 /* 200 * Disable device using power management register. 201 * 1 - Device Power On 202 * 0 - Device Power Off 203 * Mask can be set in loader. 204 * EXAMPLE: 205 * loader> set hw.pm-disable-mask=0x2 206 * 207 * Common mask: 208 * |-------------------------------| 209 * | Device | Kirkwood | Discovery | 210 * |-------------------------------| 211 * | USB0 | 0x00008 | 0x020000 | 212 * |-------------------------------| 213 * | USB1 | - | 0x040000 | 214 * |-------------------------------| 215 * | USB2 | - | 0x080000 | 216 * |-------------------------------| 217 * | GE0 | 0x00001 | 0x000002 | 218 * |-------------------------------| 219 * | GE1 | - | 0x000004 | 220 * |-------------------------------| 221 * | IDMA | - | 0x100000 | 222 * |-------------------------------| 223 * | XOR | 0x10000 | 0x200000 | 224 * |-------------------------------| 225 * | CESA | 0x20000 | 0x400000 | 226 * |-------------------------------| 227 * | SATA | 0x04000 | 0x004000 | 228 * --------------------------------| 229 * This feature can be used only on Kirkwood and Discovery 230 * machines. 231 */ 232 static __inline void 233 pm_disable_device(int mask) 234 { 235 #ifdef DIAGNOSTIC 236 uint32_t reg; 237 238 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 239 printf("Power Management Register: 0%x\n", reg); 240 241 reg &= ~mask; 242 soc_power_ctrl_set(reg); 243 printf("Device %x is disabled\n", mask); 244 245 reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); 246 printf("Power Management Register: 0%x\n", reg); 247 #endif 248 } 249 250 int 251 fdt_pm(phandle_t node) 252 { 253 uint32_t cpu_pm_ctrl; 254 int i, ena, compat; 255 256 ena = 1; 257 cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); 258 for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { 259 if (dev_mask & (1 << i)) 260 continue; 261 262 compat = ofw_bus_node_is_compatible(node, 263 fdt_pm_mask_table[i].compat); 264 #if defined(SOC_MV_KIRKWOOD) 265 if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 266 dev_mask |= (1 << i); 267 ena = 0; 268 break; 269 } else if (compat) { 270 dev_mask |= (1 << i); 271 break; 272 } 273 #else 274 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { 275 dev_mask |= (1 << i); 276 ena = 0; 277 break; 278 } else if (compat) { 279 dev_mask |= (1 << i); 280 break; 281 } 282 #endif 283 } 284 285 return (ena); 286 } 287 288 uint32_t 289 read_cpu_ctrl(uint32_t reg) 290 { 291 292 return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); 293 } 294 295 void 296 write_cpu_ctrl(uint32_t reg, uint32_t val) 297 { 298 299 bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); 300 } 301 302 #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) 303 uint32_t 304 read_cpu_mp_clocks(uint32_t reg) 305 { 306 307 return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); 308 } 309 310 void 311 write_cpu_mp_clocks(uint32_t reg, uint32_t val) 312 { 313 314 bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); 315 } 316 317 uint32_t 318 read_cpu_misc(uint32_t reg) 319 { 320 321 return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); 322 } 323 324 void 325 write_cpu_misc(uint32_t reg, uint32_t val) 326 { 327 328 bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); 329 } 330 #endif 331 332 void 333 cpu_reset(void) 334 { 335 336 #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) 337 write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); 338 write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 339 #else 340 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); 341 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); 342 #endif 343 while (1); 344 } 345 346 uint32_t 347 cpu_extra_feat(void) 348 { 349 uint32_t dev, rev; 350 uint32_t ef = 0; 351 352 soc_id(&dev, &rev); 353 354 switch (dev) { 355 case MV_DEV_88F6281: 356 case MV_DEV_88F6282: 357 case MV_DEV_88RC8180: 358 case MV_DEV_MV78100_Z0: 359 case MV_DEV_MV78100: 360 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); 361 break; 362 case MV_DEV_88F5182: 363 case MV_DEV_88F5281: 364 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); 365 break; 366 default: 367 if (bootverbose) 368 printf("This ARM Core does not support any extra features\n"); 369 } 370 371 return (ef); 372 } 373 374 /* 375 * Get the power status of device. This feature is only supported on 376 * Kirkwood and Discovery SoCs. 377 */ 378 uint32_t 379 soc_power_ctrl_get(uint32_t mask) 380 { 381 382 #if SOC_MV_POWER_STAT_SUPPORTED 383 if (mask != CPU_PM_CTRL_NONE) 384 mask &= read_cpu_ctrl(CPU_PM_CTRL); 385 386 return (mask); 387 #else 388 return (mask); 389 #endif 390 } 391 392 /* 393 * Set the power status of device. This feature is only supported on 394 * Kirkwood and Discovery SoCs. 395 */ 396 void 397 soc_power_ctrl_set(uint32_t mask) 398 { 399 400 #if !defined(SOC_MV_ORION) 401 if (mask != CPU_PM_CTRL_NONE) 402 write_cpu_ctrl(CPU_PM_CTRL, mask); 403 #endif 404 } 405 406 void 407 soc_id(uint32_t *dev, uint32_t *rev) 408 { 409 410 /* 411 * Notice: system identifiers are available in the registers range of 412 * PCIE controller, so using this function is only allowed (and 413 * possible) after the internal registers range has been mapped in via 414 * devmap_bootstrap(). 415 */ 416 *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; 417 *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; 418 } 419 420 static void 421 soc_identify(void) 422 { 423 uint32_t d, r, size, mode, freq; 424 const char *dev; 425 const char *rev; 426 427 soc_id(&d, &r); 428 429 printf("SOC: "); 430 if (bootverbose) 431 printf("(0x%4x:0x%02x) ", d, r); 432 433 rev = ""; 434 switch (d) { 435 case MV_DEV_88F5181: 436 dev = "Marvell 88F5181"; 437 if (r == 3) 438 rev = "B1"; 439 break; 440 case MV_DEV_88F5182: 441 dev = "Marvell 88F5182"; 442 if (r == 2) 443 rev = "A2"; 444 break; 445 case MV_DEV_88F5281: 446 dev = "Marvell 88F5281"; 447 if (r == 4) 448 rev = "D0"; 449 else if (r == 5) 450 rev = "D1"; 451 else if (r == 6) 452 rev = "D2"; 453 break; 454 case MV_DEV_88F6281: 455 dev = "Marvell 88F6281"; 456 if (r == 0) 457 rev = "Z0"; 458 else if (r == 2) 459 rev = "A0"; 460 else if (r == 3) 461 rev = "A1"; 462 break; 463 case MV_DEV_88RC8180: 464 dev = "Marvell 88RC8180"; 465 break; 466 case MV_DEV_88RC9480: 467 dev = "Marvell 88RC9480"; 468 break; 469 case MV_DEV_88RC9580: 470 dev = "Marvell 88RC9580"; 471 break; 472 case MV_DEV_88F6781: 473 dev = "Marvell 88F6781"; 474 if (r == 2) 475 rev = "Y0"; 476 break; 477 case MV_DEV_88F6282: 478 dev = "Marvell 88F6282"; 479 if (r == 0) 480 rev = "A0"; 481 else if (r == 1) 482 rev = "A1"; 483 break; 484 case MV_DEV_88F6828: 485 dev = "Marvell 88F6828"; 486 break; 487 case MV_DEV_88F6820: 488 dev = "Marvell 88F6820"; 489 break; 490 case MV_DEV_88F6810: 491 dev = "Marvell 88F6810"; 492 break; 493 case MV_DEV_MV78100_Z0: 494 dev = "Marvell MV78100 Z0"; 495 break; 496 case MV_DEV_MV78100: 497 dev = "Marvell MV78100"; 498 break; 499 case MV_DEV_MV78160: 500 dev = "Marvell MV78160"; 501 break; 502 case MV_DEV_MV78260: 503 dev = "Marvell MV78260"; 504 break; 505 case MV_DEV_MV78460: 506 dev = "Marvell MV78460"; 507 break; 508 default: 509 dev = "UNKNOWN"; 510 break; 511 } 512 513 printf("%s", dev); 514 if (*rev != '\0') 515 printf(" rev %s", rev); 516 printf(", TClock %dMHz", get_tclk() / 1000 / 1000); 517 freq = get_cpu_freq(); 518 if (freq != 0) 519 printf(", Frequency %dMHz", freq / 1000 / 1000); 520 printf("\n"); 521 522 mode = read_cpu_ctrl(CPU_CONFIG); 523 printf(" Instruction cache prefetch %s, data cache prefetch %s\n", 524 (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", 525 (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); 526 527 switch (d) { 528 case MV_DEV_88F6281: 529 case MV_DEV_88F6282: 530 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; 531 printf(" 256KB 4-way set-associative %s unified L2 cache\n", 532 mode ? "write-through" : "write-back"); 533 break; 534 case MV_DEV_MV78100: 535 mode = read_cpu_ctrl(CPU_CONTROL); 536 size = mode & CPU_CONTROL_L2_SIZE; 537 mode = mode & CPU_CONTROL_L2_MODE; 538 printf(" %s set-associative %s unified L2 cache\n", 539 size ? "256KB 4-way" : "512KB 8-way", 540 mode ? "write-through" : "write-back"); 541 break; 542 default: 543 break; 544 } 545 } 546 547 static void 548 platform_identify(void *dummy) 549 { 550 551 soc_identify(); 552 553 /* 554 * XXX Board identification e.g. read out from FPGA or similar should 555 * go here 556 */ 557 } 558 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, 559 NULL); 560 561 #ifdef KDB 562 static void 563 mv_enter_debugger(void *dummy) 564 { 565 566 if (boothowto & RB_KDB) 567 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 568 } 569 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); 570 #endif 571 572 int 573 soc_decode_win(void) 574 { 575 uint32_t dev, rev; 576 int mask, err; 577 578 mask = 0; 579 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); 580 581 if (mask != 0) 582 pm_disable_device(mask); 583 584 /* Retrieve data about physical addresses from device tree. */ 585 if ((err = win_cpu_from_dt()) != 0) 586 return (err); 587 588 /* Retrieve our ID: some windows facilities vary between SoC models */ 589 soc_id(&dev, &rev); 590 591 #ifdef SOC_MV_ARMADAXP 592 if ((err = decode_win_sdram_fixup()) != 0) 593 return(err); 594 #endif 595 596 if (!decode_win_cpu_valid() || !decode_win_usb_valid() || 597 !decode_win_eth_valid() || !decode_win_idma_valid() || 598 !decode_win_pcie_valid() || !decode_win_sata_valid() || 599 !decode_win_xor_valid() || !decode_win_usb3_valid() || 600 !decode_win_sdhci_valid() || !decode_win_cesa_valid()) 601 return (EINVAL); 602 603 decode_win_cpu_setup(); 604 if (MV_DUMP_WIN) 605 soc_dump_decode_win(); 606 607 eth_port = 0; 608 usb_port = 0; 609 if ((err = fdt_win_setup()) != 0) 610 return (err); 611 612 return (0); 613 } 614 615 /************************************************************************** 616 * Decode windows registers accessors 617 **************************************************************************/ 618 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 619 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 620 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 621 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 622 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) 623 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) 624 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) 625 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) 626 627 WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) 628 WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) 629 WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) 630 WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) 631 632 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) 633 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) 634 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) 635 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) 636 637 #ifdef SOC_MV_ARMADA38X 638 WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) 639 WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) 640 WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) 641 WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) 642 #endif 643 644 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) 645 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) 646 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) 647 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) 648 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) 649 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) 650 651 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) 652 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) 653 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) 654 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) 655 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) 656 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) 657 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) 658 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) 659 660 WIN_REG_BASE_RD(win_eth, bare, 0x290) 661 WIN_REG_BASE_RD(win_eth, epap, 0x294) 662 WIN_REG_BASE_WR(win_eth, bare, 0x290) 663 WIN_REG_BASE_WR(win_eth, epap, 0x294) 664 665 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); 666 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); 667 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); 668 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); 669 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); 670 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); 671 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); 672 WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 673 WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); 674 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); 675 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); 676 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); 677 678 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) 679 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) 680 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) 681 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) 682 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) 683 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) 684 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) 685 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) 686 WIN_REG_BASE_RD(win_idma, bare, 0xa80) 687 WIN_REG_BASE_WR(win_idma, bare, 0xa80) 688 689 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); 690 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); 691 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); 692 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); 693 #if defined(SOC_MV_ARMADA38X) 694 WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); 695 WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); 696 #endif 697 698 WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 699 WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); 700 WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); 701 WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); 702 703 #ifndef SOC_MV_DOVE 704 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 705 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 706 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) 707 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) 708 #else 709 /* 710 * On 88F6781 (Dove) SoC DDR Controller is accessed through 711 * single MBUS <-> AXI bridge. In this case we provide emulated 712 * ddr_br_read() and ddr_sz_read() functions to keep compatibility 713 * with common decoding windows setup code. 714 */ 715 716 static inline uint32_t ddr_br_read(int i) 717 { 718 uint32_t mmap; 719 720 /* Read Memory Address Map Register for CS i */ 721 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 722 723 /* Return CS i base address */ 724 return (mmap & 0xFF000000); 725 } 726 727 static inline uint32_t ddr_sz_read(int i) 728 { 729 uint32_t mmap, size; 730 731 /* Read Memory Address Map Register for CS i */ 732 mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); 733 734 /* Extract size of CS space in 64kB units */ 735 size = (1 << ((mmap >> 16) & 0x0F)); 736 737 /* Return CS size and enable/disable status */ 738 return (((size - 1) << 16) | (mmap & 0x01)); 739 } 740 #endif 741 742 /************************************************************************** 743 * Decode windows helper routines 744 **************************************************************************/ 745 void 746 soc_dump_decode_win(void) 747 { 748 uint32_t dev, rev; 749 int i; 750 751 soc_id(&dev, &rev); 752 753 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 754 printf("CPU window#%d: c 0x%08x, b 0x%08x", i, 755 win_cpu_cr_read(i), 756 win_cpu_br_read(i)); 757 758 if (win_cpu_can_remap(i)) 759 printf(", rl 0x%08x, rh 0x%08x", 760 win_cpu_remap_l_read(i), 761 win_cpu_remap_h_read(i)); 762 763 printf("\n"); 764 } 765 printf("Internal regs base: 0x%08x\n", 766 bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); 767 768 for (i = 0; i < MV_WIN_DDR_MAX; i++) 769 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, 770 ddr_br_read(i), ddr_sz_read(i)); 771 } 772 773 /************************************************************************** 774 * CPU windows routines 775 **************************************************************************/ 776 int 777 win_cpu_can_remap(int i) 778 { 779 uint32_t dev, rev; 780 781 soc_id(&dev, &rev); 782 783 /* Depending on the SoC certain windows have remap capability */ 784 if ((dev == MV_DEV_88F5182 && i < 2) || 785 (dev == MV_DEV_88F5281 && i < 4) || 786 (dev == MV_DEV_88F6281 && i < 4) || 787 (dev == MV_DEV_88F6282 && i < 4) || 788 (dev == MV_DEV_88F6828 && i < 20) || 789 (dev == MV_DEV_88F6820 && i < 20) || 790 (dev == MV_DEV_88F6810 && i < 20) || 791 (dev == MV_DEV_88RC8180 && i < 2) || 792 (dev == MV_DEV_88F6781 && i < 4) || 793 (dev == MV_DEV_MV78100_Z0 && i < 8) || 794 ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) 795 return (1); 796 797 return (0); 798 } 799 800 /* XXX This should check for overlapping remap fields too.. */ 801 int 802 decode_win_overlap(int win, int win_no, const struct decode_win *wintab) 803 { 804 const struct decode_win *tab; 805 int i; 806 807 tab = wintab; 808 809 for (i = 0; i < win_no; i++, tab++) { 810 if (i == win) 811 /* Skip self */ 812 continue; 813 814 if ((tab->base + tab->size - 1) < (wintab + win)->base) 815 continue; 816 817 else if (((wintab + win)->base + (wintab + win)->size - 1) < 818 tab->base) 819 continue; 820 else 821 return (i); 822 } 823 824 return (-1); 825 } 826 827 static int 828 decode_win_cpu_valid(void) 829 { 830 int i, j, rv; 831 uint32_t b, e, s; 832 833 if (cpu_wins_no > MV_WIN_CPU_MAX) { 834 printf("CPU windows: too many entries: %d\n", cpu_wins_no); 835 return (0); 836 } 837 838 rv = 1; 839 for (i = 0; i < cpu_wins_no; i++) { 840 841 if (cpu_wins[i].target == 0) { 842 printf("CPU window#%d: DDR target window is not " 843 "supposed to be reprogrammed!\n", i); 844 rv = 0; 845 } 846 847 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { 848 printf("CPU window#%d: not capable of remapping, but " 849 "val 0x%08x defined\n", i, cpu_wins[i].remap); 850 rv = 0; 851 } 852 853 s = cpu_wins[i].size; 854 b = cpu_wins[i].base; 855 e = b + s - 1; 856 if (s > (0xFFFFFFFF - b + 1)) { 857 /* 858 * XXX this boundary check should account for 64bit 859 * and remapping.. 860 */ 861 printf("CPU window#%d: no space for size 0x%08x at " 862 "0x%08x\n", i, s, b); 863 rv = 0; 864 continue; 865 } 866 867 if (b != rounddown2(b, s)) { 868 printf("CPU window#%d: address 0x%08x is not aligned " 869 "to 0x%08x\n", i, b, s); 870 rv = 0; 871 continue; 872 } 873 874 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); 875 if (j >= 0) { 876 printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " 877 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 878 cpu_wins[j].base, 879 cpu_wins[j].base + cpu_wins[j].size - 1); 880 rv = 0; 881 } 882 } 883 884 return (rv); 885 } 886 887 int 888 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, 889 vm_paddr_t remap) 890 { 891 uint32_t br, cr; 892 int win, i; 893 894 if (remap == ~0) { 895 win = MV_WIN_CPU_MAX - 1; 896 i = -1; 897 } else { 898 win = 0; 899 i = 1; 900 } 901 902 while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { 903 cr = win_cpu_cr_read(win); 904 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) 905 break; 906 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | 907 (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == 908 ((attr << MV_WIN_CPU_ATTR_SHIFT) | 909 (target << MV_WIN_CPU_TARGET_SHIFT))) 910 break; 911 win += i; 912 } 913 if ((win < 0) || (win >= MV_WIN_CPU_MAX) || 914 ((remap != ~0) && (win_cpu_can_remap(win) == 0))) 915 return (-1); 916 917 br = base & 0xffff0000; 918 win_cpu_br_write(win, br); 919 920 if (win_cpu_can_remap(win)) { 921 if (remap != ~0) { 922 win_cpu_remap_l_write(win, remap & 0xffff0000); 923 win_cpu_remap_h_write(win, 0); 924 } else { 925 /* 926 * Remap function is not used for a given window 927 * (capable of remapping) - set remap field with the 928 * same value as base. 929 */ 930 win_cpu_remap_l_write(win, base & 0xffff0000); 931 win_cpu_remap_h_write(win, 0); 932 } 933 } 934 935 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | 936 (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; 937 win_cpu_cr_write(win, cr); 938 939 return (0); 940 } 941 942 static void 943 decode_win_cpu_setup(void) 944 { 945 int i; 946 947 /* Disable all CPU windows */ 948 for (i = 0; i < MV_WIN_CPU_MAX; i++) { 949 win_cpu_cr_write(i, 0); 950 win_cpu_br_write(i, 0); 951 if (win_cpu_can_remap(i)) { 952 win_cpu_remap_l_write(i, 0); 953 win_cpu_remap_h_write(i, 0); 954 } 955 } 956 957 for (i = 0; i < cpu_wins_no; i++) 958 if (cpu_wins[i].target > 0) 959 decode_win_cpu_set(cpu_wins[i].target, 960 cpu_wins[i].attr, cpu_wins[i].base, 961 cpu_wins[i].size, cpu_wins[i].remap); 962 963 } 964 965 #ifdef SOC_MV_ARMADAXP 966 static int 967 decode_win_sdram_fixup(void) 968 { 969 struct mem_region mr[FDT_MEM_REGIONS]; 970 uint8_t window_valid[MV_WIN_DDR_MAX]; 971 int mr_cnt, err, i, j; 972 uint32_t valid_win_num = 0; 973 974 /* Grab physical memory regions information from device tree. */ 975 err = fdt_get_mem_regions(mr, &mr_cnt, NULL); 976 if (err != 0) 977 return (err); 978 979 for (i = 0; i < MV_WIN_DDR_MAX; i++) 980 window_valid[i] = 0; 981 982 /* Try to match entries from device tree with settings from u-boot */ 983 for (i = 0; i < mr_cnt; i++) { 984 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 985 if (ddr_is_active(j) && 986 (ddr_base(j) == mr[i].mr_start) && 987 (ddr_size(j) == mr[i].mr_size)) { 988 window_valid[j] = 1; 989 valid_win_num++; 990 } 991 } 992 } 993 994 if (mr_cnt != valid_win_num) 995 return (EINVAL); 996 997 /* Destroy windows without corresponding device tree entry */ 998 for (j = 0; j < MV_WIN_DDR_MAX; j++) { 999 if (ddr_is_active(j) && (window_valid[j] != 1)) { 1000 printf("Disabling SDRAM decoding window: %d\n", j); 1001 ddr_disable(j); 1002 } 1003 } 1004 1005 return (0); 1006 } 1007 #endif 1008 /* 1009 * Check if we're able to cover all active DDR banks. 1010 */ 1011 static int 1012 decode_win_can_cover_ddr(int max) 1013 { 1014 int i, c; 1015 1016 c = 0; 1017 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1018 if (ddr_is_active(i)) 1019 c++; 1020 1021 if (c > max) { 1022 printf("Unable to cover all active DDR banks: " 1023 "%d, available windows: %d\n", c, max); 1024 return (0); 1025 } 1026 1027 return (1); 1028 } 1029 1030 /************************************************************************** 1031 * DDR windows routines 1032 **************************************************************************/ 1033 int 1034 ddr_is_active(int i) 1035 { 1036 1037 if (ddr_sz_read(i) & 0x1) 1038 return (1); 1039 1040 return (0); 1041 } 1042 1043 void 1044 ddr_disable(int i) 1045 { 1046 1047 ddr_sz_write(i, 0); 1048 ddr_br_write(i, 0); 1049 } 1050 1051 uint32_t 1052 ddr_base(int i) 1053 { 1054 1055 return (ddr_br_read(i) & 0xff000000); 1056 } 1057 1058 uint32_t 1059 ddr_size(int i) 1060 { 1061 1062 return ((ddr_sz_read(i) | 0x00ffffff) + 1); 1063 } 1064 1065 uint32_t 1066 ddr_attr(int i) 1067 { 1068 uint32_t dev, rev, attr; 1069 1070 soc_id(&dev, &rev); 1071 if (dev == MV_DEV_88RC8180) 1072 return ((ddr_sz_read(i) & 0xf0) >> 4); 1073 if (dev == MV_DEV_88F6781) 1074 return (0); 1075 1076 attr = (i == 0 ? 0xe : 1077 (i == 1 ? 0xd : 1078 (i == 2 ? 0xb : 1079 (i == 3 ? 0x7 : 0xff)))); 1080 if (platform_io_coherent) 1081 attr |= 0x10; 1082 1083 return (attr); 1084 } 1085 1086 uint32_t 1087 ddr_target(int i) 1088 { 1089 uint32_t dev, rev; 1090 1091 soc_id(&dev, &rev); 1092 if (dev == MV_DEV_88RC8180) { 1093 i = (ddr_sz_read(i) & 0xf0) >> 4; 1094 return (i == 0xe ? 0xc : 1095 (i == 0xd ? 0xd : 1096 (i == 0xb ? 0xe : 1097 (i == 0x7 ? 0xf : 0xc)))); 1098 } 1099 1100 /* 1101 * On SOCs other than 88RC8180 Mbus unit ID for 1102 * DDR SDRAM controller is always 0x0. 1103 */ 1104 return (0); 1105 } 1106 1107 /************************************************************************** 1108 * CESA windows routines 1109 **************************************************************************/ 1110 static int 1111 decode_win_cesa_valid(void) 1112 { 1113 1114 return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); 1115 } 1116 1117 static void 1118 decode_win_cesa_dump(u_long base) 1119 { 1120 int i; 1121 1122 for (i = 0; i < MV_WIN_CESA_MAX; i++) 1123 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, 1124 win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); 1125 } 1126 1127 /* 1128 * Set CESA decode windows. 1129 */ 1130 static void 1131 decode_win_cesa_setup(u_long base) 1132 { 1133 uint32_t br, cr; 1134 uint64_t size; 1135 int i, j; 1136 1137 for (i = 0; i < MV_WIN_CESA_MAX; i++) { 1138 win_cesa_cr_write(base, i, 0); 1139 win_cesa_br_write(base, i, 0); 1140 } 1141 1142 /* Only access to active DRAM banks is required */ 1143 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1144 if (ddr_is_active(i)) { 1145 br = ddr_base(i); 1146 1147 size = ddr_size(i); 1148 #ifdef SOC_MV_ARMADA38X 1149 /* 1150 * Armada 38x SoC's equipped with 4GB DRAM 1151 * suffer freeze during CESA operation, if 1152 * MBUS window opened at given DRAM CS reaches 1153 * end of the address space. Apply a workaround 1154 * by setting the window size to the closest possible 1155 * value, i.e. divide it by 2. 1156 */ 1157 if (size + ddr_base(i) == 0x100000000ULL) 1158 size /= 2; 1159 #endif 1160 1161 cr = (((size - 1) & 0xffff0000) | 1162 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1163 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1164 IO_WIN_ENA_MASK); 1165 1166 /* Set the first free CESA window */ 1167 for (j = 0; j < MV_WIN_CESA_MAX; j++) { 1168 if (win_cesa_cr_read(base, j) & 0x1) 1169 continue; 1170 1171 win_cesa_br_write(base, j, br); 1172 win_cesa_cr_write(base, j, cr); 1173 break; 1174 } 1175 } 1176 } 1177 } 1178 1179 /************************************************************************** 1180 * USB windows routines 1181 **************************************************************************/ 1182 static int 1183 decode_win_usb_valid(void) 1184 { 1185 1186 return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); 1187 } 1188 1189 static void 1190 decode_win_usb_dump(u_long base) 1191 { 1192 int i; 1193 1194 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) 1195 return; 1196 1197 for (i = 0; i < MV_WIN_USB_MAX; i++) 1198 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, 1199 win_usb_cr_read(base, i), win_usb_br_read(base, i)); 1200 } 1201 1202 /* 1203 * Set USB decode windows. 1204 */ 1205 static void 1206 decode_win_usb_setup(u_long base) 1207 { 1208 uint32_t br, cr; 1209 int i, j; 1210 1211 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) 1212 return; 1213 1214 usb_port++; 1215 1216 for (i = 0; i < MV_WIN_USB_MAX; i++) { 1217 win_usb_cr_write(base, i, 0); 1218 win_usb_br_write(base, i, 0); 1219 } 1220 1221 /* Only access to active DRAM banks is required */ 1222 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1223 if (ddr_is_active(i)) { 1224 br = ddr_base(i); 1225 /* 1226 * XXX for 6281 we should handle Mbus write 1227 * burst limit field in the ctrl reg 1228 */ 1229 cr = (((ddr_size(i) - 1) & 0xffff0000) | 1230 (ddr_attr(i) << 8) | 1231 (ddr_target(i) << 4) | 1); 1232 1233 /* Set the first free USB window */ 1234 for (j = 0; j < MV_WIN_USB_MAX; j++) { 1235 if (win_usb_cr_read(base, j) & 0x1) 1236 continue; 1237 1238 win_usb_br_write(base, j, br); 1239 win_usb_cr_write(base, j, cr); 1240 break; 1241 } 1242 } 1243 } 1244 } 1245 1246 /************************************************************************** 1247 * USB3 windows routines 1248 **************************************************************************/ 1249 #ifdef SOC_MV_ARMADA38X 1250 static int 1251 decode_win_usb3_valid(void) 1252 { 1253 1254 return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); 1255 } 1256 1257 static void 1258 decode_win_usb3_dump(u_long base) 1259 { 1260 int i; 1261 1262 for (i = 0; i < MV_WIN_USB3_MAX; i++) 1263 printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, 1264 win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); 1265 } 1266 1267 /* 1268 * Set USB3 decode windows 1269 */ 1270 static void 1271 decode_win_usb3_setup(u_long base) 1272 { 1273 uint32_t br, cr; 1274 int i, j; 1275 1276 for (i = 0; i < MV_WIN_USB3_MAX; i++) { 1277 win_usb3_cr_write(base, i, 0); 1278 win_usb3_br_write(base, i, 0); 1279 } 1280 1281 /* Only access to active DRAM banks is required */ 1282 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1283 if (ddr_is_active(i)) { 1284 br = ddr_base(i); 1285 cr = (((ddr_size(i) - 1) & 1286 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 1287 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 1288 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 1289 IO_WIN_ENA_MASK); 1290 1291 /* Set the first free USB3.0 window */ 1292 for (j = 0; j < MV_WIN_USB3_MAX; j++) { 1293 if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) 1294 continue; 1295 1296 win_usb3_br_write(base, j, br); 1297 win_usb3_cr_write(base, j, cr); 1298 break; 1299 } 1300 } 1301 } 1302 } 1303 #else 1304 /* 1305 * Provide dummy functions to satisfy the build 1306 * for SoCs not equipped with USB3 1307 */ 1308 static int 1309 decode_win_usb3_valid(void) 1310 { 1311 1312 return (1); 1313 } 1314 1315 static void 1316 decode_win_usb3_setup(u_long base) 1317 { 1318 } 1319 1320 static void 1321 decode_win_usb3_dump(u_long base) 1322 { 1323 } 1324 #endif 1325 /************************************************************************** 1326 * ETH windows routines 1327 **************************************************************************/ 1328 1329 static int 1330 win_eth_can_remap(int i) 1331 { 1332 1333 /* ETH encode windows 0-3 have remap capability */ 1334 if (i < 4) 1335 return (1); 1336 1337 return (0); 1338 } 1339 1340 static int 1341 eth_bare_read(uint32_t base, int i) 1342 { 1343 uint32_t v; 1344 1345 v = win_eth_bare_read(base); 1346 v &= (1 << i); 1347 1348 return (v >> i); 1349 } 1350 1351 static void 1352 eth_bare_write(uint32_t base, int i, int val) 1353 { 1354 uint32_t v; 1355 1356 v = win_eth_bare_read(base); 1357 v &= ~(1 << i); 1358 v |= (val << i); 1359 win_eth_bare_write(base, v); 1360 } 1361 1362 static void 1363 eth_epap_write(uint32_t base, int i, int val) 1364 { 1365 uint32_t v; 1366 1367 v = win_eth_epap_read(base); 1368 v &= ~(0x3 << (i * 2)); 1369 v |= (val << (i * 2)); 1370 win_eth_epap_write(base, v); 1371 } 1372 1373 static void 1374 decode_win_eth_dump(u_long base) 1375 { 1376 int i; 1377 1378 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) 1379 return; 1380 1381 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1382 printf("ETH window#%d: b 0x%08x, s 0x%08x", i, 1383 win_eth_br_read(base, i), 1384 win_eth_sz_read(base, i)); 1385 1386 if (win_eth_can_remap(i)) 1387 printf(", ha 0x%08x", 1388 win_eth_har_read(base, i)); 1389 1390 printf("\n"); 1391 } 1392 printf("ETH windows: bare 0x%08x, epap 0x%08x\n", 1393 win_eth_bare_read(base), 1394 win_eth_epap_read(base)); 1395 } 1396 1397 #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) 1398 1399 static void 1400 decode_win_eth_setup(u_long base) 1401 { 1402 uint32_t br, sz; 1403 int i, j; 1404 1405 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) 1406 return; 1407 1408 eth_port++; 1409 1410 /* Disable, clear and revoke protection for all ETH windows */ 1411 for (i = 0; i < MV_WIN_ETH_MAX; i++) { 1412 1413 eth_bare_write(base, i, 1); 1414 eth_epap_write(base, i, 0); 1415 win_eth_br_write(base, i, 0); 1416 win_eth_sz_write(base, i, 0); 1417 if (win_eth_can_remap(i)) 1418 win_eth_har_write(base, i, 0); 1419 } 1420 1421 /* Only access to active DRAM banks is required */ 1422 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1423 if (ddr_is_active(i)) { 1424 1425 br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); 1426 sz = ((ddr_size(i) - 1) & 0xffff0000); 1427 1428 /* Set the first free ETH window */ 1429 for (j = 0; j < MV_WIN_ETH_MAX; j++) { 1430 if (eth_bare_read(base, j) == 0) 1431 continue; 1432 1433 win_eth_br_write(base, j, br); 1434 win_eth_sz_write(base, j, sz); 1435 1436 /* XXX remapping ETH windows not supported */ 1437 1438 /* Set protection RW */ 1439 eth_epap_write(base, j, 0x3); 1440 1441 /* Enable window */ 1442 eth_bare_write(base, j, 0); 1443 break; 1444 } 1445 } 1446 } 1447 1448 static void 1449 decode_win_neta_dump(u_long base) 1450 { 1451 1452 decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); 1453 } 1454 1455 static void 1456 decode_win_neta_setup(u_long base) 1457 { 1458 1459 decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); 1460 } 1461 1462 static int 1463 decode_win_eth_valid(void) 1464 { 1465 1466 return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); 1467 } 1468 1469 /************************************************************************** 1470 * PCIE windows routines 1471 **************************************************************************/ 1472 static void 1473 decode_win_pcie_dump(u_long base) 1474 { 1475 int i; 1476 1477 printf("PCIE windows base 0x%08lx\n", base); 1478 for (i = 0; i < MV_WIN_PCIE_MAX; i++) 1479 printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", 1480 i, win_pcie_cr_read(base, i), 1481 win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); 1482 1483 for (i = 0; i < MV_PCIE_BAR_MAX; i++) 1484 printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", 1485 i, pcie_bar_cr_read(base, i), 1486 pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); 1487 } 1488 1489 void 1490 decode_win_pcie_setup(u_long base) 1491 { 1492 uint32_t size = 0, ddrbase = ~0; 1493 uint32_t cr, br; 1494 int i, j; 1495 1496 for (i = 0; i < MV_PCIE_BAR_MAX; i++) { 1497 pcie_bar_br_write(base, i, 1498 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1499 if (i < 3) 1500 pcie_bar_brh_write(base, i, 0); 1501 if (i > 0) 1502 pcie_bar_cr_write(base, i, 0); 1503 } 1504 1505 for (i = 0; i < MV_WIN_PCIE_MAX; i++) { 1506 win_pcie_cr_write(base, i, 0); 1507 win_pcie_br_write(base, i, 0); 1508 win_pcie_remap_write(base, i, 0); 1509 } 1510 1511 /* On End-Point only set BAR size to 1MB regardless of DDR size */ 1512 if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) 1513 & MV_PCIE_ROOT_CMPLX) == 0) { 1514 pcie_bar_cr_write(base, 1, 0xf0000 | 1); 1515 return; 1516 } 1517 1518 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 1519 if (ddr_is_active(i)) { 1520 /* Map DDR to BAR 1 */ 1521 cr = (ddr_size(i) - 1) & 0xffff0000; 1522 size += ddr_size(i) & 0xffff0000; 1523 cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 1524 br = ddr_base(i); 1525 if (br < ddrbase) 1526 ddrbase = br; 1527 1528 /* Use the first available PCIE window */ 1529 for (j = 0; j < MV_WIN_PCIE_MAX; j++) { 1530 if (win_pcie_cr_read(base, j) != 0) 1531 continue; 1532 1533 win_pcie_br_write(base, j, br); 1534 win_pcie_cr_write(base, j, cr); 1535 break; 1536 } 1537 } 1538 } 1539 1540 /* 1541 * Upper 16 bits in BAR register is interpreted as BAR size 1542 * (in 64 kB units) plus 64kB, so subtract 0x10000 1543 * form value passed to register to get correct value. 1544 */ 1545 size -= 0x10000; 1546 pcie_bar_cr_write(base, 1, size | 1); 1547 pcie_bar_br_write(base, 1, ddrbase | 1548 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1549 pcie_bar_br_write(base, 0, fdt_immr_pa | 1550 MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); 1551 } 1552 1553 static int 1554 decode_win_pcie_valid(void) 1555 { 1556 1557 return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); 1558 } 1559 1560 /************************************************************************** 1561 * IDMA windows routines 1562 **************************************************************************/ 1563 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) 1564 static int 1565 idma_bare_read(u_long base, int i) 1566 { 1567 uint32_t v; 1568 1569 v = win_idma_bare_read(base); 1570 v &= (1 << i); 1571 1572 return (v >> i); 1573 } 1574 1575 static void 1576 idma_bare_write(u_long base, int i, int val) 1577 { 1578 uint32_t v; 1579 1580 v = win_idma_bare_read(base); 1581 v &= ~(1 << i); 1582 v |= (val << i); 1583 win_idma_bare_write(base, v); 1584 } 1585 1586 /* 1587 * Sets channel protection 'val' for window 'w' on channel 'c' 1588 */ 1589 static void 1590 idma_cap_write(u_long base, int c, int w, int val) 1591 { 1592 uint32_t v; 1593 1594 v = win_idma_cap_read(base, c); 1595 v &= ~(0x3 << (w * 2)); 1596 v |= (val << (w * 2)); 1597 win_idma_cap_write(base, c, v); 1598 } 1599 1600 /* 1601 * Set protection 'val' on all channels for window 'w' 1602 */ 1603 static void 1604 idma_set_prot(u_long base, int w, int val) 1605 { 1606 int c; 1607 1608 for (c = 0; c < MV_IDMA_CHAN_MAX; c++) 1609 idma_cap_write(base, c, w, val); 1610 } 1611 1612 static int 1613 win_idma_can_remap(int i) 1614 { 1615 1616 /* IDMA decode windows 0-3 have remap capability */ 1617 if (i < 4) 1618 return (1); 1619 1620 return (0); 1621 } 1622 1623 void 1624 decode_win_idma_setup(u_long base) 1625 { 1626 uint32_t br, sz; 1627 int i, j; 1628 1629 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1630 return; 1631 /* 1632 * Disable and clear all IDMA windows, revoke protection for all channels 1633 */ 1634 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1635 1636 idma_bare_write(base, i, 1); 1637 win_idma_br_write(base, i, 0); 1638 win_idma_sz_write(base, i, 0); 1639 if (win_idma_can_remap(i) == 1) 1640 win_idma_har_write(base, i, 0); 1641 } 1642 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1643 win_idma_cap_write(base, i, 0); 1644 1645 /* 1646 * Set up access to all active DRAM banks 1647 */ 1648 for (i = 0; i < MV_WIN_DDR_MAX; i++) 1649 if (ddr_is_active(i)) { 1650 br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); 1651 sz = ((ddr_size(i) - 1) & 0xffff0000); 1652 1653 /* Place DDR entries in non-remapped windows */ 1654 for (j = 0; j < MV_WIN_IDMA_MAX; j++) 1655 if (win_idma_can_remap(j) != 1 && 1656 idma_bare_read(base, j) == 1) { 1657 1658 /* Configure window */ 1659 win_idma_br_write(base, j, br); 1660 win_idma_sz_write(base, j, sz); 1661 1662 /* Set protection RW on all channels */ 1663 idma_set_prot(base, j, 0x3); 1664 1665 /* Enable window */ 1666 idma_bare_write(base, j, 0); 1667 break; 1668 } 1669 } 1670 1671 /* 1672 * Remaining targets -- from statically defined table 1673 */ 1674 for (i = 0; i < idma_wins_no; i++) 1675 if (idma_wins[i].target > 0) { 1676 br = (idma_wins[i].base & 0xffff0000) | 1677 (idma_wins[i].attr << 8) | idma_wins[i].target; 1678 sz = ((idma_wins[i].size - 1) & 0xffff0000); 1679 1680 /* Set the first free IDMA window */ 1681 for (j = 0; j < MV_WIN_IDMA_MAX; j++) { 1682 if (idma_bare_read(base, j) == 0) 1683 continue; 1684 1685 /* Configure window */ 1686 win_idma_br_write(base, j, br); 1687 win_idma_sz_write(base, j, sz); 1688 if (win_idma_can_remap(j) && 1689 idma_wins[j].remap >= 0) 1690 win_idma_har_write(base, j, 1691 idma_wins[j].remap); 1692 1693 /* Set protection RW on all channels */ 1694 idma_set_prot(base, j, 0x3); 1695 1696 /* Enable window */ 1697 idma_bare_write(base, j, 0); 1698 break; 1699 } 1700 } 1701 } 1702 1703 int 1704 decode_win_idma_valid(void) 1705 { 1706 const struct decode_win *wintab; 1707 int c, i, j, rv; 1708 uint32_t b, e, s; 1709 1710 if (idma_wins_no > MV_WIN_IDMA_MAX) { 1711 printf("IDMA windows: too many entries: %d\n", idma_wins_no); 1712 return (0); 1713 } 1714 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 1715 if (ddr_is_active(i)) 1716 c++; 1717 1718 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { 1719 printf("IDMA windows: too many entries: %d, available: %d\n", 1720 idma_wins_no, MV_WIN_IDMA_MAX - c); 1721 return (0); 1722 } 1723 1724 wintab = idma_wins; 1725 rv = 1; 1726 for (i = 0; i < idma_wins_no; i++, wintab++) { 1727 1728 if (wintab->target == 0) { 1729 printf("IDMA window#%d: DDR target window is not " 1730 "supposed to be reprogrammed!\n", i); 1731 rv = 0; 1732 } 1733 1734 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 1735 printf("IDMA window#%d: not capable of remapping, but " 1736 "val 0x%08x defined\n", i, wintab->remap); 1737 rv = 0; 1738 } 1739 1740 s = wintab->size; 1741 b = wintab->base; 1742 e = b + s - 1; 1743 if (s > (0xFFFFFFFF - b + 1)) { 1744 /* XXX this boundary check should account for 64bit and 1745 * remapping.. */ 1746 printf("IDMA window#%d: no space for size 0x%08x at " 1747 "0x%08x\n", i, s, b); 1748 rv = 0; 1749 continue; 1750 } 1751 1752 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); 1753 if (j >= 0) { 1754 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " 1755 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 1756 idma_wins[j].base, 1757 idma_wins[j].base + idma_wins[j].size - 1); 1758 rv = 0; 1759 } 1760 } 1761 1762 return (rv); 1763 } 1764 1765 void 1766 decode_win_idma_dump(u_long base) 1767 { 1768 int i; 1769 1770 if (pm_is_disabled(CPU_PM_CTRL_IDMA)) 1771 return; 1772 1773 for (i = 0; i < MV_WIN_IDMA_MAX; i++) { 1774 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, 1775 win_idma_br_read(base, i), win_idma_sz_read(base, i)); 1776 1777 if (win_idma_can_remap(i)) 1778 printf(", ha 0x%08x", win_idma_har_read(base, i)); 1779 1780 printf("\n"); 1781 } 1782 for (i = 0; i < MV_IDMA_CHAN_MAX; i++) 1783 printf("IDMA channel#%d: ap 0x%08x\n", i, 1784 win_idma_cap_read(base, i)); 1785 printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); 1786 } 1787 #else 1788 1789 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ 1790 int 1791 decode_win_idma_valid(void) 1792 { 1793 1794 return (1); 1795 } 1796 1797 void 1798 decode_win_idma_setup(u_long base) 1799 { 1800 } 1801 1802 void 1803 decode_win_idma_dump(u_long base) 1804 { 1805 } 1806 #endif 1807 1808 /************************************************************************** 1809 * XOR windows routines 1810 **************************************************************************/ 1811 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 1812 static int 1813 xor_ctrl_read(u_long base, int i, int c, int e) 1814 { 1815 uint32_t v; 1816 v = win_xor_ctrl_read(base, c, e); 1817 v &= (1 << i); 1818 1819 return (v >> i); 1820 } 1821 1822 static void 1823 xor_ctrl_write(u_long base, int i, int c, int e, int val) 1824 { 1825 uint32_t v; 1826 1827 v = win_xor_ctrl_read(base, c, e); 1828 v &= ~(1 << i); 1829 v |= (val << i); 1830 win_xor_ctrl_write(base, c, e, v); 1831 } 1832 1833 /* 1834 * Set channel protection 'val' for window 'w' on channel 'c' 1835 */ 1836 static void 1837 xor_chan_write(u_long base, int c, int e, int w, int val) 1838 { 1839 uint32_t v; 1840 1841 v = win_xor_ctrl_read(base, c, e); 1842 v &= ~(0x3 << (w * 2 + 16)); 1843 v |= (val << (w * 2 + 16)); 1844 win_xor_ctrl_write(base, c, e, v); 1845 } 1846 1847 /* 1848 * Set protection 'val' on all channels for window 'w' on engine 'e' 1849 */ 1850 static void 1851 xor_set_prot(u_long base, int w, int e, int val) 1852 { 1853 int c; 1854 1855 for (c = 0; c < MV_XOR_CHAN_MAX; c++) 1856 xor_chan_write(base, c, e, w, val); 1857 } 1858 1859 static int 1860 win_xor_can_remap(int i) 1861 { 1862 1863 /* XOR decode windows 0-3 have remap capability */ 1864 if (i < 4) 1865 return (1); 1866 1867 return (0); 1868 } 1869 1870 static int 1871 xor_max_eng(void) 1872 { 1873 uint32_t dev, rev; 1874 1875 soc_id(&dev, &rev); 1876 switch (dev) { 1877 case MV_DEV_88F6281: 1878 case MV_DEV_88F6282: 1879 case MV_DEV_MV78130: 1880 case MV_DEV_MV78160: 1881 case MV_DEV_MV78230: 1882 case MV_DEV_MV78260: 1883 case MV_DEV_MV78460: 1884 return (2); 1885 case MV_DEV_MV78100: 1886 case MV_DEV_MV78100_Z0: 1887 return (1); 1888 default: 1889 return (0); 1890 } 1891 } 1892 1893 static void 1894 xor_active_dram(u_long base, int c, int e, int *window) 1895 { 1896 uint32_t br, sz; 1897 int i, m, w; 1898 1899 /* 1900 * Set up access to all active DRAM banks 1901 */ 1902 m = xor_max_eng(); 1903 for (i = 0; i < m; i++) 1904 if (ddr_is_active(i)) { 1905 br = ddr_base(i) | (ddr_attr(i) << 8) | 1906 ddr_target(i); 1907 sz = ((ddr_size(i) - 1) & 0xffff0000); 1908 1909 /* Place DDR entries in non-remapped windows */ 1910 for (w = 0; w < MV_WIN_XOR_MAX; w++) 1911 if (win_xor_can_remap(w) != 1 && 1912 (xor_ctrl_read(base, w, c, e) == 0) && 1913 w > *window) { 1914 /* Configure window */ 1915 win_xor_br_write(base, w, e, br); 1916 win_xor_sz_write(base, w, e, sz); 1917 1918 /* Set protection RW on all channels */ 1919 xor_set_prot(base, w, e, 0x3); 1920 1921 /* Enable window */ 1922 xor_ctrl_write(base, w, c, e, 1); 1923 (*window)++; 1924 break; 1925 } 1926 } 1927 } 1928 1929 void 1930 decode_win_xor_setup(u_long base) 1931 { 1932 uint32_t br, sz; 1933 int i, j, z, e = 1, m, window; 1934 1935 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 1936 return; 1937 1938 /* 1939 * Disable and clear all XOR windows, revoke protection for all 1940 * channels 1941 */ 1942 m = xor_max_eng(); 1943 for (j = 0; j < m; j++, e--) { 1944 1945 /* Number of non-remaped windows */ 1946 window = MV_XOR_NON_REMAP - 1; 1947 1948 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 1949 win_xor_br_write(base, i, e, 0); 1950 win_xor_sz_write(base, i, e, 0); 1951 } 1952 1953 if (win_xor_can_remap(i) == 1) 1954 win_xor_har_write(base, i, e, 0); 1955 1956 for (i = 0; i < MV_XOR_CHAN_MAX; i++) { 1957 win_xor_ctrl_write(base, i, e, 0); 1958 xor_active_dram(base, i, e, &window); 1959 } 1960 1961 /* 1962 * Remaining targets -- from a statically defined table 1963 */ 1964 for (i = 0; i < xor_wins_no; i++) 1965 if (xor_wins[i].target > 0) { 1966 br = (xor_wins[i].base & 0xffff0000) | 1967 (xor_wins[i].attr << 8) | 1968 xor_wins[i].target; 1969 sz = ((xor_wins[i].size - 1) & 0xffff0000); 1970 1971 /* Set the first free XOR window */ 1972 for (z = 0; z < MV_WIN_XOR_MAX; z++) { 1973 if (xor_ctrl_read(base, z, 0, e) && 1974 xor_ctrl_read(base, z, 1, e)) 1975 continue; 1976 1977 /* Configure window */ 1978 win_xor_br_write(base, z, e, br); 1979 win_xor_sz_write(base, z, e, sz); 1980 if (win_xor_can_remap(z) && 1981 xor_wins[z].remap >= 0) 1982 win_xor_har_write(base, z, e, 1983 xor_wins[z].remap); 1984 1985 /* Set protection RW on all channels */ 1986 xor_set_prot(base, z, e, 0x3); 1987 1988 /* Enable window */ 1989 xor_ctrl_write(base, z, 0, e, 1); 1990 xor_ctrl_write(base, z, 1, e, 1); 1991 break; 1992 } 1993 } 1994 } 1995 } 1996 1997 int 1998 decode_win_xor_valid(void) 1999 { 2000 const struct decode_win *wintab; 2001 int c, i, j, rv; 2002 uint32_t b, e, s; 2003 2004 if (xor_wins_no > MV_WIN_XOR_MAX) { 2005 printf("XOR windows: too many entries: %d\n", xor_wins_no); 2006 return (0); 2007 } 2008 for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) 2009 if (ddr_is_active(i)) 2010 c++; 2011 2012 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { 2013 printf("XOR windows: too many entries: %d, available: %d\n", 2014 xor_wins_no, MV_WIN_IDMA_MAX - c); 2015 return (0); 2016 } 2017 2018 wintab = xor_wins; 2019 rv = 1; 2020 for (i = 0; i < xor_wins_no; i++, wintab++) { 2021 2022 if (wintab->target == 0) { 2023 printf("XOR window#%d: DDR target window is not " 2024 "supposed to be reprogrammed!\n", i); 2025 rv = 0; 2026 } 2027 2028 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { 2029 printf("XOR window#%d: not capable of remapping, but " 2030 "val 0x%08x defined\n", i, wintab->remap); 2031 rv = 0; 2032 } 2033 2034 s = wintab->size; 2035 b = wintab->base; 2036 e = b + s - 1; 2037 if (s > (0xFFFFFFFF - b + 1)) { 2038 /* 2039 * XXX this boundary check should account for 64bit 2040 * and remapping.. 2041 */ 2042 printf("XOR window#%d: no space for size 0x%08x at " 2043 "0x%08x\n", i, s, b); 2044 rv = 0; 2045 continue; 2046 } 2047 2048 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); 2049 if (j >= 0) { 2050 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " 2051 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, 2052 xor_wins[j].base, 2053 xor_wins[j].base + xor_wins[j].size - 1); 2054 rv = 0; 2055 } 2056 } 2057 2058 return (rv); 2059 } 2060 2061 void 2062 decode_win_xor_dump(u_long base) 2063 { 2064 int i, j; 2065 int e = 1; 2066 2067 if (pm_is_disabled(CPU_PM_CTRL_XOR)) 2068 return; 2069 2070 for (j = 0; j < xor_max_eng(); j++, e--) { 2071 for (i = 0; i < MV_WIN_XOR_MAX; i++) { 2072 printf("XOR window#%d: b 0x%08x, s 0x%08x", i, 2073 win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); 2074 2075 if (win_xor_can_remap(i)) 2076 printf(", ha 0x%08x", win_xor_har_read(base, i, e)); 2077 2078 printf("\n"); 2079 } 2080 for (i = 0; i < MV_XOR_CHAN_MAX; i++) 2081 printf("XOR control#%d: 0x%08x\n", i, 2082 win_xor_ctrl_read(base, i, e)); 2083 } 2084 } 2085 2086 #else 2087 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ 2088 static int 2089 decode_win_xor_valid(void) 2090 { 2091 2092 return (1); 2093 } 2094 2095 static void 2096 decode_win_xor_setup(u_long base) 2097 { 2098 } 2099 2100 static void 2101 decode_win_xor_dump(u_long base) 2102 { 2103 } 2104 #endif 2105 2106 /************************************************************************** 2107 * SATA windows routines 2108 **************************************************************************/ 2109 static void 2110 decode_win_sata_setup(u_long base) 2111 { 2112 uint32_t cr, br; 2113 int i, j; 2114 2115 if (pm_is_disabled(CPU_PM_CTRL_SATA)) 2116 return; 2117 2118 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2119 win_sata_cr_write(base, i, 0); 2120 win_sata_br_write(base, i, 0); 2121 } 2122 2123 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2124 if (ddr_is_active(i)) { 2125 cr = ((ddr_size(i) - 1) & 0xffff0000) | 2126 (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; 2127 br = ddr_base(i); 2128 2129 /* Use the first available SATA window */ 2130 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2131 if ((win_sata_cr_read(base, j) & 1) != 0) 2132 continue; 2133 2134 win_sata_br_write(base, j, br); 2135 win_sata_cr_write(base, j, cr); 2136 break; 2137 } 2138 } 2139 } 2140 2141 #ifdef SOC_MV_ARMADA38X 2142 /* 2143 * Configure AHCI decoding windows 2144 */ 2145 static void 2146 decode_win_ahci_setup(u_long base) 2147 { 2148 uint32_t br, cr, sz; 2149 int i, j; 2150 2151 for (i = 0; i < MV_WIN_SATA_MAX; i++) { 2152 win_sata_cr_write(base, i, 0); 2153 win_sata_br_write(base, i, 0); 2154 win_sata_sz_write(base, i, 0); 2155 } 2156 2157 for (i = 0; i < MV_WIN_DDR_MAX; i++) { 2158 if (ddr_is_active(i)) { 2159 cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2160 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2161 IO_WIN_ENA_MASK; 2162 br = ddr_base(i); 2163 sz = (ddr_size(i) - 1) & 2164 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); 2165 2166 /* Use first available SATA window */ 2167 for (j = 0; j < MV_WIN_SATA_MAX; j++) { 2168 if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) 2169 continue; 2170 2171 /* BASE is set to DRAM base (0x00000000) */ 2172 win_sata_br_write(base, j, br); 2173 /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ 2174 win_sata_cr_write(base, j, cr); 2175 /* SIZE is set to 16MB - max value */ 2176 win_sata_sz_write(base, j, sz); 2177 break; 2178 } 2179 } 2180 } 2181 } 2182 2183 static void 2184 decode_win_ahci_dump(u_long base) 2185 { 2186 int i; 2187 2188 for (i = 0; i < MV_WIN_SATA_MAX; i++) 2189 printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, 2190 win_sata_cr_read(base, i), win_sata_br_read(base, i), 2191 win_sata_sz_read(base,i)); 2192 } 2193 2194 #else 2195 /* 2196 * Provide dummy functions to satisfy the build 2197 * for SoC's not equipped with AHCI controller 2198 */ 2199 static void 2200 decode_win_ahci_setup(u_long base) 2201 { 2202 } 2203 2204 static void 2205 decode_win_ahci_dump(u_long base) 2206 { 2207 } 2208 #endif 2209 2210 static int 2211 decode_win_sata_valid(void) 2212 { 2213 uint32_t dev, rev; 2214 2215 soc_id(&dev, &rev); 2216 if (dev == MV_DEV_88F5281) 2217 return (1); 2218 2219 return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); 2220 } 2221 2222 static void 2223 decode_win_sdhci_setup(u_long base) 2224 { 2225 uint32_t cr, br; 2226 int i, j; 2227 2228 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { 2229 win_sdhci_cr_write(base, i, 0); 2230 win_sdhci_br_write(base, i, 0); 2231 } 2232 2233 for (i = 0; i < MV_WIN_DDR_MAX; i++) 2234 if (ddr_is_active(i)) { 2235 br = ddr_base(i); 2236 cr = (((ddr_size(i) - 1) & 2237 (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | 2238 (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | 2239 (ddr_target(i) << IO_WIN_TGT_SHIFT) | 2240 IO_WIN_ENA_MASK); 2241 2242 /* Use the first available SDHCI window */ 2243 for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { 2244 if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) 2245 continue; 2246 2247 win_sdhci_cr_write(base, j, cr); 2248 win_sdhci_br_write(base, j, br); 2249 break; 2250 } 2251 } 2252 } 2253 2254 static void 2255 decode_win_sdhci_dump(u_long base) 2256 { 2257 int i; 2258 2259 for (i = 0; i < MV_WIN_SDHCI_MAX; i++) 2260 printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, 2261 win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); 2262 } 2263 2264 static int 2265 decode_win_sdhci_valid(void) 2266 { 2267 2268 #ifdef SOC_MV_ARMADA38X 2269 return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); 2270 #endif 2271 2272 /* Satisfy platforms not equipped with this controller. */ 2273 return (1); 2274 } 2275 2276 /************************************************************************** 2277 * FDT parsing routines. 2278 **************************************************************************/ 2279 2280 static int 2281 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, 2282 int *tuplesize) 2283 { 2284 phandle_t node; 2285 pcell_t addr_cells, par_addr_cells, size_cells; 2286 int len, tuple_size, tuples_count; 2287 2288 node = OF_finddevice(nodename); 2289 if (node == -1) 2290 return (EINVAL); 2291 2292 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 2293 return (ENXIO); 2294 2295 par_addr_cells = fdt_parent_addr_cells(node); 2296 if (par_addr_cells > 2) 2297 return (ERANGE); 2298 2299 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 2300 size_cells); 2301 2302 /* Note the OF_getprop_alloc() cannot be used at this early stage. */ 2303 len = OF_getprop(node, "ranges", buf, size); 2304 2305 /* 2306 * XXX this does not handle the empty 'ranges;' case, which is 2307 * legitimate and should be allowed. 2308 */ 2309 tuples_count = len / tuple_size; 2310 if (tuples_count <= 0) 2311 return (ERANGE); 2312 2313 if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) 2314 return (ERANGE); 2315 2316 *tuples = tuples_count; 2317 *tuplesize = tuple_size; 2318 return (0); 2319 } 2320 2321 static int 2322 win_cpu_from_dt(void) 2323 { 2324 pcell_t ranges[48]; 2325 phandle_t node; 2326 int i, entry_size, err, t, tuple_size, tuples; 2327 u_long sram_base, sram_size; 2328 2329 t = 0; 2330 /* Retrieve 'ranges' property of '/localbus' node. */ 2331 if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), 2332 &tuples, &tuple_size)) == 0) { 2333 /* 2334 * Fill CPU decode windows table. 2335 */ 2336 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); 2337 2338 entry_size = tuple_size / sizeof(pcell_t); 2339 cpu_wins_no = tuples; 2340 2341 /* Check range */ 2342 if (tuples > nitems(cpu_win_tbl)) { 2343 debugf("too many tuples to fit into cpu_win_tbl\n"); 2344 return (ENOMEM); 2345 } 2346 2347 for (i = 0, t = 0; t < tuples; i += entry_size, t++) { 2348 cpu_win_tbl[t].target = 1; 2349 cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); 2350 cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); 2351 cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); 2352 cpu_win_tbl[t].remap = ~0; 2353 debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " 2354 "size = 0x%0x remap = 0x%0x\n", 2355 cpu_win_tbl[t].target, 2356 cpu_win_tbl[t].attr, cpu_win_tbl[t].base, 2357 cpu_win_tbl[t].size, cpu_win_tbl[t].remap); 2358 } 2359 } 2360 2361 /* 2362 * Retrieve CESA SRAM data. 2363 */ 2364 if ((node = OF_finddevice("sram")) != -1) 2365 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) 2366 goto moveon; 2367 2368 if ((node = OF_finddevice("/")) == 0) 2369 return (ENXIO); 2370 2371 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) 2372 /* SRAM block is not always present. */ 2373 return (0); 2374 moveon: 2375 sram_base = sram_size = 0; 2376 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2377 return (EINVAL); 2378 2379 /* Check range */ 2380 if (t >= nitems(cpu_win_tbl)) { 2381 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2382 return (ENOMEM); 2383 } 2384 2385 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2386 #ifdef SOC_MV_ARMADA38X 2387 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); 2388 #else 2389 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2390 #endif 2391 cpu_win_tbl[t].base = sram_base; 2392 cpu_win_tbl[t].size = sram_size; 2393 cpu_win_tbl[t].remap = ~0; 2394 cpu_wins_no++; 2395 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2396 2397 /* Check if there is a second CESA node */ 2398 while ((node = OF_peer(node)) != 0) { 2399 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { 2400 if (fdt_regsize(node, &sram_base, &sram_size) != 0) 2401 return (EINVAL); 2402 break; 2403 } 2404 } 2405 2406 if (node == 0) 2407 return (0); 2408 2409 t++; 2410 if (t >= nitems(cpu_win_tbl)) { 2411 debugf("cannot fit CESA tuple into cpu_win_tbl\n"); 2412 return (ENOMEM); 2413 } 2414 2415 /* Configure window for CESA1 */ 2416 cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; 2417 cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); 2418 cpu_win_tbl[t].base = sram_base; 2419 cpu_win_tbl[t].size = sram_size; 2420 cpu_win_tbl[t].remap = ~0; 2421 cpu_wins_no++; 2422 debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); 2423 2424 return (0); 2425 } 2426 2427 static int 2428 fdt_win_process(phandle_t child) 2429 { 2430 int i; 2431 struct soc_node_spec *soc_node; 2432 int addr_cells, size_cells; 2433 pcell_t reg[8]; 2434 u_long size, base; 2435 2436 for (i = 0; soc_nodes[i].compat != NULL; i++) { 2437 2438 soc_node = &soc_nodes[i]; 2439 2440 /* Setup only for enabled devices */ 2441 if (ofw_bus_node_status_okay(child) == 0) 2442 continue; 2443 2444 if (!ofw_bus_node_is_compatible(child, soc_node->compat)) 2445 continue; 2446 2447 if (fdt_addrsize_cells(OF_parent(child), &addr_cells, 2448 &size_cells)) 2449 return (ENXIO); 2450 2451 if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) 2452 return (ENOMEM); 2453 2454 if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) 2455 return (EINVAL); 2456 2457 if (addr_cells <= 2) 2458 base = fdt_data_get(®[0], addr_cells); 2459 else 2460 base = fdt_data_get(®[addr_cells - 2], 2); 2461 size = fdt_data_get(®[addr_cells], size_cells); 2462 2463 base = (base & 0x000fffff) | fdt_immr_va; 2464 if (soc_node->decode_handler != NULL) 2465 soc_node->decode_handler(base); 2466 else 2467 return (ENXIO); 2468 2469 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) 2470 soc_node->dump_handler(base); 2471 } 2472 2473 return (0); 2474 } 2475 static int 2476 fdt_win_setup(void) 2477 { 2478 phandle_t node, child, sb; 2479 phandle_t child_pci; 2480 int err; 2481 2482 sb = 0; 2483 node = OF_finddevice("/"); 2484 if (node == -1) 2485 panic("fdt_win_setup: no root node"); 2486 2487 /* Allow for coherent transactions on the A38x MBUS */ 2488 if (ofw_bus_node_is_compatible(node, "marvell,armada380")) 2489 platform_io_coherent = true; 2490 2491 /* 2492 * Traverse through all children of root and simple-bus nodes. 2493 * For each found device retrieve decode windows data (if applicable). 2494 */ 2495 child = OF_child(node); 2496 while (child != 0) { 2497 /* Lookup for callback and run */ 2498 err = fdt_win_process(child); 2499 if (err != 0) 2500 return (err); 2501 2502 /* Process Marvell Armada-XP/38x PCIe controllers */ 2503 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { 2504 child_pci = OF_child(child); 2505 while (child_pci != 0) { 2506 err = fdt_win_process(child_pci); 2507 if (err != 0) 2508 return (err); 2509 2510 child_pci = OF_peer(child_pci); 2511 } 2512 } 2513 2514 /* 2515 * Once done with root-level children let's move down to 2516 * simple-bus and its children. 2517 */ 2518 child = OF_peer(child); 2519 if ((child == 0) && (node == OF_finddevice("/"))) { 2520 sb = node = fdt_find_compatible(node, "simple-bus", 0); 2521 if (node == 0) 2522 return (ENXIO); 2523 child = OF_child(node); 2524 } 2525 /* 2526 * Next, move one more level down to internal-regs node (if 2527 * it is present) and its children. This node also have 2528 * "simple-bus" compatible. 2529 */ 2530 if ((child == 0) && (node == sb)) { 2531 node = fdt_find_compatible(node, "simple-bus", 0); 2532 if (node == 0) 2533 return (0); 2534 child = OF_child(node); 2535 } 2536 } 2537 2538 return (0); 2539 } 2540 2541 static void 2542 fdt_fixup_busfreq(phandle_t root) 2543 { 2544 phandle_t sb; 2545 pcell_t freq; 2546 2547 freq = cpu_to_fdt32(get_tclk()); 2548 2549 /* 2550 * Fix bus speed in cpu node 2551 */ 2552 if ((sb = OF_finddevice("cpu")) != 0) 2553 if (fdt_is_compatible_strict(sb, "ARM,88VS584")) 2554 OF_setprop(sb, "bus-frequency", (void *)&freq, 2555 sizeof(freq)); 2556 2557 /* 2558 * This fixup sets the simple-bus bus-frequency property. 2559 */ 2560 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) 2561 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); 2562 } 2563 2564 static void 2565 fdt_fixup_ranges(phandle_t root) 2566 { 2567 phandle_t node; 2568 pcell_t par_addr_cells, addr_cells, size_cells; 2569 pcell_t ranges[3], reg[2], *rangesptr; 2570 int len, tuple_size, tuples_count; 2571 uint32_t base; 2572 2573 /* Fix-up SoC ranges according to real fdt_immr_pa */ 2574 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { 2575 if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && 2576 (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { 2577 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2578 addr_cells + size_cells); 2579 len = OF_getprop(node, "ranges", ranges, 2580 sizeof(ranges)); 2581 tuples_count = len / tuple_size; 2582 /* Unexpected settings are not supported */ 2583 if (tuples_count != 1) 2584 goto fixup_failed; 2585 2586 rangesptr = &ranges[0]; 2587 rangesptr += par_addr_cells; 2588 base = fdt_data_get((void *)rangesptr, addr_cells); 2589 *rangesptr = cpu_to_fdt32(fdt_immr_pa); 2590 if (OF_setprop(node, "ranges", (void *)&ranges[0], 2591 sizeof(ranges)) < 0) 2592 goto fixup_failed; 2593 } 2594 } 2595 2596 /* Fix-up PCIe reg according to real PCIe registers' PA */ 2597 if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { 2598 if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 2599 &size_cells) == 0) { 2600 tuple_size = sizeof(pcell_t) * (par_addr_cells + 2601 size_cells); 2602 len = OF_getprop(node, "reg", reg, sizeof(reg)); 2603 tuples_count = len / tuple_size; 2604 /* Unexpected settings are not supported */ 2605 if (tuples_count != 1) 2606 goto fixup_failed; 2607 2608 base = fdt_data_get((void *)®[0], par_addr_cells); 2609 base &= ~0xFF000000; 2610 base |= fdt_immr_pa; 2611 reg[0] = cpu_to_fdt32(base); 2612 if (OF_setprop(node, "reg", (void *)®[0], 2613 sizeof(reg)) < 0) 2614 goto fixup_failed; 2615 } 2616 } 2617 /* Fix-up succeeded. May return and continue */ 2618 return; 2619 2620 fixup_failed: 2621 while (1) { 2622 /* 2623 * In case of any error while fixing ranges just hang. 2624 * 1. No message can be displayed yet since console 2625 * is not initialized. 2626 * 2. Going further will cause failure on bus_space_map() 2627 * relying on the wrong ranges or data abort when 2628 * accessing PCIe registers. 2629 */ 2630 } 2631 } 2632 2633 struct fdt_fixup_entry fdt_fixup_table[] = { 2634 { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, 2635 { "mrvl,DB-78460", &fdt_fixup_busfreq }, 2636 { "mrvl,DB-78460", &fdt_fixup_ranges }, 2637 { NULL, NULL } 2638 }; 2639 2640 #ifndef INTRNG 2641 static int 2642 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, 2643 int *pol) 2644 { 2645 2646 if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && 2647 !ofw_bus_node_is_compatible(node, "mrvl,mpic")) 2648 return (ENXIO); 2649 2650 *interrupt = fdt32_to_cpu(intr[0]); 2651 *trig = INTR_TRIGGER_CONFORM; 2652 *pol = INTR_POLARITY_CONFORM; 2653 2654 return (0); 2655 } 2656 2657 fdt_pic_decode_t fdt_pic_table[] = { 2658 #ifdef SOC_MV_ARMADA38X 2659 &gic_decode_fdt, 2660 #endif 2661 &fdt_pic_decode_ic, 2662 NULL 2663 }; 2664 #endif 2665 2666 uint64_t 2667 get_sar_value(void) 2668 { 2669 uint32_t sar_low, sar_high; 2670 2671 #if defined(SOC_MV_ARMADAXP) 2672 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2673 SAMPLE_AT_RESET_HI); 2674 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2675 SAMPLE_AT_RESET_LO); 2676 #elif defined(SOC_MV_ARMADA38X) 2677 sar_high = 0; 2678 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 2679 SAMPLE_AT_RESET); 2680 #else 2681 /* 2682 * TODO: Add getting proper values for other SoC configurations 2683 */ 2684 sar_high = 0; 2685 sar_low = 0; 2686 #endif 2687 2688 return (((uint64_t)sar_high << 32) | sar_low); 2689 } 2690