xref: /freebsd/sys/arm/mv/mv_armv7_machdep.c (revision f7c32ed617858bcd22f8d1b03199099d50125721)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2017 Semihalf.
5  * Copyright (c) 1994-1998 Mark Brinicombe.
6  * Copyright (c) 1994 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *      This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
39  */
40 
41 #include "opt_ddb.h"
42 #include "opt_platform.h"
43 
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
46 
47 #define _ARM32_BUS_DMA_PRIVATE
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/bus.h>
51 #include <sys/devmap.h>
52 #include <sys/kernel.h>
53 
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56 
57 #include <arm/arm/mpcore_timervar.h>
58 #include <arm/arm/nexusvar.h>
59 
60 #include <machine/bus.h>
61 #include <machine/fdt.h>
62 #include <machine/machdep.h>
63 #include <machine/platform.h>
64 #include <machine/platformvar.h>
65 #include <machine/pte-v6.h>
66 
67 #include <arm/mv/mvreg.h>
68 #include <arm/mv/mvvar.h>
69 #include <arm/mv/mvwin.h>
70 
71 #include <dev/fdt/fdt_common.h>
72 #include <dev/ofw/ofw_bus_subr.h>
73 
74 #include "opt_platform.h"
75 #include "platform_if.h"
76 
77 #if defined(SOC_MV_ARMADA38X)
78 #include "platform_pl310_if.h"
79 #include "armada38x/armada38x_pl310.h"
80 #endif
81 
82 static int platform_mpp_init(void);
83 int armada38x_win_set_iosync_barrier(void);
84 int armada38x_scu_enable(void);
85 int armada38x_open_bootrom_win(void);
86 int armada38x_mbus_optimization(void);
87 
88 static vm_offset_t mv_platform_lastaddr(platform_t plate);
89 static int mv_platform_probe_and_attach(platform_t plate);
90 static void mv_platform_gpio_init(platform_t plate);
91 static void mv_cpu_reset(platform_t plat);
92 
93 static void mv_a38x_platform_late_init(platform_t plate);
94 static int mv_a38x_platform_devmap_init(platform_t plate);
95 static void mv_axp_platform_late_init(platform_t plate);
96 static int mv_axp_platform_devmap_init(platform_t plate);
97 
98 void armadaxp_init_coher_fabric(void);
99 void armadaxp_l2_init(void);
100 
101 #ifdef SMP
102 void mv_a38x_platform_mp_setmaxid(platform_t plate);
103 void mv_a38x_platform_mp_start_ap(platform_t plate);
104 void mv_axp_platform_mp_setmaxid(platform_t plate);
105 void mv_axp_platform_mp_start_ap(platform_t plate);
106 #endif
107 
108 #define MPP_PIN_MAX		68
109 #define MPP_PIN_CELLS		2
110 #define MPP_PINS_PER_REG	8
111 #define MPP_SEL(pin,func)	(((func) & 0xf) <<		\
112     (((pin) % MPP_PINS_PER_REG) * 4))
113 
114 static void
115 mv_busdma_tag_init(void *arg __unused)
116 {
117 	phandle_t node;
118 	bus_dma_tag_t dmat;
119 
120 	/*
121 	 * If this platform has coherent DMA, create the parent DMA tag to pass
122 	 * down the coherent flag to all busses and devices on the platform,
123 	 * otherwise return without doing anything. By default create tag
124 	 * for all A38x-based platforms only.
125 	 */
126 	if ((node = OF_finddevice("/")) == -1){
127 		printf("no tree\n");
128 		return;
129 	}
130 
131 	if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0)
132 		return;
133 
134 	bus_dma_tag_create(NULL,	/* No parent tag */
135 	    1, 0,			/* alignment, bounds */
136 	    BUS_SPACE_MAXADDR,		/* lowaddr */
137 	    BUS_SPACE_MAXADDR,		/* highaddr */
138 	    NULL, NULL,			/* filter, filterarg */
139 	    BUS_SPACE_MAXSIZE,		/* maxsize */
140 	    BUS_SPACE_UNRESTRICTED,	/* nsegments */
141 	    BUS_SPACE_MAXSIZE,		/* maxsegsize */
142 	    BUS_DMA_COHERENT,		/* flags */
143 	    NULL, NULL,			/* lockfunc, lockarg */
144 	    &dmat);
145 
146 	nexus_set_dma_tag(dmat);
147 
148 }
149 SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL);
150 
151 static int
152 platform_mpp_init(void)
153 {
154 	pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
155 	int mpp[MPP_PIN_MAX];
156 	uint32_t ctrl_val, ctrl_offset;
157 	pcell_t reg[4];
158 	u_long start, size;
159 	phandle_t node;
160 	pcell_t pin_cells, *pinmap_ptr, pin_count;
161 	ssize_t len;
162 	int par_addr_cells, par_size_cells;
163 	int tuple_size, tuples, rv, pins, i, j;
164 	int mpp_pin, mpp_function;
165 
166 	/*
167 	 * Try to access the MPP node directly i.e. through /aliases/mpp.
168 	 */
169 	if ((node = OF_finddevice("mpp")) != -1)
170 		if (ofw_bus_node_is_compatible(node, "mrvl,mpp"))
171 			goto moveon;
172 	/*
173 	 * Find the node the long way.
174 	 */
175 	if ((node = OF_finddevice("/")) == -1)
176 		return (ENXIO);
177 
178 	if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
179 		return (ENXIO);
180 
181 	if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
182 		/*
183 		 * No MPP node. Fall back to how MPP got set by the
184 		 * first-stage loader and try to continue booting.
185 		 */
186 		return (0);
187 moveon:
188 	/*
189 	 * Process 'reg' prop.
190 	 */
191 	if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
192 	    &par_size_cells)) != 0)
193 		return(ENXIO);
194 
195 	tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
196 	len = OF_getprop(node, "reg", reg, sizeof(reg));
197 	tuples = len / tuple_size;
198 	if (tuple_size <= 0)
199 		return (EINVAL);
200 
201 	rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
202 	    &start, &size);
203 	if (rv != 0)
204 		return (rv);
205 	start += fdt_immr_va;
206 
207 	/*
208 	 * Process 'pin-count' and 'pin-map' props.
209 	 */
210 	if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
211 		return (ENXIO);
212 	if (pin_count > MPP_PIN_MAX)
213 		return (ERANGE);
214 
215 	if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
216 		pin_cells = MPP_PIN_CELLS;
217 	if (pin_cells > MPP_PIN_CELLS)
218 		return (ERANGE);
219 	tuple_size = sizeof(pcell_t) * pin_cells;
220 
221 	bzero(pinmap, sizeof(pinmap));
222 	len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap));
223 	if (len <= 0)
224 		return (ERANGE);
225 	if (len % tuple_size)
226 		return (ERANGE);
227 	pins = len / tuple_size;
228 	if (pins > pin_count)
229 		return (ERANGE);
230 	/*
231 	 * Fill out a "mpp[pin] => function" table. All pins unspecified in
232 	 * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
233 	 */
234 	bzero(mpp, sizeof(mpp));
235 	pinmap_ptr = pinmap;
236 	for (i = 0; i < pins; i++) {
237 		mpp_pin = *pinmap_ptr;
238 		mpp_function = *(pinmap_ptr + 1);
239 		mpp[mpp_pin] = mpp_function;
240 		pinmap_ptr += pin_cells;
241 	}
242 
243 	/*
244 	 * Prepare and program MPP control register values.
245 	 */
246 	ctrl_offset = 0;
247 	for (i = 0; i < pin_count;) {
248 		ctrl_val = 0;
249 
250 		for (j = 0; j < MPP_PINS_PER_REG; j++) {
251 			if (i + j == pin_count - 1)
252 				break;
253 			ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
254 		}
255 		i += MPP_PINS_PER_REG;
256 		bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
257 		    ctrl_val);
258 
259 		ctrl_offset += 4;
260 	}
261 
262 	return (0);
263 }
264 
265 static vm_offset_t
266 mv_platform_lastaddr(platform_t plat)
267 {
268 
269 	return (fdt_immr_va);
270 }
271 
272 static int
273 mv_platform_probe_and_attach(platform_t plate)
274 {
275 
276 	if (fdt_immr_addr(MV_BASE) != 0)
277 		while (1);
278 	return (0);
279 }
280 
281 static void
282 mv_platform_gpio_init(platform_t plate)
283 {
284 
285 	/*
286 	 * Re-initialise MPP. It is important to call this prior to using
287 	 * console as the physical connection can be routed via MPP.
288 	 */
289 	if (platform_mpp_init() != 0)
290 		while (1);
291 }
292 
293 static void
294 mv_a38x_platform_late_init(platform_t plate)
295 {
296 
297 	/*
298 	 * Re-initialise decode windows
299 	 */
300 	if (mv_check_soc_family() == MV_SOC_UNSUPPORTED)
301 		panic("Unsupported SoC family\n");
302 
303 	if (soc_decode_win() != 0)
304 		printf("WARNING: could not re-initialise decode windows! "
305 		    "Running with existing settings...\n");
306 
307 	/* Configure timers' base frequency */
308 	arm_tmr_change_frequency(get_cpu_freq() / 2);
309 
310 	/*
311 	 * Workaround for Marvell Armada38X family HW issue
312 	 * between Cortex-A9 CPUs and on-chip devices that may
313 	 * cause hang on heavy load.
314 	 * To avoid that, map all registers including PCIe IO
315 	 * as strongly ordered instead of device memory.
316 	 */
317 	pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO);
318 
319 	/* Set IO Sync Barrier bit for all Mbus devices */
320 	if (armada38x_win_set_iosync_barrier() != 0)
321 		printf("WARNING: could not map CPU Subsystem registers\n");
322 	if (armada38x_mbus_optimization() != 0)
323 		printf("WARNING: could not enable mbus optimization\n");
324 	if (armada38x_scu_enable() != 0)
325 		printf("WARNING: could not enable SCU\n");
326 #ifdef SMP
327 	/* Open window to bootROM memory - needed for SMP */
328 	if (armada38x_open_bootrom_win() != 0)
329 		printf("WARNING: could not open window to bootROM\n");
330 #endif
331 }
332 
333 static void
334 mv_axp_platform_late_init(platform_t plate)
335 {
336 	phandle_t node;
337 	/*
338 	 * Re-initialise decode windows
339 	 */
340 	if (soc_decode_win() != 0)
341 		printf("WARNING: could not re-initialise decode windows! "
342 		    "Running with existing settings...\n");
343 	if ((node = OF_finddevice("/")) == -1)
344 		return;
345 
346 #if !defined(SMP)
347 	/* For SMP case it should be initialized after APs are booted */
348 	armadaxp_init_coher_fabric();
349 #endif
350 	armadaxp_l2_init();
351 }
352 
353 #define FDT_DEVMAP_MAX	(MV_WIN_CPU_MAX_ARMV7 + 2)
354 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
355 	{ 0, 0, 0, }
356 };
357 
358 static int
359 platform_sram_devmap(struct devmap_entry *map)
360 {
361 
362 	return (ENOENT);
363 }
364 
365 /*
366  * Construct devmap table with DT-derived config data.
367  */
368 static int
369 mv_a38x_platform_devmap_init(platform_t plat)
370 {
371 	phandle_t root, child;
372 	int i;
373 
374 	i = 0;
375 	devmap_register_table(&fdt_devmap[0]);
376 
377 	if ((root = OF_finddevice("/")) == -1)
378 		return (ENXIO);
379 
380 	/*
381 	 * IMMR range.
382 	 */
383 	fdt_devmap[i].pd_va = fdt_immr_va;
384 	fdt_devmap[i].pd_pa = fdt_immr_pa;
385 	fdt_devmap[i].pd_size = fdt_immr_size;
386 	i++;
387 
388 	/*
389 	 * SRAM range.
390 	 */
391 	if (i < FDT_DEVMAP_MAX)
392 		if (platform_sram_devmap(&fdt_devmap[i]) == 0)
393 			i++;
394 
395 	/*
396 	 * PCI range(s).
397 	 * PCI range(s) and localbus.
398 	 */
399 	for (child = OF_child(root); child != 0; child = OF_peer(child)) {
400 		if (mv_fdt_is_type(child, "pci") ||
401 		    mv_fdt_is_type(child, "pciep")) {
402 			/*
403 			 * Check space: each PCI node will consume 2 devmap
404 			 * entries.
405 			 */
406 			if (i + 1 >= FDT_DEVMAP_MAX)
407 				return (ENOMEM);
408 
409 			if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
410 				    MV_PCI_VA_MEM_BASE) != 0)
411 				return (ENXIO);
412 			i += 2;
413 		}
414 	}
415 
416 	return (0);
417 }
418 
419 static int
420 mv_axp_platform_devmap_init(platform_t plate)
421 {
422 	vm_paddr_t cur_immr_pa;
423 
424 	/*
425 	 * Acquire SoC registers' base passed by u-boot and fill devmap
426 	 * accordingly. DTB is going to be modified basing on this data
427 	 * later.
428 	 */
429 	__asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
430 	cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
431 	if (cur_immr_pa != 0)
432 		fdt_immr_pa = cur_immr_pa;
433 
434 	mv_a38x_platform_devmap_init(plate);
435 
436 	return (0);
437 }
438 
439 static void
440 mv_cpu_reset(platform_t plat)
441 {
442 
443 	write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7);
444 	write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7);
445 }
446 
447 #if defined(SOC_MV_ARMADA38X)
448 static platform_method_t mv_a38x_methods[] = {
449 	PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init),
450 	PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset),
451 	PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr),
452 	PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach),
453 	PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init),
454 	PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init),
455 	PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init),
456 	PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl),
457 	PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug),
458 #ifdef SMP
459 	PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap),
460 	PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid),
461 #endif
462 
463 	PLATFORMMETHOD_END,
464 };
465 FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100);
466 #endif
467 
468 static platform_method_t mv_axp_methods[] = {
469 	PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init),
470 	PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset),
471 	PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr),
472 	PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach),
473 	PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init),
474 	PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init),
475 #ifdef SMP
476 	PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap),
477 	PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid),
478 #endif
479 
480 	PLATFORMMETHOD_END,
481 };
482 FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100);
483