1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2017 Semihalf. 5 * Copyright (c) 1994-1998 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 39 */ 40 41 #include "opt_ddb.h" 42 #include "opt_platform.h" 43 44 #include <sys/cdefs.h> 45 #define _ARM32_BUS_DMA_PRIVATE 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/devmap.h> 50 #include <sys/kernel.h> 51 52 #include <vm/vm.h> 53 #include <vm/pmap.h> 54 55 #include <arm/arm/mpcore_timervar.h> 56 #include <arm/arm/nexusvar.h> 57 58 #include <machine/bus.h> 59 #include <machine/fdt.h> 60 #include <machine/machdep.h> 61 #include <machine/platform.h> 62 #include <machine/platformvar.h> 63 #include <machine/pte.h> 64 65 #include <arm/mv/mvreg.h> 66 #include <arm/mv/mvvar.h> 67 #include <arm/mv/mvwin.h> 68 69 #include <dev/fdt/fdt_common.h> 70 #include <dev/ofw/ofw_bus_subr.h> 71 72 #include "opt_platform.h" 73 #include "platform_if.h" 74 75 #if defined(SOC_MV_ARMADA38X) 76 #include "platform_pl310_if.h" 77 #include "armada38x/armada38x_pl310.h" 78 #endif 79 80 static int platform_mpp_init(void); 81 int armada38x_win_set_iosync_barrier(void); 82 int armada38x_scu_enable(void); 83 int armada38x_open_bootrom_win(void); 84 int armada38x_mbus_optimization(void); 85 86 static vm_offset_t mv_platform_lastaddr(platform_t plate); 87 static int mv_platform_probe_and_attach(platform_t plate); 88 static void mv_platform_gpio_init(platform_t plate); 89 static void mv_cpu_reset(platform_t plat); 90 91 static void mv_a38x_platform_late_init(platform_t plate); 92 static int mv_a38x_platform_devmap_init(platform_t plate); 93 static void mv_axp_platform_late_init(platform_t plate); 94 static int mv_axp_platform_devmap_init(platform_t plate); 95 96 void armadaxp_init_coher_fabric(void); 97 void armadaxp_l2_init(void); 98 99 #ifdef SMP 100 void mv_a38x_platform_mp_setmaxid(platform_t plate); 101 void mv_a38x_platform_mp_start_ap(platform_t plate); 102 void mv_axp_platform_mp_setmaxid(platform_t plate); 103 void mv_axp_platform_mp_start_ap(platform_t plate); 104 #endif 105 106 vm_paddr_t fdt_immr_pa; 107 vm_offset_t fdt_immr_va; 108 static vm_offset_t fdt_immr_size; 109 110 #define MPP_PIN_MAX 68 111 #define MPP_PIN_CELLS 2 112 #define MPP_PINS_PER_REG 8 113 #define MPP_SEL(pin,func) (((func) & 0xf) << \ 114 (((pin) % MPP_PINS_PER_REG) * 4)) 115 116 static void 117 mv_busdma_tag_init(void *arg __unused) 118 { 119 phandle_t node; 120 bus_dma_tag_t dmat; 121 122 /* 123 * If this platform has coherent DMA, create the parent DMA tag to pass 124 * down the coherent flag to all busses and devices on the platform, 125 * otherwise return without doing anything. By default create tag 126 * for all A38x-based platforms only. 127 */ 128 if ((node = OF_finddevice("/")) == -1){ 129 printf("no tree\n"); 130 return; 131 } 132 133 if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) 134 return; 135 136 bus_dma_tag_create(NULL, /* No parent tag */ 137 1, 0, /* alignment, bounds */ 138 BUS_SPACE_MAXADDR, /* lowaddr */ 139 BUS_SPACE_MAXADDR, /* highaddr */ 140 NULL, NULL, /* filter, filterarg */ 141 BUS_SPACE_MAXSIZE, /* maxsize */ 142 BUS_SPACE_UNRESTRICTED, /* nsegments */ 143 BUS_SPACE_MAXSIZE, /* maxsegsize */ 144 BUS_DMA_COHERENT, /* flags */ 145 NULL, NULL, /* lockfunc, lockarg */ 146 &dmat); 147 148 nexus_set_dma_tag(dmat); 149 150 } 151 SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); 152 153 static int 154 platform_mpp_init(void) 155 { 156 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 157 int mpp[MPP_PIN_MAX]; 158 uint32_t ctrl_val, ctrl_offset; 159 pcell_t reg[4]; 160 u_long start, size; 161 phandle_t node; 162 pcell_t pin_cells, *pinmap_ptr, pin_count; 163 ssize_t len; 164 int par_addr_cells, par_size_cells; 165 int tuple_size, rv, pins, i, j; 166 int mpp_pin, mpp_function; 167 168 /* 169 * Try to access the MPP node directly i.e. through /aliases/mpp. 170 */ 171 if ((node = OF_finddevice("mpp")) != -1) 172 if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) 173 goto moveon; 174 /* 175 * Find the node the long way. 176 */ 177 if ((node = OF_finddevice("/")) == -1) 178 return (ENXIO); 179 180 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 181 return (ENXIO); 182 183 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 184 /* 185 * No MPP node. Fall back to how MPP got set by the 186 * first-stage loader and try to continue booting. 187 */ 188 return (0); 189 moveon: 190 /* 191 * Process 'reg' prop. 192 */ 193 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 194 &par_size_cells)) != 0) 195 return(ENXIO); 196 197 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 198 len = OF_getprop(node, "reg", reg, sizeof(reg)); 199 if (tuple_size <= 0) 200 return (EINVAL); 201 202 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 203 &start, &size); 204 if (rv != 0) 205 return (rv); 206 start += fdt_immr_va; 207 208 /* 209 * Process 'pin-count' and 'pin-map' props. 210 */ 211 if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 212 return (ENXIO); 213 if (pin_count > MPP_PIN_MAX) 214 return (ERANGE); 215 216 if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 217 pin_cells = MPP_PIN_CELLS; 218 if (pin_cells > MPP_PIN_CELLS) 219 return (ERANGE); 220 tuple_size = sizeof(pcell_t) * pin_cells; 221 222 bzero(pinmap, sizeof(pinmap)); 223 len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); 224 if (len <= 0) 225 return (ERANGE); 226 if (len % tuple_size) 227 return (ERANGE); 228 pins = len / tuple_size; 229 if (pins > pin_count) 230 return (ERANGE); 231 /* 232 * Fill out a "mpp[pin] => function" table. All pins unspecified in 233 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 234 */ 235 bzero(mpp, sizeof(mpp)); 236 pinmap_ptr = pinmap; 237 for (i = 0; i < pins; i++) { 238 mpp_pin = *pinmap_ptr; 239 mpp_function = *(pinmap_ptr + 1); 240 mpp[mpp_pin] = mpp_function; 241 pinmap_ptr += pin_cells; 242 } 243 244 /* 245 * Prepare and program MPP control register values. 246 */ 247 ctrl_offset = 0; 248 for (i = 0; i < pin_count;) { 249 ctrl_val = 0; 250 251 for (j = 0; j < MPP_PINS_PER_REG; j++) { 252 if (i + j == pin_count - 1) 253 break; 254 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 255 } 256 i += MPP_PINS_PER_REG; 257 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 258 ctrl_val); 259 260 ctrl_offset += 4; 261 } 262 263 return (0); 264 } 265 266 static vm_offset_t 267 mv_platform_lastaddr(platform_t plat) 268 { 269 270 return (fdt_immr_va); 271 } 272 273 static int 274 mv_platform_probe_and_attach(platform_t plate) 275 { 276 277 phandle_t node; 278 u_long base, size; 279 int r; 280 281 /* 282 * Try to access the SOC node directly i.e. through /aliases/. 283 */ 284 if ((node = OF_finddevice("soc")) != -1) 285 if (ofw_bus_node_is_compatible(node, "simple-bus")) 286 goto moveon; 287 /* 288 * Find the node the long way. 289 */ 290 if ((node = OF_finddevice("/")) == -1) 291 goto errout; 292 293 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 294 goto errout; 295 296 moveon: 297 if ((r = fdt_get_range(node, 0, &base, &size)) == 0) { 298 fdt_immr_pa = base; 299 fdt_immr_va = MV_BASE; 300 fdt_immr_size = size; 301 return (0); 302 } 303 304 errout: 305 while (1); 306 } 307 308 static void 309 mv_platform_gpio_init(platform_t plate) 310 { 311 312 /* 313 * Re-initialise MPP. It is important to call this prior to using 314 * console as the physical connection can be routed via MPP. 315 */ 316 if (platform_mpp_init() != 0) 317 while (1); 318 } 319 320 static void 321 mv_a38x_platform_late_init(platform_t plate) 322 { 323 324 /* 325 * Re-initialise decode windows 326 */ 327 if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) 328 panic("Unsupported SoC family\n"); 329 330 if (soc_decode_win() != 0) 331 printf("WARNING: could not re-initialise decode windows! " 332 "Running with existing settings...\n"); 333 334 /* Configure timers' base frequency */ 335 arm_tmr_change_frequency(get_cpu_freq() / 2); 336 337 /* 338 * Workaround for Marvell Armada38X family HW issue 339 * between Cortex-A9 CPUs and on-chip devices that may 340 * cause hang on heavy load. 341 * To avoid that, map all registers including PCIe IO 342 * as strongly ordered instead of device memory. 343 */ 344 pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO); 345 346 /* Set IO Sync Barrier bit for all Mbus devices */ 347 if (armada38x_win_set_iosync_barrier() != 0) 348 printf("WARNING: could not map CPU Subsystem registers\n"); 349 if (armada38x_mbus_optimization() != 0) 350 printf("WARNING: could not enable mbus optimization\n"); 351 if (armada38x_scu_enable() != 0) 352 printf("WARNING: could not enable SCU\n"); 353 #ifdef SMP 354 /* Open window to bootROM memory - needed for SMP */ 355 if (armada38x_open_bootrom_win() != 0) 356 printf("WARNING: could not open window to bootROM\n"); 357 #endif 358 } 359 360 static void 361 mv_axp_platform_late_init(platform_t plate) 362 { 363 phandle_t node; 364 /* 365 * Re-initialise decode windows 366 */ 367 if (soc_decode_win() != 0) 368 printf("WARNING: could not re-initialise decode windows! " 369 "Running with existing settings...\n"); 370 if ((node = OF_finddevice("/")) == -1) 371 return; 372 373 #if !defined(SMP) 374 /* For SMP case it should be initialized after APs are booted */ 375 armadaxp_init_coher_fabric(); 376 #endif 377 armadaxp_l2_init(); 378 } 379 380 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2) 381 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 382 { 0, 0, 0, } 383 }; 384 385 static int 386 platform_sram_devmap(struct devmap_entry *map) 387 { 388 389 return (ENOENT); 390 } 391 392 /* 393 * Construct devmap table with DT-derived config data. 394 */ 395 static int 396 mv_a38x_platform_devmap_init(platform_t plat) 397 { 398 phandle_t root, child; 399 int i; 400 401 i = 0; 402 devmap_register_table(&fdt_devmap[0]); 403 404 if ((root = OF_finddevice("/")) == -1) 405 return (ENXIO); 406 407 /* 408 * IMMR range. 409 */ 410 fdt_devmap[i].pd_va = fdt_immr_va; 411 fdt_devmap[i].pd_pa = fdt_immr_pa; 412 fdt_devmap[i].pd_size = fdt_immr_size; 413 i++; 414 415 /* 416 * SRAM range. 417 */ 418 if (i < FDT_DEVMAP_MAX) 419 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 420 i++; 421 422 /* 423 * PCI range(s). 424 * PCI range(s) and localbus. 425 */ 426 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 427 if (mv_fdt_is_type(child, "pci") || 428 mv_fdt_is_type(child, "pciep")) { 429 /* 430 * Check space: each PCI node will consume 2 devmap 431 * entries. 432 */ 433 if (i + 1 >= FDT_DEVMAP_MAX) 434 return (ENOMEM); 435 436 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 437 MV_PCI_VA_MEM_BASE) != 0) 438 return (ENXIO); 439 i += 2; 440 } 441 } 442 443 return (0); 444 } 445 446 static int 447 mv_axp_platform_devmap_init(platform_t plate) 448 { 449 vm_paddr_t cur_immr_pa; 450 451 /* 452 * Acquire SoC registers' base passed by u-boot and fill devmap 453 * accordingly. DTB is going to be modified basing on this data 454 * later. 455 */ 456 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 457 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 458 if (cur_immr_pa != 0) 459 fdt_immr_pa = cur_immr_pa; 460 461 mv_a38x_platform_devmap_init(plate); 462 463 return (0); 464 } 465 466 static void 467 mv_cpu_reset(platform_t plat) 468 { 469 470 write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7); 471 write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7); 472 } 473 474 #if defined(SOC_MV_ARMADA38X) 475 static platform_method_t mv_a38x_methods[] = { 476 PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init), 477 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 478 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 479 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 480 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 481 PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init), 482 PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init), 483 PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl), 484 PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug), 485 #ifdef SMP 486 PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap), 487 PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid), 488 #endif 489 490 PLATFORMMETHOD_END, 491 }; 492 FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100); 493 #endif 494 495 static platform_method_t mv_axp_methods[] = { 496 PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init), 497 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 498 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 499 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 500 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 501 PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init), 502 #ifdef SMP 503 PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap), 504 PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid), 505 #endif 506 507 PLATFORMMETHOD_END, 508 }; 509 FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100); 510