1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2017 Semihalf. 5 * Copyright (c) 1994-1998 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 39 */ 40 41 #include "opt_ddb.h" 42 #include "opt_platform.h" 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #define _ARM32_BUS_DMA_PRIVATE 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/bus.h> 51 #include <sys/devmap.h> 52 #include <sys/kernel.h> 53 54 #include <vm/vm.h> 55 #include <vm/pmap.h> 56 57 #include <arm/arm/mpcore_timervar.h> 58 #include <arm/arm/nexusvar.h> 59 60 #include <machine/bus.h> 61 #include <machine/fdt.h> 62 #include <machine/machdep.h> 63 #include <machine/platform.h> 64 #include <machine/platformvar.h> 65 #include <machine/pte-v6.h> 66 67 #include <arm/mv/mvreg.h> 68 #include <arm/mv/mvvar.h> 69 #include <arm/mv/mvwin.h> 70 71 #include <dev/fdt/fdt_common.h> 72 #include <dev/ofw/ofw_bus_subr.h> 73 74 #include "opt_platform.h" 75 #include "platform_if.h" 76 77 #if defined(SOC_MV_ARMADA38X) 78 #include "platform_pl310_if.h" 79 #include "armada38x/armada38x_pl310.h" 80 #endif 81 82 static int platform_mpp_init(void); 83 int armada38x_win_set_iosync_barrier(void); 84 int armada38x_scu_enable(void); 85 int armada38x_open_bootrom_win(void); 86 int armada38x_mbus_optimization(void); 87 88 static vm_offset_t mv_platform_lastaddr(platform_t plate); 89 static int mv_platform_probe_and_attach(platform_t plate); 90 static void mv_platform_gpio_init(platform_t plate); 91 static void mv_cpu_reset(platform_t plat); 92 93 static void mv_a38x_platform_late_init(platform_t plate); 94 static int mv_a38x_platform_devmap_init(platform_t plate); 95 static void mv_axp_platform_late_init(platform_t plate); 96 static int mv_axp_platform_devmap_init(platform_t plate); 97 98 void armadaxp_init_coher_fabric(void); 99 void armadaxp_l2_init(void); 100 101 #ifdef SMP 102 void mv_a38x_platform_mp_setmaxid(platform_t plate); 103 void mv_a38x_platform_mp_start_ap(platform_t plate); 104 void mv_axp_platform_mp_setmaxid(platform_t plate); 105 void mv_axp_platform_mp_start_ap(platform_t plate); 106 #endif 107 108 #define MPP_PIN_MAX 68 109 #define MPP_PIN_CELLS 2 110 #define MPP_PINS_PER_REG 8 111 #define MPP_SEL(pin,func) (((func) & 0xf) << \ 112 (((pin) % MPP_PINS_PER_REG) * 4)) 113 114 static void 115 mv_busdma_tag_init(void *arg __unused) 116 { 117 phandle_t node; 118 bus_dma_tag_t dmat; 119 120 /* 121 * If this platform has coherent DMA, create the parent DMA tag to pass 122 * down the coherent flag to all busses and devices on the platform, 123 * otherwise return without doing anything. By default create tag 124 * for all A38x-based platforms only. 125 */ 126 if ((node = OF_finddevice("/")) == -1){ 127 printf("no tree\n"); 128 return; 129 } 130 131 if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) 132 return; 133 134 bus_dma_tag_create(NULL, /* No parent tag */ 135 1, 0, /* alignment, bounds */ 136 BUS_SPACE_MAXADDR, /* lowaddr */ 137 BUS_SPACE_MAXADDR, /* highaddr */ 138 NULL, NULL, /* filter, filterarg */ 139 BUS_SPACE_MAXSIZE, /* maxsize */ 140 BUS_SPACE_UNRESTRICTED, /* nsegments */ 141 BUS_SPACE_MAXSIZE, /* maxsegsize */ 142 BUS_DMA_COHERENT, /* flags */ 143 NULL, NULL, /* lockfunc, lockarg */ 144 &dmat); 145 146 nexus_set_dma_tag(dmat); 147 148 } 149 SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); 150 151 static int 152 platform_mpp_init(void) 153 { 154 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 155 int mpp[MPP_PIN_MAX]; 156 uint32_t ctrl_val, ctrl_offset; 157 pcell_t reg[4]; 158 u_long start, size; 159 phandle_t node; 160 pcell_t pin_cells, *pinmap_ptr, pin_count; 161 ssize_t len; 162 int par_addr_cells, par_size_cells; 163 int tuple_size, rv, pins, i, j; 164 int mpp_pin, mpp_function; 165 166 /* 167 * Try to access the MPP node directly i.e. through /aliases/mpp. 168 */ 169 if ((node = OF_finddevice("mpp")) != -1) 170 if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) 171 goto moveon; 172 /* 173 * Find the node the long way. 174 */ 175 if ((node = OF_finddevice("/")) == -1) 176 return (ENXIO); 177 178 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 179 return (ENXIO); 180 181 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 182 /* 183 * No MPP node. Fall back to how MPP got set by the 184 * first-stage loader and try to continue booting. 185 */ 186 return (0); 187 moveon: 188 /* 189 * Process 'reg' prop. 190 */ 191 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 192 &par_size_cells)) != 0) 193 return(ENXIO); 194 195 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 196 len = OF_getprop(node, "reg", reg, sizeof(reg)); 197 if (tuple_size <= 0) 198 return (EINVAL); 199 200 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 201 &start, &size); 202 if (rv != 0) 203 return (rv); 204 start += fdt_immr_va; 205 206 /* 207 * Process 'pin-count' and 'pin-map' props. 208 */ 209 if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 210 return (ENXIO); 211 if (pin_count > MPP_PIN_MAX) 212 return (ERANGE); 213 214 if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 215 pin_cells = MPP_PIN_CELLS; 216 if (pin_cells > MPP_PIN_CELLS) 217 return (ERANGE); 218 tuple_size = sizeof(pcell_t) * pin_cells; 219 220 bzero(pinmap, sizeof(pinmap)); 221 len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); 222 if (len <= 0) 223 return (ERANGE); 224 if (len % tuple_size) 225 return (ERANGE); 226 pins = len / tuple_size; 227 if (pins > pin_count) 228 return (ERANGE); 229 /* 230 * Fill out a "mpp[pin] => function" table. All pins unspecified in 231 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 232 */ 233 bzero(mpp, sizeof(mpp)); 234 pinmap_ptr = pinmap; 235 for (i = 0; i < pins; i++) { 236 mpp_pin = *pinmap_ptr; 237 mpp_function = *(pinmap_ptr + 1); 238 mpp[mpp_pin] = mpp_function; 239 pinmap_ptr += pin_cells; 240 } 241 242 /* 243 * Prepare and program MPP control register values. 244 */ 245 ctrl_offset = 0; 246 for (i = 0; i < pin_count;) { 247 ctrl_val = 0; 248 249 for (j = 0; j < MPP_PINS_PER_REG; j++) { 250 if (i + j == pin_count - 1) 251 break; 252 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 253 } 254 i += MPP_PINS_PER_REG; 255 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 256 ctrl_val); 257 258 ctrl_offset += 4; 259 } 260 261 return (0); 262 } 263 264 static vm_offset_t 265 mv_platform_lastaddr(platform_t plat) 266 { 267 268 return (fdt_immr_va); 269 } 270 271 static int 272 mv_platform_probe_and_attach(platform_t plate) 273 { 274 275 if (fdt_immr_addr(MV_BASE) != 0) 276 while (1); 277 return (0); 278 } 279 280 static void 281 mv_platform_gpio_init(platform_t plate) 282 { 283 284 /* 285 * Re-initialise MPP. It is important to call this prior to using 286 * console as the physical connection can be routed via MPP. 287 */ 288 if (platform_mpp_init() != 0) 289 while (1); 290 } 291 292 static void 293 mv_a38x_platform_late_init(platform_t plate) 294 { 295 296 /* 297 * Re-initialise decode windows 298 */ 299 if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) 300 panic("Unsupported SoC family\n"); 301 302 if (soc_decode_win() != 0) 303 printf("WARNING: could not re-initialise decode windows! " 304 "Running with existing settings...\n"); 305 306 /* Configure timers' base frequency */ 307 arm_tmr_change_frequency(get_cpu_freq() / 2); 308 309 /* 310 * Workaround for Marvell Armada38X family HW issue 311 * between Cortex-A9 CPUs and on-chip devices that may 312 * cause hang on heavy load. 313 * To avoid that, map all registers including PCIe IO 314 * as strongly ordered instead of device memory. 315 */ 316 pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO); 317 318 /* Set IO Sync Barrier bit for all Mbus devices */ 319 if (armada38x_win_set_iosync_barrier() != 0) 320 printf("WARNING: could not map CPU Subsystem registers\n"); 321 if (armada38x_mbus_optimization() != 0) 322 printf("WARNING: could not enable mbus optimization\n"); 323 if (armada38x_scu_enable() != 0) 324 printf("WARNING: could not enable SCU\n"); 325 #ifdef SMP 326 /* Open window to bootROM memory - needed for SMP */ 327 if (armada38x_open_bootrom_win() != 0) 328 printf("WARNING: could not open window to bootROM\n"); 329 #endif 330 } 331 332 static void 333 mv_axp_platform_late_init(platform_t plate) 334 { 335 phandle_t node; 336 /* 337 * Re-initialise decode windows 338 */ 339 if (soc_decode_win() != 0) 340 printf("WARNING: could not re-initialise decode windows! " 341 "Running with existing settings...\n"); 342 if ((node = OF_finddevice("/")) == -1) 343 return; 344 345 #if !defined(SMP) 346 /* For SMP case it should be initialized after APs are booted */ 347 armadaxp_init_coher_fabric(); 348 #endif 349 armadaxp_l2_init(); 350 } 351 352 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2) 353 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { 354 { 0, 0, 0, } 355 }; 356 357 static int 358 platform_sram_devmap(struct devmap_entry *map) 359 { 360 361 return (ENOENT); 362 } 363 364 /* 365 * Construct devmap table with DT-derived config data. 366 */ 367 static int 368 mv_a38x_platform_devmap_init(platform_t plat) 369 { 370 phandle_t root, child; 371 int i; 372 373 i = 0; 374 devmap_register_table(&fdt_devmap[0]); 375 376 if ((root = OF_finddevice("/")) == -1) 377 return (ENXIO); 378 379 /* 380 * IMMR range. 381 */ 382 fdt_devmap[i].pd_va = fdt_immr_va; 383 fdt_devmap[i].pd_pa = fdt_immr_pa; 384 fdt_devmap[i].pd_size = fdt_immr_size; 385 i++; 386 387 /* 388 * SRAM range. 389 */ 390 if (i < FDT_DEVMAP_MAX) 391 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 392 i++; 393 394 /* 395 * PCI range(s). 396 * PCI range(s) and localbus. 397 */ 398 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 399 if (mv_fdt_is_type(child, "pci") || 400 mv_fdt_is_type(child, "pciep")) { 401 /* 402 * Check space: each PCI node will consume 2 devmap 403 * entries. 404 */ 405 if (i + 1 >= FDT_DEVMAP_MAX) 406 return (ENOMEM); 407 408 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 409 MV_PCI_VA_MEM_BASE) != 0) 410 return (ENXIO); 411 i += 2; 412 } 413 } 414 415 return (0); 416 } 417 418 static int 419 mv_axp_platform_devmap_init(platform_t plate) 420 { 421 vm_paddr_t cur_immr_pa; 422 423 /* 424 * Acquire SoC registers' base passed by u-boot and fill devmap 425 * accordingly. DTB is going to be modified basing on this data 426 * later. 427 */ 428 __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); 429 cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; 430 if (cur_immr_pa != 0) 431 fdt_immr_pa = cur_immr_pa; 432 433 mv_a38x_platform_devmap_init(plate); 434 435 return (0); 436 } 437 438 static void 439 mv_cpu_reset(platform_t plat) 440 { 441 442 write_cpu_misc(RSTOUTn_MASK_ARMV7, SOFT_RST_OUT_EN_ARMV7); 443 write_cpu_misc(SYSTEM_SOFT_RESET_ARMV7, SYS_SOFT_RST_ARMV7); 444 } 445 446 #if defined(SOC_MV_ARMADA38X) 447 static platform_method_t mv_a38x_methods[] = { 448 PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init), 449 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 450 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 451 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 452 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 453 PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init), 454 PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init), 455 PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl), 456 PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug), 457 #ifdef SMP 458 PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap), 459 PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid), 460 #endif 461 462 PLATFORMMETHOD_END, 463 }; 464 FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100); 465 #endif 466 467 static platform_method_t mv_axp_methods[] = { 468 PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init), 469 PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), 470 PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), 471 PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), 472 PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), 473 PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init), 474 #ifdef SMP 475 PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap), 476 PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid), 477 #endif 478 479 PLATFORMMETHOD_END, 480 }; 481 FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100); 482