xref: /freebsd/sys/arm/mv/mv_ap806_sei.c (revision 6966ac055c3b7a39266fb982493330df7a097997)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/proc.h>
37 #include <sys/rman.h>
38 #include <sys/lock.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
41 
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44 #include <machine/resource.h>
45 
46 #include <dev/fdt/simplebus.h>
47 
48 #include <dev/ofw/ofw_bus.h>
49 #include <dev/ofw/ofw_bus_subr.h>
50 
51 #include "pic_if.h"
52 
53 #define	MV_AP806_SEI_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
54 #define	MV_AP806_SEI_UNLOCK(_sc)	mtx_unlock(&(_sc)->mtx)
55 #define	MV_AP806_SEI_LOCK_INIT(_sc)	mtx_init(&_sc->mtx, 			\
56 	    device_get_nameunit(_sc->dev), "mv_ap806_sei", MTX_DEF)
57 #define	MV_AP806_SEI_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->mtx);
58 #define	MV_AP806_SEI_ASSERT_LOCKED(_sc)	mtx_assert(&_sc->mtx, MA_OWNED);
59 #define	MV_AP806_SEI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
60 
61 #define	MV_AP806_SEI_MAX_NIRQS	64
62 #define GICP_SECR0		0x00
63 #define GICP_SECR1		0x04
64 #define GICP_SECR(i)		(0x00  + (((i)/32) * 0x4))
65 #define GICP_SECR_BIT(i)	((i) % 32)
66 #define GICP_SEMR0		0x20
67 #define GICP_SEMR1		0x24
68 #define GICP_SEMR(i)		(0x20  + (((i)/32) * 0x4))
69 #define GICP_SEMR_BIT(i)	((i) % 32)
70 
71 
72 
73 struct mv_ap806_sei_irqsrc {
74 	struct intr_irqsrc	isrc;
75 	u_int			irq;
76 };
77 
78 struct mv_ap806_sei_softc {
79 	device_t		dev;
80 	struct resource		*mem_res;
81 	struct resource		*irq_res;
82 	void			*irq_ih;
83 	struct mtx		mtx;
84 
85 	struct mv_ap806_sei_irqsrc *isrcs;
86 };
87 
88 static struct ofw_compat_data compat_data[] = {
89 	{"marvell,ap806-sei", 1},
90 	{NULL,             0}
91 };
92 
93 #define	RD4(sc, reg)		bus_read_4((sc)->mem_res, (reg))
94 #define	WR4(sc, reg, val)	bus_write_4((sc)->mem_res, (reg), (val))
95 
96 static inline void
97 mv_ap806_sei_isrc_mask(struct mv_ap806_sei_softc *sc,
98      struct mv_ap806_sei_irqsrc *sisrc, uint32_t val)
99 {
100 	uint32_t tmp;
101 	int bit;
102 
103 	bit = GICP_SEMR_BIT(sisrc->irq);
104 	MV_AP806_SEI_LOCK(sc);
105 	tmp = RD4(sc, GICP_SEMR(sisrc->irq));
106 	if (val != 0)
107 		tmp |= 1 << bit;
108 	else
109 		tmp &= ~(1 << bit);
110 	WR4(sc, GICP_SEMR(sisrc->irq), tmp);
111 	MV_AP806_SEI_UNLOCK(sc);
112 }
113 
114 static inline void
115 mv_ap806_sei_isrc_eoi(struct mv_ap806_sei_softc *sc,
116      struct mv_ap806_sei_irqsrc *sisrc)
117 {
118 
119 	WR4(sc, GICP_SECR(sisrc->irq), GICP_SECR_BIT(sisrc->irq));
120 }
121 
122 static void
123 mv_ap806_sei_enable_intr(device_t dev, struct intr_irqsrc *isrc)
124 {
125 	struct mv_ap806_sei_softc *sc;
126 	struct mv_ap806_sei_irqsrc *sisrc;
127 
128 	sc = device_get_softc(dev);
129 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
130 	mv_ap806_sei_isrc_mask(sc, sisrc, 0);
131 }
132 
133 static void
134 mv_ap806_sei_disable_intr(device_t dev, struct intr_irqsrc *isrc)
135 {
136 	struct mv_ap806_sei_softc *sc;
137 	struct mv_ap806_sei_irqsrc *sisrc;
138 
139 	sc = device_get_softc(dev);
140 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
141 	mv_ap806_sei_isrc_mask(sc, sisrc, 1);
142 }
143 
144 static int
145 mv_ap806_sei_map(device_t dev, struct intr_map_data *data, u_int *irqp)
146 {
147 	struct mv_ap806_sei_softc *sc;
148 	struct intr_map_data_fdt *daf;
149 	u_int irq;
150 
151 	sc = device_get_softc(dev);
152 
153 	if (data->type != INTR_MAP_DATA_FDT)
154 		return (ENOTSUP);
155 
156 	daf = (struct intr_map_data_fdt *)data;
157 	if (daf->ncells != 1 || daf->cells[0] >= MV_AP806_SEI_MAX_NIRQS)
158 		return (EINVAL);
159 	irq = daf->cells[0];
160 	if (irqp != NULL)
161 		*irqp = irq;
162 
163 	return(0);
164 }
165 
166 static int
167 mv_ap806_sei_map_intr(device_t dev, struct intr_map_data *data,
168     struct intr_irqsrc **isrcp)
169 {
170 	struct mv_ap806_sei_softc *sc;
171 	u_int irq;
172 	int rv;
173 
174 	sc = device_get_softc(dev);
175 	rv = mv_ap806_sei_map(dev, data, &irq);
176 	if (rv == 0)
177 		*isrcp = &sc->isrcs[irq].isrc;
178 
179 	return (rv);
180 }
181 
182 
183 
184 static int
185 mv_ap806_sei_setup_intr(device_t dev, struct intr_irqsrc *isrc,
186     struct resource *res, struct intr_map_data *data)
187 {
188 	struct mv_ap806_sei_softc *sc;
189 	struct mv_ap806_sei_irqsrc *sisrc;
190 	u_int irq;
191 	int rv;
192 
193 	sc = device_get_softc(dev);
194 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
195 	if (data == NULL)
196 		return (ENOTSUP);
197 	rv = mv_ap806_sei_map(dev, data, &irq);
198 	if (rv != 0)
199 		return (rv);
200 	if (irq != sisrc->irq)
201 		return (EINVAL);
202 	mv_ap806_sei_isrc_mask(sc, sisrc, 0);
203 	return (0);
204 }
205 
206 static int
207 mv_ap806_sei_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
208     struct resource *res, struct intr_map_data *data)
209 {
210 	struct mv_ap806_sei_softc *sc;
211 	struct mv_ap806_sei_irqsrc *sisrc;
212 
213 	sc = device_get_softc(dev);
214 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
215 
216 	mv_ap806_sei_isrc_mask(sc, sisrc, 1);
217 	return (0);
218 }
219 
220 static void
221 mv_ap806_sei_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
222 {
223 	struct mv_ap806_sei_softc *sc;
224 	struct mv_ap806_sei_irqsrc *sisrc;
225 
226 	sc = device_get_softc(dev);
227 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
228 
229 	mv_ap806_sei_isrc_mask(sc, sisrc, 1);
230 	mv_ap806_sei_isrc_eoi(sc, sisrc);
231 }
232 
233 static void
234 mv_ap806_sei_post_ithread(device_t dev, struct intr_irqsrc *isrc)
235 {
236 	struct mv_ap806_sei_softc *sc;
237 	struct mv_ap806_sei_irqsrc *sisrc;
238 
239 	sc = device_get_softc(dev);
240 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
241 
242 	mv_ap806_sei_isrc_mask(sc, sisrc, 1);
243 }
244 
245 static void
246 mv_ap806_sei_post_filter(device_t dev, struct intr_irqsrc *isrc)
247 {
248 	struct mv_ap806_sei_softc *sc;
249 	struct mv_ap806_sei_irqsrc *sisrc;
250 
251 	sc = device_get_softc(dev);
252 	sisrc = (struct mv_ap806_sei_irqsrc *)isrc;
253 
254 	mv_ap806_sei_isrc_mask(sc, sisrc, 1);
255 	mv_ap806_sei_isrc_eoi(sc, sisrc);
256 }
257 
258 /* ----------------------------------------------------------------------------
259  *
260  *		B u s    i n t e r f a c e
261  */
262 static int
263 mv_ap806_sei_intr(void *arg)
264 {
265 	struct mv_ap806_sei_softc *sc;
266 	struct mv_ap806_sei_irqsrc *sirq;
267 	struct trapframe *tf;
268 	uint64_t cause;
269 	u_int irq;
270 
271 	sc = (struct mv_ap806_sei_softc *)arg;
272 	tf = curthread->td_intr_frame;
273 	while (1) {
274 		cause = RD4(sc, GICP_SECR1);
275 		cause <<= 32;
276 		cause |= RD4(sc, GICP_SECR0);
277 
278 		irq = ffsll(cause);
279 		if (irq == 0) break;
280 		irq--;
281 		sirq = &sc->isrcs[irq];
282 		if (intr_isrc_dispatch(&sirq->isrc, tf) != 0) {
283 			mv_ap806_sei_isrc_mask(sc, sirq, 0);
284 			mv_ap806_sei_isrc_eoi(sc, sirq);
285 			device_printf(sc->dev,
286 			    "Stray irq %u disabled\n", irq);
287 		}
288 	}
289 
290 	return (FILTER_HANDLED);
291 }
292 
293 
294 static int
295 mv_ap806_sei_probe(device_t dev)
296 {
297 
298 	if (!ofw_bus_status_okay(dev))
299 		return (ENXIO);
300 
301 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
302 		return (ENXIO);
303 
304 	device_set_desc(dev, "Marvell SEI");
305 	return (BUS_PROBE_DEFAULT);
306 }
307 
308 static int
309 mv_ap806_sei_attach(device_t dev)
310 {
311 	struct mv_ap806_sei_softc *sc;
312 	phandle_t xref, node;
313 	uint32_t irq;
314 	const char *name;
315 	int rv, rid;
316 
317 	sc = device_get_softc(dev);
318 	sc->dev = dev;
319 	node = ofw_bus_get_node(dev);
320 	MV_AP806_SEI_LOCK_INIT(sc);
321 
322 	/* Allocate resources. */
323 	rid = 0;
324 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
325 	    RF_ACTIVE);
326 	if (sc->mem_res == NULL) {
327 		device_printf(dev, "Cannot allocate memory resources\n");
328 		rv = ENXIO;
329 		goto fail;
330 	}
331 
332 	rid = 0;
333 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
334 	if (sc->irq_res == NULL) {
335 		device_printf(dev, "Cannot allocate IRQ resources\n");
336 		rv = ENXIO;
337 		goto fail;
338 	}
339 
340 	/* Mask all interrupts) */
341 	WR4(sc, GICP_SEMR0, 0xFFFFFFFF);
342 	WR4(sc, GICP_SEMR1, 0xFFFFFFFF);
343 
344 	/* Create all interrupt sources */
345 	sc->isrcs = malloc(sizeof(*sc->isrcs) * MV_AP806_SEI_MAX_NIRQS,
346 	    M_DEVBUF, M_WAITOK | M_ZERO);
347 	name = device_get_nameunit(sc->dev);
348 	for (irq = 0; irq < MV_AP806_SEI_MAX_NIRQS; irq++) {
349 		sc->isrcs[irq].irq = irq;
350 		rv = intr_isrc_register(&sc->isrcs[irq].isrc,
351 		    sc->dev, 0, "%s,%u", name, irq);
352 		if (rv != 0)
353 			goto fail; /* XXX deregister ISRCs */
354 	}
355 	xref = OF_xref_from_node(node);;
356 	if (intr_pic_register(dev, xref) == NULL) {
357 		device_printf(dev, "Cannot register SEI\n");
358 		rv = ENXIO;
359 		goto fail;
360 	}
361 	if (bus_setup_intr(dev, sc->irq_res,INTR_TYPE_MISC | INTR_MPSAFE,
362 	    mv_ap806_sei_intr, NULL, sc, &sc->irq_ih)) {
363 		device_printf(dev,
364 		    "Unable to register interrupt handler\n");
365 		rv = ENXIO;
366 		goto fail;
367 	}
368 
369 	OF_device_register_xref(xref, dev);
370 	return (0);
371 
372 fail:
373 	if (sc->irq_ih != NULL)
374 		bus_teardown_intr(dev, sc->irq_res, sc->irq_ih);
375 	if (sc->irq_res != NULL)
376 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
377 	if (sc->mem_res != NULL)
378 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
379 	MV_AP806_SEI_LOCK_DESTROY(sc);
380 	return (ENXIO);
381 }
382 
383 static int
384 mv_ap806_sei_detach(device_t dev)
385 {
386 
387 	return (EBUSY);
388 }
389 
390 
391 static device_method_t mv_ap806_sei_methods[] = {
392 	/* Device interface */
393 	DEVMETHOD(device_probe,		mv_ap806_sei_probe),
394 	DEVMETHOD(device_attach,	mv_ap806_sei_attach),
395 	DEVMETHOD(device_detach,	mv_ap806_sei_detach),
396 
397 	/* Interrupt controller interface */
398 	DEVMETHOD(pic_disable_intr,	mv_ap806_sei_disable_intr),
399 	DEVMETHOD(pic_enable_intr,	mv_ap806_sei_enable_intr),
400 	DEVMETHOD(pic_map_intr,		mv_ap806_sei_map_intr),
401 	DEVMETHOD(pic_setup_intr,	mv_ap806_sei_setup_intr),
402 	DEVMETHOD(pic_teardown_intr,	mv_ap806_sei_teardown_intr),
403 	DEVMETHOD(pic_post_filter,	mv_ap806_sei_post_filter),
404 	DEVMETHOD(pic_post_ithread,	mv_ap806_sei_post_ithread),
405 	DEVMETHOD(pic_pre_ithread,	mv_ap806_sei_pre_ithread),
406 
407 	DEVMETHOD_END
408 };
409 
410 static devclass_t mv_ap806_sei_devclass;
411 
412 static driver_t mv_ap806_sei_driver = {
413 	"mv_ap806_sei",
414 	mv_ap806_sei_methods,
415 	sizeof(struct mv_ap806_sei_softc),
416 };
417 
418 EARLY_DRIVER_MODULE(mv_ap806_sei, simplebus, mv_ap806_sei_driver,
419     mv_ap806_sei_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
420