1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Developed by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 29 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/cpuset.h> 40 #include <sys/ktr.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 #include <machine/cpufunc.h> 47 #include <machine/smp.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #define IRQ_ERR 4 53 #define MAIN_IRQS 116 54 55 #define IRQ_MASK 0x3ff 56 57 #define MPIC_CTRL 0x0 58 #define MPIC_SOFT_INT 0x4 59 #define MPIC_ERR_CAUSE 0x20 60 #define MPIC_ISE 0x30 61 #define MPIC_ICE 0x34 62 63 64 #define MPIC_IN_DOORBELL 0x78 65 #define MPIC_IN_DOORBELL_MASK 0x7c 66 #define MPIC_CTP 0xb0 67 #define MPIC_CTP 0xb0 68 #define MPIC_IIACK 0xb4 69 #define MPIC_ISM 0xb8 70 #define MPIC_ICM 0xbc 71 #define MPIC_ERR_MASK 0xec0 72 73 struct mv_mpic_softc { 74 struct resource * mpic_res[2]; 75 bus_space_tag_t mpic_bst; 76 bus_space_handle_t mpic_bsh; 77 bus_space_tag_t cpu_bst; 78 bus_space_handle_t cpu_bsh; 79 int mpic_high_regs; 80 int mpic_error_regs; 81 }; 82 83 static struct resource_spec mv_mpic_spec[] = { 84 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 85 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 86 { -1, 0 } 87 }; 88 89 static struct mv_mpic_softc *mv_mpic_sc = NULL; 90 91 void mpic_send_ipi(int cpus, u_int ipi); 92 93 static int mv_mpic_probe(device_t); 94 static int mv_mpic_attach(device_t); 95 uint32_t mv_mpic_get_cause(void); 96 uint32_t mv_mpic_get_cause_err(void); 97 static void arm_mask_irq_err(uintptr_t); 98 static void arm_unmask_irq_err(uintptr_t); 99 100 #define MPIC_CPU_WRITE(softc, reg, val) \ 101 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 102 #define MPIC_CPU_READ(softc, reg) \ 103 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 104 105 static int 106 mv_mpic_probe(device_t dev) 107 { 108 109 if (!ofw_bus_is_compatible(dev, "mrvl,mpic")) 110 return (ENXIO); 111 112 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 113 return (0); 114 } 115 116 static int 117 mv_mpic_attach(device_t dev) 118 { 119 struct mv_mpic_softc *sc; 120 int error; 121 122 sc = (struct mv_mpic_softc *)device_get_softc(dev); 123 124 if (mv_mpic_sc != NULL) 125 return (ENXIO); 126 mv_mpic_sc = sc; 127 128 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 129 if (error) { 130 device_printf(dev, "could not allocate resources\n"); 131 return (ENXIO); 132 } 133 134 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 135 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 136 137 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 138 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 139 140 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 141 MPIC_CTRL, 1); 142 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 143 144 return (0); 145 } 146 147 static device_method_t mv_mpic_methods[] = { 148 DEVMETHOD(device_probe, mv_mpic_probe), 149 DEVMETHOD(device_attach, mv_mpic_attach), 150 { 0, 0 } 151 }; 152 153 static driver_t mv_mpic_driver = { 154 "mpic", 155 mv_mpic_methods, 156 sizeof(struct mv_mpic_softc), 157 }; 158 159 static devclass_t mv_mpic_devclass; 160 161 DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0); 162 163 int 164 arm_get_next_irq(int last) 165 { 166 u_int irq, next = -1; 167 168 irq = mv_mpic_get_cause() & IRQ_MASK; 169 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 170 171 if (irq != IRQ_MASK) { 172 if (irq == IRQ_ERR) 173 irq = mv_mpic_get_cause_err(); 174 next = irq; 175 } 176 177 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 178 return (next); 179 } 180 181 /* 182 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 183 * by ISM/ICM and remove access to ICE in masking operation 184 */ 185 void 186 arm_mask_irq(uintptr_t nb) 187 { 188 189 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1); 190 191 if (nb < MAIN_IRQS) { 192 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 193 MPIC_ICE, nb); 194 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 195 } else 196 arm_mask_irq_err(nb); 197 } 198 199 200 static void 201 arm_mask_irq_err(uintptr_t nb) 202 { 203 uint32_t mask; 204 uint8_t bit_off; 205 206 bit_off = nb - MAIN_IRQS; 207 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 208 mask &= ~(1 << bit_off); 209 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 210 } 211 212 void 213 arm_unmask_irq(uintptr_t nb) 214 { 215 216 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 217 218 if (nb < MAIN_IRQS) { 219 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 220 MPIC_ISE, nb); 221 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 222 } else 223 arm_unmask_irq_err(nb); 224 225 if (nb == 0) 226 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DOORBELL_MASK, 0xffffffff); 227 } 228 229 void 230 arm_unmask_irq_err(uintptr_t nb) 231 { 232 uint32_t mask; 233 uint8_t bit_off; 234 235 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 236 MPIC_ISE, IRQ_ERR); 237 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, IRQ_ERR); 238 239 bit_off = nb - MAIN_IRQS; 240 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 241 mask |= (1 << bit_off); 242 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 243 } 244 245 uint32_t 246 mv_mpic_get_cause(void) 247 { 248 249 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 250 } 251 252 uint32_t 253 mv_mpic_get_cause_err(void) 254 { 255 uint32_t err_cause; 256 uint8_t bit_off; 257 258 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 259 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 260 261 if (err_cause) 262 bit_off = ffs(err_cause) - 1; 263 else 264 return (-1); 265 return (MAIN_IRQS + bit_off); 266 } 267 268 #if defined(SMP) 269 void 270 pic_ipi_send(cpuset_t cpus, u_int ipi) 271 { 272 uint32_t val, i; 273 274 val = 0x00000000; 275 for (i = 0; i < MAXCPU; i++) 276 if (CPU_ISSET(i, &cpus)) 277 val |= (1 << (8 + i)); 278 val |= ipi; 279 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 280 MPIC_SOFT_INT, val); 281 } 282 283 int 284 pic_ipi_get(int i __unused) 285 { 286 uint32_t val; 287 288 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DOORBELL); 289 if (val) 290 return (ffs(val) - 1); 291 292 return (0x3ff); 293 } 294 295 void 296 pic_ipi_clear(int ipi) 297 { 298 uint32_t val; 299 300 val = ~(1 << ipi); 301 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DOORBELL, val); 302 } 303 304 #endif 305