1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/cpuset.h> 43 #include <sys/ktr.h> 44 #include <sys/kdb.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/cpufunc.h> 54 #include <machine/smp.h> 55 56 #include <arm/mv/mvvar.h> 57 #include <arm/mv/mvreg.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/fdt/fdt_common.h> 62 63 #ifdef INTRNG 64 #include "pic_if.h" 65 #endif 66 67 #ifdef DEBUG 68 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 69 printf(fmt,##args); } while (0) 70 #else 71 #define debugf(fmt, args...) 72 #endif 73 74 #define MPIC_INT_ERR 4 75 #define MPIC_INT_MSI 96 76 77 #define MPIC_IRQ_MASK 0x3ff 78 79 #define MPIC_CTRL 0x0 80 #define MPIC_SOFT_INT 0x4 81 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 82 #define MPIC_ERR_CAUSE 0x20 83 #define MPIC_ISE 0x30 84 #define MPIC_ICE 0x34 85 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 86 87 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 88 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 89 90 #define MPIC_IN_DRBL 0x08 91 #define MPIC_IN_DRBL_MASK 0x0c 92 #define MPIC_PPI_CAUSE 0x10 93 #define MPIC_CTP 0x40 94 #define MPIC_IIACK 0x44 95 #define MPIC_ISM 0x48 96 #define MPIC_ICM 0x4c 97 #define MPIC_ERR_MASK 0xe50 98 99 #define MPIC_PPI 32 100 101 #ifdef INTRNG 102 struct mv_mpic_irqsrc { 103 struct intr_irqsrc mmi_isrc; 104 u_int mmi_irq; 105 }; 106 #endif 107 108 struct mv_mpic_softc { 109 device_t sc_dev; 110 struct resource * mpic_res[4]; 111 bus_space_tag_t mpic_bst; 112 bus_space_handle_t mpic_bsh; 113 bus_space_tag_t cpu_bst; 114 bus_space_handle_t cpu_bsh; 115 bus_space_tag_t drbl_bst; 116 bus_space_handle_t drbl_bsh; 117 struct mtx mtx; 118 #ifdef INTRNG 119 struct mv_mpic_irqsrc * mpic_isrcs; 120 #endif 121 int nirqs; 122 void * intr_hand; 123 }; 124 125 static struct resource_spec mv_mpic_spec[] = { 126 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 127 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 128 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 130 { -1, 0 } 131 }; 132 133 static struct ofw_compat_data compat_data[] = { 134 {"mrvl,mpic", true}, 135 {"marvell,mpic", true}, 136 {NULL, false} 137 }; 138 139 static struct mv_mpic_softc *mv_mpic_sc = NULL; 140 141 void mpic_send_ipi(int cpus, u_int ipi); 142 143 static int mv_mpic_probe(device_t); 144 static int mv_mpic_attach(device_t); 145 uint32_t mv_mpic_get_cause(void); 146 uint32_t mv_mpic_get_cause_err(void); 147 uint32_t mv_mpic_get_msi(void); 148 static void mpic_unmask_irq(uintptr_t nb); 149 static void mpic_mask_irq(uintptr_t nb); 150 static void mpic_mask_irq_err(uintptr_t nb); 151 static void mpic_unmask_irq_err(uintptr_t nb); 152 static int mpic_intr(void *arg); 153 static void mpic_unmask_msi(void); 154 #ifndef INTRNG 155 static void arm_mask_irq_err(uintptr_t); 156 static void arm_unmask_irq_err(uintptr_t); 157 #endif 158 159 #define MPIC_WRITE(softc, reg, val) \ 160 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 161 #define MPIC_READ(softc, reg) \ 162 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 163 164 #define MPIC_CPU_WRITE(softc, reg, val) \ 165 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 166 #define MPIC_CPU_READ(softc, reg) \ 167 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 168 169 #define MPIC_DRBL_WRITE(softc, reg, val) \ 170 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 171 #define MPIC_DRBL_READ(softc, reg) \ 172 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 173 174 static int 175 mv_mpic_probe(device_t dev) 176 { 177 178 if (!ofw_bus_status_okay(dev)) 179 return (ENXIO); 180 181 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 182 return (ENXIO); 183 184 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 185 return (0); 186 } 187 188 #ifdef INTRNG 189 static int 190 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 191 { 192 int error; 193 uint32_t irq; 194 struct intr_irqsrc *isrc; 195 const char *name; 196 197 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 198 M_WAITOK | M_ZERO); 199 200 name = device_get_nameunit(sc->sc_dev); 201 for (irq = 0; irq < sc->nirqs; irq++) { 202 sc->mpic_isrcs[irq].mmi_irq = irq; 203 204 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 205 if (irq < MPIC_PPI) { 206 error = intr_isrc_register(isrc, sc->sc_dev, 207 INTR_ISRCF_PPI, "%s", name); 208 } else { 209 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 210 name); 211 } 212 if (error != 0) { 213 /* XXX call intr_isrc_deregister() */ 214 device_printf(sc->sc_dev, "%s failed", __func__); 215 return (error); 216 } 217 } 218 return (0); 219 } 220 #endif 221 222 static int 223 mv_mpic_attach(device_t dev) 224 { 225 struct mv_mpic_softc *sc; 226 int error; 227 uint32_t val; 228 229 sc = (struct mv_mpic_softc *)device_get_softc(dev); 230 231 if (mv_mpic_sc != NULL) 232 return (ENXIO); 233 mv_mpic_sc = sc; 234 235 sc->sc_dev = dev; 236 237 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 238 239 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 240 if (error) { 241 device_printf(dev, "could not allocate resources\n"); 242 return (ENXIO); 243 } 244 #ifdef INTRNG 245 if (sc->mpic_res[3] == NULL) 246 device_printf(dev, "No interrupt to use.\n"); 247 else 248 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 249 mpic_intr, NULL, sc, &sc->intr_hand); 250 #endif 251 252 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 253 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 254 255 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 256 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 257 258 if (sc->mpic_res[2] != NULL) { 259 /* This is required only if MSIs are used. */ 260 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 261 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 262 } 263 264 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 265 MPIC_CTRL, 1); 266 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 267 268 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 269 sc->nirqs = MPIC_CTRL_NIRQS(val); 270 271 #ifdef INTRNG 272 if (mv_mpic_register_isrcs(sc) != 0) { 273 device_printf(dev, "could not register PIC ISRCs\n"); 274 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 275 return (ENXIO); 276 } 277 if (intr_pic_register(dev, OF_xref_from_device(dev)) != 0) { 278 device_printf(dev, "could not register PIC\n"); 279 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 280 return (ENXIO); 281 } 282 #endif 283 284 mpic_unmask_msi(); 285 286 return (0); 287 } 288 289 #ifdef INTRNG 290 static int 291 mpic_intr(void *arg) 292 { 293 struct mv_mpic_softc *sc; 294 uint32_t cause, irqsrc; 295 unsigned int irq; 296 u_int cpuid; 297 298 sc = arg; 299 cpuid = PCPU_GET(cpuid); 300 irq = 0; 301 302 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 303 cause >>= 1, irq++) { 304 if (cause & 1) { 305 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 306 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 307 continue; 308 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 309 curthread->td_intr_frame) != 0) { 310 mpic_mask_irq(irq); 311 device_printf(sc->sc_dev, "Stray irq %u " 312 "disabled\n", irq); 313 } 314 } 315 } 316 317 return (FILTER_HANDLED); 318 } 319 320 static void 321 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 322 { 323 u_int irq; 324 325 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 326 mpic_mask_irq(irq); 327 } 328 329 static void 330 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 331 { 332 u_int irq; 333 334 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 335 mpic_unmask_irq(irq); 336 } 337 338 static int 339 mpic_map_intr(device_t dev, struct intr_map_data *data, 340 struct intr_irqsrc **isrcp) 341 { 342 struct mv_mpic_softc *sc; 343 344 sc = device_get_softc(dev); 345 346 if (data->type != INTR_MAP_DATA_FDT || data->fdt.ncells !=1 || 347 data->fdt.cells[0] >= sc->nirqs) 348 return (EINVAL); 349 350 *isrcp = &sc->mpic_isrcs[data->fdt.cells[0]].mmi_isrc; 351 return (0); 352 } 353 354 static void 355 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 356 { 357 358 mpic_disable_intr(dev, isrc); 359 } 360 361 static void 362 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 363 { 364 365 mpic_enable_intr(dev, isrc); 366 } 367 #endif 368 369 static device_method_t mv_mpic_methods[] = { 370 DEVMETHOD(device_probe, mv_mpic_probe), 371 DEVMETHOD(device_attach, mv_mpic_attach), 372 373 #ifdef INTRNG 374 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 375 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 376 DEVMETHOD(pic_map_intr, mpic_map_intr), 377 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 378 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 379 #endif 380 { 0, 0 } 381 }; 382 383 static driver_t mv_mpic_driver = { 384 "mpic", 385 mv_mpic_methods, 386 sizeof(struct mv_mpic_softc), 387 }; 388 389 static devclass_t mv_mpic_devclass; 390 391 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0, 392 BUS_PASS_INTERRUPT); 393 394 #ifndef INTRNG 395 int 396 arm_get_next_irq(int last) 397 { 398 u_int irq, next = -1; 399 400 irq = mv_mpic_get_cause() & MPIC_IRQ_MASK; 401 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 402 403 if (irq != MPIC_IRQ_MASK) { 404 if (irq == MPIC_INT_ERR) 405 irq = mv_mpic_get_cause_err(); 406 if (irq == MPIC_INT_MSI) 407 irq = mv_mpic_get_msi(); 408 next = irq; 409 } 410 411 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 412 return (next); 413 } 414 415 /* 416 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 417 * by ISM/ICM and remove access to ICE in masking operation 418 */ 419 void 420 arm_mask_irq(uintptr_t nb) 421 { 422 423 mpic_mask_irq(nb); 424 } 425 426 427 static void 428 arm_mask_irq_err(uintptr_t nb) 429 { 430 431 mpic_mask_irq_err(nb); 432 } 433 434 void 435 arm_unmask_irq(uintptr_t nb) 436 { 437 438 mpic_unmask_irq(nb); 439 } 440 441 void 442 arm_unmask_irq_err(uintptr_t nb) 443 { 444 445 mpic_unmask_irq_err(nb); 446 } 447 #endif 448 449 static void 450 mpic_unmask_msi(void) 451 { 452 453 mpic_unmask_irq(MPIC_INT_MSI); 454 } 455 456 static void 457 mpic_unmask_irq_err(uintptr_t nb) 458 { 459 uint32_t mask; 460 uint8_t bit_off; 461 462 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 463 MPIC_ISE, MPIC_INT_ERR); 464 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 465 466 bit_off = nb - ERR_IRQ; 467 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 468 mask |= (1 << bit_off); 469 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 470 } 471 472 static void 473 mpic_mask_irq_err(uintptr_t nb) 474 { 475 uint32_t mask; 476 uint8_t bit_off; 477 478 bit_off = nb - ERR_IRQ; 479 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 480 mask &= ~(1 << bit_off); 481 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 482 } 483 484 static void 485 mpic_unmask_irq(uintptr_t nb) 486 { 487 488 if (nb < ERR_IRQ) { 489 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 490 MPIC_ISE, nb); 491 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 492 } else if (nb < MSI_IRQ) 493 mpic_unmask_irq_err(nb); 494 495 if (nb == 0) 496 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 497 } 498 499 static void 500 mpic_mask_irq(uintptr_t nb) 501 { 502 503 if (nb < ERR_IRQ) { 504 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 505 MPIC_ICE, nb); 506 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 507 } else if (nb < MSI_IRQ) 508 mpic_mask_irq_err(nb); 509 } 510 511 uint32_t 512 mv_mpic_get_cause(void) 513 { 514 515 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 516 } 517 518 uint32_t 519 mv_mpic_get_cause_err(void) 520 { 521 uint32_t err_cause; 522 uint8_t bit_off; 523 524 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 525 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 526 527 if (err_cause) 528 bit_off = ffs(err_cause) - 1; 529 else 530 return (-1); 531 532 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 533 return (ERR_IRQ + bit_off); 534 } 535 536 uint32_t 537 mv_mpic_get_msi(void) 538 { 539 uint32_t cause; 540 uint8_t bit_off; 541 542 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 543 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 544 545 if (cause) 546 bit_off = ffs(cause) - 1; 547 else 548 return (-1); 549 550 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 551 552 cause &= ~(1 << bit_off); 553 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 554 555 return (MSI_IRQ + bit_off); 556 } 557 558 int 559 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 560 { 561 u_long phys, base, size; 562 phandle_t node; 563 int error; 564 565 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 566 567 /* Get physical addres of register space */ 568 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 569 if (error) { 570 printf("%s: Cannot get register physical address, err:%d", 571 __func__, error); 572 return (error); 573 } 574 575 /* Get offset of MPIC register space */ 576 error = fdt_regsize(node, &base, &size); 577 if (error) { 578 printf("%s: Cannot get MPIC register offset, err:%d", 579 __func__, error); 580 return (error); 581 } 582 583 *addr = phys + base + MPIC_SOFT_INT; 584 *data = MPIC_SOFT_INT_DRBL1 | irq; 585 586 return (0); 587 } 588 589 590 #if defined(SMP) && defined(SOC_MV_ARMADAXP) 591 void 592 intr_pic_init_secondary(void) 593 { 594 } 595 596 void 597 pic_ipi_send(cpuset_t cpus, u_int ipi) 598 { 599 uint32_t val, i; 600 601 val = 0x00000000; 602 for (i = 0; i < MAXCPU; i++) 603 if (CPU_ISSET(i, &cpus)) 604 val |= (1 << (8 + i)); 605 val |= ipi; 606 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 607 MPIC_SOFT_INT, val); 608 } 609 610 int 611 pic_ipi_read(int i __unused) 612 { 613 uint32_t val; 614 int ipi; 615 616 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 617 if (val) { 618 ipi = ffs(val) - 1; 619 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 620 return (ipi); 621 } 622 623 return (0x3ff); 624 } 625 626 void 627 pic_ipi_clear(int ipi) 628 { 629 } 630 631 #endif 632