1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/cpuset.h> 43 #include <sys/ktr.h> 44 #include <sys/kdb.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/smp.h> 54 55 #include <arm/mv/mvvar.h> 56 #include <arm/mv/mvreg.h> 57 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_bus_subr.h> 60 #include <dev/fdt/fdt_common.h> 61 62 #ifdef INTRNG 63 #include "pic_if.h" 64 #endif 65 66 #ifdef DEBUG 67 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 68 printf(fmt,##args); } while (0) 69 #else 70 #define debugf(fmt, args...) 71 #endif 72 73 #define MPIC_INT_ERR 4 74 #define MPIC_INT_MSI 96 75 76 #define MPIC_IRQ_MASK 0x3ff 77 78 #define MPIC_CTRL 0x0 79 #define MPIC_SOFT_INT 0x4 80 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 81 #define MPIC_ERR_CAUSE 0x20 82 #define MPIC_ISE 0x30 83 #define MPIC_ICE 0x34 84 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 85 86 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 87 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 88 89 #define MPIC_IN_DRBL 0x08 90 #define MPIC_IN_DRBL_MASK 0x0c 91 #define MPIC_PPI_CAUSE 0x10 92 #define MPIC_CTP 0x40 93 #define MPIC_IIACK 0x44 94 #define MPIC_ISM 0x48 95 #define MPIC_ICM 0x4c 96 #define MPIC_ERR_MASK 0xe50 97 98 #define MPIC_PPI 32 99 100 #ifdef INTRNG 101 struct mv_mpic_irqsrc { 102 struct intr_irqsrc mmi_isrc; 103 u_int mmi_irq; 104 }; 105 #endif 106 107 struct mv_mpic_softc { 108 device_t sc_dev; 109 struct resource * mpic_res[4]; 110 bus_space_tag_t mpic_bst; 111 bus_space_handle_t mpic_bsh; 112 bus_space_tag_t cpu_bst; 113 bus_space_handle_t cpu_bsh; 114 bus_space_tag_t drbl_bst; 115 bus_space_handle_t drbl_bsh; 116 struct mtx mtx; 117 #ifdef INTRNG 118 struct mv_mpic_irqsrc * mpic_isrcs; 119 #endif 120 int nirqs; 121 void * intr_hand; 122 }; 123 124 static struct resource_spec mv_mpic_spec[] = { 125 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 126 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 127 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 128 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 129 { -1, 0 } 130 }; 131 132 static struct ofw_compat_data compat_data[] = { 133 {"mrvl,mpic", true}, 134 {"marvell,mpic", true}, 135 {NULL, false} 136 }; 137 138 static struct mv_mpic_softc *mv_mpic_sc = NULL; 139 140 void mpic_send_ipi(int cpus, u_int ipi); 141 142 static int mv_mpic_probe(device_t); 143 static int mv_mpic_attach(device_t); 144 uint32_t mv_mpic_get_cause(void); 145 uint32_t mv_mpic_get_cause_err(void); 146 uint32_t mv_mpic_get_msi(void); 147 static void mpic_unmask_irq(uintptr_t nb); 148 static void mpic_mask_irq(uintptr_t nb); 149 static void mpic_mask_irq_err(uintptr_t nb); 150 static void mpic_unmask_irq_err(uintptr_t nb); 151 static boolean_t mpic_irq_is_percpu(uintptr_t); 152 #ifdef INTRNG 153 static int mpic_intr(void *arg); 154 #endif 155 static void mpic_unmask_msi(void); 156 157 #define MPIC_WRITE(softc, reg, val) \ 158 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 159 #define MPIC_READ(softc, reg) \ 160 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 161 162 #define MPIC_CPU_WRITE(softc, reg, val) \ 163 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 164 #define MPIC_CPU_READ(softc, reg) \ 165 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 166 167 #define MPIC_DRBL_WRITE(softc, reg, val) \ 168 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 169 #define MPIC_DRBL_READ(softc, reg) \ 170 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 171 172 static int 173 mv_mpic_probe(device_t dev) 174 { 175 176 if (!ofw_bus_status_okay(dev)) 177 return (ENXIO); 178 179 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 180 return (ENXIO); 181 182 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 183 return (0); 184 } 185 186 #ifdef INTRNG 187 static int 188 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 189 { 190 int error; 191 uint32_t irq; 192 struct intr_irqsrc *isrc; 193 const char *name; 194 195 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 196 M_WAITOK | M_ZERO); 197 198 name = device_get_nameunit(sc->sc_dev); 199 for (irq = 0; irq < sc->nirqs; irq++) { 200 sc->mpic_isrcs[irq].mmi_irq = irq; 201 202 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 203 if (irq < MPIC_PPI) { 204 error = intr_isrc_register(isrc, sc->sc_dev, 205 INTR_ISRCF_PPI, "%s", name); 206 } else { 207 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 208 name); 209 } 210 if (error != 0) { 211 /* XXX call intr_isrc_deregister() */ 212 device_printf(sc->sc_dev, "%s failed", __func__); 213 return (error); 214 } 215 } 216 return (0); 217 } 218 #endif 219 220 static int 221 mv_mpic_attach(device_t dev) 222 { 223 struct mv_mpic_softc *sc; 224 int error; 225 uint32_t val; 226 227 sc = (struct mv_mpic_softc *)device_get_softc(dev); 228 229 if (mv_mpic_sc != NULL) 230 return (ENXIO); 231 mv_mpic_sc = sc; 232 233 sc->sc_dev = dev; 234 235 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 236 237 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 238 if (error) { 239 device_printf(dev, "could not allocate resources\n"); 240 return (ENXIO); 241 } 242 #ifdef INTRNG 243 if (sc->mpic_res[3] == NULL) 244 device_printf(dev, "No interrupt to use.\n"); 245 else 246 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 247 mpic_intr, NULL, sc, &sc->intr_hand); 248 #endif 249 250 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 251 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 252 253 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 254 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 255 256 if (sc->mpic_res[2] != NULL) { 257 /* This is required only if MSIs are used. */ 258 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 259 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 260 } 261 262 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1); 263 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 264 265 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 266 sc->nirqs = MPIC_CTRL_NIRQS(val); 267 268 #ifdef INTRNG 269 if (mv_mpic_register_isrcs(sc) != 0) { 270 device_printf(dev, "could not register PIC ISRCs\n"); 271 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 272 return (ENXIO); 273 } 274 275 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev); 276 277 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { 278 device_printf(dev, "could not register PIC\n"); 279 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 280 return (ENXIO); 281 } 282 #endif 283 284 mpic_unmask_msi(); 285 286 return (0); 287 } 288 289 #ifdef INTRNG 290 static int 291 mpic_intr(void *arg) 292 { 293 struct mv_mpic_softc *sc; 294 uint32_t cause, irqsrc; 295 unsigned int irq; 296 u_int cpuid; 297 298 sc = arg; 299 cpuid = PCPU_GET(cpuid); 300 irq = 0; 301 302 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 303 cause >>= 1, irq++) { 304 if (cause & 1) { 305 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 306 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 307 continue; 308 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 309 curthread->td_intr_frame) != 0) { 310 mpic_mask_irq(irq); 311 device_printf(sc->sc_dev, "Stray irq %u " 312 "disabled\n", irq); 313 } 314 } 315 } 316 317 return (FILTER_HANDLED); 318 } 319 320 static void 321 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 322 { 323 u_int irq; 324 325 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 326 mpic_mask_irq(irq); 327 } 328 329 static void 330 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 331 { 332 u_int irq; 333 334 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 335 mpic_unmask_irq(irq); 336 } 337 338 static int 339 mpic_map_intr(device_t dev, struct intr_map_data *data, 340 struct intr_irqsrc **isrcp) 341 { 342 struct intr_map_data_fdt *daf; 343 struct mv_mpic_softc *sc; 344 345 if (data->type != INTR_MAP_DATA_FDT) 346 return (ENOTSUP); 347 348 sc = device_get_softc(dev); 349 daf = (struct intr_map_data_fdt *)data; 350 351 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs) 352 return (EINVAL); 353 354 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc; 355 return (0); 356 } 357 358 static void 359 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 360 { 361 362 mpic_disable_intr(dev, isrc); 363 } 364 365 static void 366 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 367 { 368 369 mpic_enable_intr(dev, isrc); 370 } 371 372 static void 373 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc) 374 { 375 } 376 #endif 377 378 static device_method_t mv_mpic_methods[] = { 379 DEVMETHOD(device_probe, mv_mpic_probe), 380 DEVMETHOD(device_attach, mv_mpic_attach), 381 382 #ifdef INTRNG 383 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 384 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 385 DEVMETHOD(pic_map_intr, mpic_map_intr), 386 DEVMETHOD(pic_post_filter, mpic_post_filter), 387 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 388 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 389 #endif 390 { 0, 0 } 391 }; 392 393 static driver_t mv_mpic_driver = { 394 "mpic", 395 mv_mpic_methods, 396 sizeof(struct mv_mpic_softc), 397 }; 398 399 static devclass_t mv_mpic_devclass; 400 401 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0, 402 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 403 404 #ifndef INTRNG 405 int 406 arm_get_next_irq(int last) 407 { 408 u_int irq, next = -1; 409 410 irq = mv_mpic_get_cause() & MPIC_IRQ_MASK; 411 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 412 413 if (irq != MPIC_IRQ_MASK) { 414 if (irq == MPIC_INT_ERR) 415 irq = mv_mpic_get_cause_err(); 416 if (irq == MPIC_INT_MSI) 417 irq = mv_mpic_get_msi(); 418 next = irq; 419 } 420 421 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 422 return (next); 423 } 424 425 /* 426 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 427 * by ISM/ICM and remove access to ICE in masking operation 428 */ 429 void 430 arm_mask_irq(uintptr_t nb) 431 { 432 433 mpic_mask_irq(nb); 434 } 435 436 void 437 arm_unmask_irq(uintptr_t nb) 438 { 439 440 mpic_unmask_irq(nb); 441 } 442 #endif 443 444 static void 445 mpic_unmask_msi(void) 446 { 447 448 mpic_unmask_irq(MPIC_INT_MSI); 449 } 450 451 static void 452 mpic_unmask_irq_err(uintptr_t nb) 453 { 454 uint32_t mask; 455 uint8_t bit_off; 456 457 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR); 458 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 459 460 bit_off = nb - ERR_IRQ; 461 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 462 mask |= (1 << bit_off); 463 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 464 } 465 466 static void 467 mpic_mask_irq_err(uintptr_t nb) 468 { 469 uint32_t mask; 470 uint8_t bit_off; 471 472 bit_off = nb - ERR_IRQ; 473 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 474 mask &= ~(1 << bit_off); 475 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 476 } 477 478 static boolean_t 479 mpic_irq_is_percpu(uintptr_t nb) 480 { 481 if (nb < MPIC_PPI) 482 return TRUE; 483 484 return FALSE; 485 } 486 487 static void 488 mpic_unmask_irq(uintptr_t nb) 489 { 490 491 if (mpic_irq_is_percpu(nb)) 492 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 493 else if (nb < ERR_IRQ) 494 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); 495 else if (nb < MSI_IRQ) 496 mpic_unmask_irq_err(nb); 497 498 if (nb == 0) 499 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 500 } 501 502 static void 503 mpic_mask_irq(uintptr_t nb) 504 { 505 506 if (mpic_irq_is_percpu(nb)) 507 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 508 else if (nb < ERR_IRQ) 509 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); 510 else if (nb < MSI_IRQ) 511 mpic_mask_irq_err(nb); 512 } 513 514 uint32_t 515 mv_mpic_get_cause(void) 516 { 517 518 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 519 } 520 521 uint32_t 522 mv_mpic_get_cause_err(void) 523 { 524 uint32_t err_cause; 525 uint8_t bit_off; 526 527 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE); 528 529 if (err_cause) 530 bit_off = ffs(err_cause) - 1; 531 else 532 return (-1); 533 534 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 535 return (ERR_IRQ + bit_off); 536 } 537 538 uint32_t 539 mv_mpic_get_msi(void) 540 { 541 uint32_t cause; 542 uint8_t bit_off; 543 544 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 545 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 546 547 if (cause) 548 bit_off = ffs(cause) - 1; 549 else 550 return (-1); 551 552 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 553 554 cause &= ~(1 << bit_off); 555 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 556 557 return (MSI_IRQ + bit_off); 558 } 559 560 int 561 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 562 { 563 u_long phys, base, size; 564 phandle_t node; 565 int error; 566 567 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 568 569 /* Get physical address of register space */ 570 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 571 if (error) { 572 printf("%s: Cannot get register physical address, err:%d", 573 __func__, error); 574 return (error); 575 } 576 577 /* Get offset of MPIC register space */ 578 error = fdt_regsize(node, &base, &size); 579 if (error) { 580 printf("%s: Cannot get MPIC register offset, err:%d", 581 __func__, error); 582 return (error); 583 } 584 585 *addr = phys + base + MPIC_SOFT_INT; 586 *data = MPIC_SOFT_INT_DRBL1 | irq; 587 588 return (0); 589 } 590 591 592 #if defined(SMP) && defined(SOC_MV_ARMADAXP) 593 void 594 intr_pic_init_secondary(void) 595 { 596 } 597 598 void 599 pic_ipi_send(cpuset_t cpus, u_int ipi) 600 { 601 uint32_t val, i; 602 603 val = 0x00000000; 604 for (i = 0; i < MAXCPU; i++) 605 if (CPU_ISSET(i, &cpus)) 606 val |= (1 << (8 + i)); 607 val |= ipi; 608 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val); 609 } 610 611 int 612 pic_ipi_read(int i __unused) 613 { 614 uint32_t val; 615 int ipi; 616 617 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 618 if (val) { 619 ipi = ffs(val) - 1; 620 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 621 return (ipi); 622 } 623 624 return (0x3ff); 625 } 626 627 void 628 pic_ipi_clear(int ipi) 629 { 630 } 631 632 #endif 633