1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/cpuset.h> 41 #include <sys/ktr.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 #include <machine/cpufunc.h> 48 #include <machine/smp.h> 49 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 #include <dev/fdt/fdt_common.h> 55 56 #ifdef DEBUG 57 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 58 printf(fmt,##args); } while (0) 59 #else 60 #define debugf(fmt, args...) 61 #endif 62 63 #define MPIC_INT_ERR 4 64 #define MPIC_INT_MSI 96 65 66 #define IRQ_MASK 0x3ff 67 68 #define MPIC_CTRL 0x0 69 #define MPIC_SOFT_INT 0x4 70 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 71 #define MPIC_ERR_CAUSE 0x20 72 #define MPIC_ISE 0x30 73 #define MPIC_ICE 0x34 74 75 76 #define MPIC_IN_DRBL 0x78 77 #define MPIC_IN_DRBL_MASK 0x7c 78 #define MPIC_CTP 0xb0 79 #define MPIC_CTP 0xb0 80 #define MPIC_IIACK 0xb4 81 #define MPIC_ISM 0xb8 82 #define MPIC_ICM 0xbc 83 #define MPIC_ERR_MASK 0xec0 84 85 struct mv_mpic_softc { 86 device_t sc_dev; 87 struct resource * mpic_res[3]; 88 bus_space_tag_t mpic_bst; 89 bus_space_handle_t mpic_bsh; 90 bus_space_tag_t cpu_bst; 91 bus_space_handle_t cpu_bsh; 92 bus_space_tag_t drbl_bst; 93 bus_space_handle_t drbl_bsh; 94 }; 95 96 static struct resource_spec mv_mpic_spec[] = { 97 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 98 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 99 { SYS_RES_MEMORY, 2, RF_ACTIVE }, 100 { -1, 0 } 101 }; 102 103 static struct mv_mpic_softc *mv_mpic_sc = NULL; 104 105 void mpic_send_ipi(int cpus, u_int ipi); 106 107 static int mv_mpic_probe(device_t); 108 static int mv_mpic_attach(device_t); 109 uint32_t mv_mpic_get_cause(void); 110 uint32_t mv_mpic_get_cause_err(void); 111 uint32_t mv_mpic_get_msi(void); 112 static void arm_mask_irq_err(uintptr_t); 113 static void arm_unmask_irq_err(uintptr_t); 114 static void arm_unmask_msi(void); 115 116 #define MPIC_CPU_WRITE(softc, reg, val) \ 117 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 118 #define MPIC_CPU_READ(softc, reg) \ 119 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 120 121 #define MPIC_DRBL_WRITE(softc, reg, val) \ 122 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 123 #define MPIC_DRBL_READ(softc, reg) \ 124 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 125 126 static int 127 mv_mpic_probe(device_t dev) 128 { 129 130 if (!ofw_bus_is_compatible(dev, "mrvl,mpic")) 131 return (ENXIO); 132 133 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 134 return (0); 135 } 136 137 static int 138 mv_mpic_attach(device_t dev) 139 { 140 struct mv_mpic_softc *sc; 141 int error; 142 143 sc = (struct mv_mpic_softc *)device_get_softc(dev); 144 145 if (mv_mpic_sc != NULL) 146 return (ENXIO); 147 mv_mpic_sc = sc; 148 149 sc->sc_dev = dev; 150 151 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 152 if (error) { 153 device_printf(dev, "could not allocate resources\n"); 154 return (ENXIO); 155 } 156 157 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 158 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 159 160 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 161 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 162 163 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 164 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 165 166 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 167 MPIC_CTRL, 1); 168 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 169 170 arm_unmask_msi(); 171 172 return (0); 173 } 174 175 static device_method_t mv_mpic_methods[] = { 176 DEVMETHOD(device_probe, mv_mpic_probe), 177 DEVMETHOD(device_attach, mv_mpic_attach), 178 { 0, 0 } 179 }; 180 181 static driver_t mv_mpic_driver = { 182 "mpic", 183 mv_mpic_methods, 184 sizeof(struct mv_mpic_softc), 185 }; 186 187 static devclass_t mv_mpic_devclass; 188 189 DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0); 190 191 int 192 arm_get_next_irq(int last) 193 { 194 u_int irq, next = -1; 195 196 irq = mv_mpic_get_cause() & IRQ_MASK; 197 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 198 199 if (irq != IRQ_MASK) { 200 if (irq == MPIC_INT_ERR) 201 irq = mv_mpic_get_cause_err(); 202 if (irq == MPIC_INT_MSI) 203 irq = mv_mpic_get_msi(); 204 next = irq; 205 } 206 207 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 208 return (next); 209 } 210 211 /* 212 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 213 * by ISM/ICM and remove access to ICE in masking operation 214 */ 215 void 216 arm_mask_irq(uintptr_t nb) 217 { 218 219 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 1); 220 221 if (nb < ERR_IRQ) { 222 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 223 MPIC_ICE, nb); 224 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 225 } else if (nb < MSI_IRQ) 226 arm_mask_irq_err(nb); 227 } 228 229 230 static void 231 arm_mask_irq_err(uintptr_t nb) 232 { 233 uint32_t mask; 234 uint8_t bit_off; 235 236 bit_off = nb - ERR_IRQ; 237 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 238 mask &= ~(1 << bit_off); 239 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 240 } 241 242 void 243 arm_unmask_irq(uintptr_t nb) 244 { 245 246 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 247 248 if (nb < ERR_IRQ) { 249 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 250 MPIC_ISE, nb); 251 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 252 } else if (nb < MSI_IRQ) 253 arm_unmask_irq_err(nb); 254 255 if (nb == 0) 256 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 257 } 258 259 void 260 arm_unmask_irq_err(uintptr_t nb) 261 { 262 uint32_t mask; 263 uint8_t bit_off; 264 265 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 266 MPIC_ISE, MPIC_INT_ERR); 267 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 268 269 bit_off = nb - ERR_IRQ; 270 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 271 mask |= (1 << bit_off); 272 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 273 } 274 275 static void 276 arm_unmask_msi(void) 277 { 278 279 arm_unmask_irq(MPIC_INT_MSI); 280 } 281 282 uint32_t 283 mv_mpic_get_cause(void) 284 { 285 286 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 287 } 288 289 uint32_t 290 mv_mpic_get_cause_err(void) 291 { 292 uint32_t err_cause; 293 uint8_t bit_off; 294 295 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 296 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 297 298 if (err_cause) 299 bit_off = ffs(err_cause) - 1; 300 else 301 return (-1); 302 303 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 304 return (ERR_IRQ + bit_off); 305 } 306 307 uint32_t 308 mv_mpic_get_msi(void) 309 { 310 uint32_t cause; 311 uint8_t bit_off; 312 313 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 314 315 if (cause) 316 bit_off = ffs(cause) - 1; 317 else 318 return (-1); 319 320 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 321 322 cause &= ~(1 << bit_off); 323 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 324 325 return (MSI_IRQ + bit_off); 326 } 327 328 int 329 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 330 { 331 u_long phys, base, size; 332 phandle_t node; 333 int error; 334 335 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 336 337 /* Get physical addres of register space */ 338 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 339 if (error) { 340 printf("%s: Cannot get register physical address, err:%d", 341 __func__, error); 342 return (error); 343 } 344 345 /* Get offset of MPIC register space */ 346 error = fdt_regsize(node, &base, &size); 347 if (error) { 348 printf("%s: Cannot get MPIC register offset, err:%d", 349 __func__, error); 350 return (error); 351 } 352 353 *addr = phys + base + MPIC_SOFT_INT; 354 *data = MPIC_SOFT_INT_DRBL1 | irq; 355 356 return (0); 357 } 358 359 #if defined(SMP) 360 void 361 pic_ipi_send(cpuset_t cpus, u_int ipi) 362 { 363 uint32_t val, i; 364 365 val = 0x00000000; 366 for (i = 0; i < MAXCPU; i++) 367 if (CPU_ISSET(i, &cpus)) 368 val |= (1 << (8 + i)); 369 val |= ipi; 370 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 371 MPIC_SOFT_INT, val); 372 } 373 374 int 375 pic_ipi_get(int i __unused) 376 { 377 uint32_t val; 378 379 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 380 if (val) 381 return (ffs(val) - 1); 382 383 return (0x3ff); 384 } 385 386 void 387 pic_ipi_clear(int ipi) 388 { 389 uint32_t val; 390 391 val = ~(1 << ipi); 392 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, val); 393 } 394 395 #endif 396