1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/cpuset.h> 43 #include <sys/ktr.h> 44 #include <sys/kdb.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/proc.h> 50 #include <sys/smp.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 #include <machine/smp.h> 55 56 #include <arm/mv/mvvar.h> 57 #include <arm/mv/mvreg.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/fdt/fdt_common.h> 62 63 #ifdef INTRNG 64 #include "pic_if.h" 65 #endif 66 67 #ifdef DEBUG 68 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 69 printf(fmt,##args); } while (0) 70 #else 71 #define debugf(fmt, args...) 72 #endif 73 74 #define MPIC_INT_LOCAL 3 75 #define MPIC_INT_ERR 4 76 #define MPIC_INT_MSI 96 77 78 #define MPIC_IRQ_MASK 0x3ff 79 80 #define MPIC_CTRL 0x0 81 #define MPIC_SOFT_INT 0x4 82 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 83 #define MPIC_ERR_CAUSE 0x20 84 #define MPIC_ISE 0x30 85 #define MPIC_ICE 0x34 86 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 87 88 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 89 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 90 91 #define MPIC_IN_DRBL 0x08 92 #define MPIC_IN_DRBL_MASK 0x0c 93 #define MPIC_PPI_CAUSE 0x10 94 #define MPIC_CTP 0x40 95 #define MPIC_IIACK 0x44 96 #define MPIC_ISM 0x48 97 #define MPIC_ICM 0x4c 98 #define MPIC_ERR_MASK 0x50 99 #define MPIC_LOCAL_MASK 0x54 100 #define MPIC_CPU(n) (n) * 0x100 101 102 #define MPIC_PPI 32 103 104 #ifdef INTRNG 105 struct mv_mpic_irqsrc { 106 struct intr_irqsrc mmi_isrc; 107 u_int mmi_irq; 108 }; 109 #endif 110 111 struct mv_mpic_softc { 112 device_t sc_dev; 113 struct resource * mpic_res[4]; 114 bus_space_tag_t mpic_bst; 115 bus_space_handle_t mpic_bsh; 116 bus_space_tag_t cpu_bst; 117 bus_space_handle_t cpu_bsh; 118 bus_space_tag_t drbl_bst; 119 bus_space_handle_t drbl_bsh; 120 struct mtx mtx; 121 #ifdef INTRNG 122 struct mv_mpic_irqsrc * mpic_isrcs; 123 #endif 124 int nirqs; 125 void * intr_hand; 126 }; 127 128 static struct resource_spec mv_mpic_spec[] = { 129 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 130 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 131 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 132 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 133 { -1, 0 } 134 }; 135 136 static struct ofw_compat_data compat_data[] = { 137 {"mrvl,mpic", true}, 138 {"marvell,mpic", true}, 139 {NULL, false} 140 }; 141 142 static struct mv_mpic_softc *mv_mpic_sc = NULL; 143 144 void mpic_send_ipi(int cpus, u_int ipi); 145 146 static int mv_mpic_probe(device_t); 147 static int mv_mpic_attach(device_t); 148 uint32_t mv_mpic_get_cause(void); 149 uint32_t mv_mpic_get_cause_err(void); 150 uint32_t mv_mpic_get_msi(void); 151 static void mpic_unmask_irq(uintptr_t nb); 152 static void mpic_mask_irq(uintptr_t nb); 153 static void mpic_mask_irq_err(uintptr_t nb); 154 static void mpic_unmask_irq_err(uintptr_t nb); 155 static boolean_t mpic_irq_is_percpu(uintptr_t); 156 #ifdef INTRNG 157 static int mpic_intr(void *arg); 158 #endif 159 static void mpic_unmask_msi(void); 160 161 #define MPIC_WRITE(softc, reg, val) \ 162 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 163 #define MPIC_READ(softc, reg) \ 164 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 165 166 #define MPIC_CPU_WRITE(softc, reg, val) \ 167 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 168 #define MPIC_CPU_READ(softc, reg) \ 169 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 170 171 #define MPIC_DRBL_WRITE(softc, reg, val) \ 172 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 173 #define MPIC_DRBL_READ(softc, reg) \ 174 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 175 176 static int 177 mv_mpic_probe(device_t dev) 178 { 179 180 if (!ofw_bus_status_okay(dev)) 181 return (ENXIO); 182 183 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 184 return (ENXIO); 185 186 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 187 return (0); 188 } 189 190 #ifdef INTRNG 191 static int 192 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 193 { 194 int error; 195 uint32_t irq; 196 struct intr_irqsrc *isrc; 197 const char *name; 198 199 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 200 M_WAITOK | M_ZERO); 201 202 name = device_get_nameunit(sc->sc_dev); 203 for (irq = 0; irq < sc->nirqs; irq++) { 204 sc->mpic_isrcs[irq].mmi_irq = irq; 205 206 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 207 if (irq < MPIC_PPI) { 208 error = intr_isrc_register(isrc, sc->sc_dev, 209 INTR_ISRCF_PPI, "%s", name); 210 } else { 211 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 212 name); 213 } 214 if (error != 0) { 215 /* XXX call intr_isrc_deregister() */ 216 device_printf(sc->sc_dev, "%s failed", __func__); 217 return (error); 218 } 219 } 220 return (0); 221 } 222 #endif 223 224 static int 225 mv_mpic_attach(device_t dev) 226 { 227 struct mv_mpic_softc *sc; 228 int error; 229 uint32_t val; 230 int cpu; 231 232 sc = (struct mv_mpic_softc *)device_get_softc(dev); 233 234 if (mv_mpic_sc != NULL) 235 return (ENXIO); 236 mv_mpic_sc = sc; 237 238 sc->sc_dev = dev; 239 240 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 241 242 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 243 if (error) { 244 device_printf(dev, "could not allocate resources\n"); 245 return (ENXIO); 246 } 247 #ifdef INTRNG 248 if (sc->mpic_res[3] == NULL) 249 device_printf(dev, "No interrupt to use.\n"); 250 else 251 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 252 mpic_intr, NULL, sc, &sc->intr_hand); 253 #endif 254 255 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 256 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 257 258 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 259 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 260 261 if (sc->mpic_res[2] != NULL) { 262 /* This is required only if MSIs are used. */ 263 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 264 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 265 } 266 267 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1); 268 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 269 270 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 271 sc->nirqs = MPIC_CTRL_NIRQS(val); 272 273 #ifdef INTRNG 274 if (mv_mpic_register_isrcs(sc) != 0) { 275 device_printf(dev, "could not register PIC ISRCs\n"); 276 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 277 return (ENXIO); 278 } 279 280 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev); 281 282 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { 283 device_printf(dev, "could not register PIC\n"); 284 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 285 return (ENXIO); 286 } 287 #endif 288 289 mpic_unmask_msi(); 290 291 /* Unmask CPU performance counters overflow irq */ 292 for (cpu = 0; cpu < mp_ncpus; cpu++) 293 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK, 294 (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc, 295 MPIC_CPU(cpu) + MPIC_LOCAL_MASK)); 296 297 return (0); 298 } 299 300 #ifdef INTRNG 301 static int 302 mpic_intr(void *arg) 303 { 304 struct mv_mpic_softc *sc; 305 uint32_t cause, irqsrc; 306 unsigned int irq; 307 u_int cpuid; 308 309 sc = arg; 310 cpuid = PCPU_GET(cpuid); 311 irq = 0; 312 313 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 314 cause >>= 1, irq++) { 315 if (cause & 1) { 316 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 317 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 318 continue; 319 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 320 curthread->td_intr_frame) != 0) { 321 mpic_mask_irq(irq); 322 device_printf(sc->sc_dev, "Stray irq %u " 323 "disabled\n", irq); 324 } 325 } 326 } 327 328 return (FILTER_HANDLED); 329 } 330 331 static void 332 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 333 { 334 u_int irq; 335 336 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 337 mpic_mask_irq(irq); 338 } 339 340 static void 341 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 342 { 343 u_int irq; 344 345 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 346 mpic_unmask_irq(irq); 347 } 348 349 static int 350 mpic_map_intr(device_t dev, struct intr_map_data *data, 351 struct intr_irqsrc **isrcp) 352 { 353 struct intr_map_data_fdt *daf; 354 struct mv_mpic_softc *sc; 355 356 if (data->type != INTR_MAP_DATA_FDT) 357 return (ENOTSUP); 358 359 sc = device_get_softc(dev); 360 daf = (struct intr_map_data_fdt *)data; 361 362 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs) 363 return (EINVAL); 364 365 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc; 366 return (0); 367 } 368 369 static void 370 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 371 { 372 373 mpic_disable_intr(dev, isrc); 374 } 375 376 static void 377 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 378 { 379 380 mpic_enable_intr(dev, isrc); 381 } 382 383 static void 384 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc) 385 { 386 } 387 #endif 388 389 static device_method_t mv_mpic_methods[] = { 390 DEVMETHOD(device_probe, mv_mpic_probe), 391 DEVMETHOD(device_attach, mv_mpic_attach), 392 393 #ifdef INTRNG 394 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 395 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 396 DEVMETHOD(pic_map_intr, mpic_map_intr), 397 DEVMETHOD(pic_post_filter, mpic_post_filter), 398 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 399 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 400 #endif 401 { 0, 0 } 402 }; 403 404 static driver_t mv_mpic_driver = { 405 "mpic", 406 mv_mpic_methods, 407 sizeof(struct mv_mpic_softc), 408 }; 409 410 static devclass_t mv_mpic_devclass; 411 412 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0, 413 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 414 415 #ifndef INTRNG 416 int 417 arm_get_next_irq(int last) 418 { 419 u_int irq, next = -1; 420 421 irq = mv_mpic_get_cause() & MPIC_IRQ_MASK; 422 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 423 424 if (irq != MPIC_IRQ_MASK) { 425 if (irq == MPIC_INT_ERR) 426 irq = mv_mpic_get_cause_err(); 427 if (irq == MPIC_INT_MSI) 428 irq = mv_mpic_get_msi(); 429 next = irq; 430 } 431 432 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 433 return (next); 434 } 435 436 /* 437 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 438 * by ISM/ICM and remove access to ICE in masking operation 439 */ 440 void 441 arm_mask_irq(uintptr_t nb) 442 { 443 444 mpic_mask_irq(nb); 445 } 446 447 void 448 arm_unmask_irq(uintptr_t nb) 449 { 450 451 mpic_unmask_irq(nb); 452 } 453 #endif 454 455 static void 456 mpic_unmask_msi(void) 457 { 458 459 mpic_unmask_irq(MPIC_INT_MSI); 460 } 461 462 static void 463 mpic_unmask_irq_err(uintptr_t nb) 464 { 465 uint32_t mask; 466 uint8_t bit_off; 467 468 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR); 469 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 470 471 bit_off = nb - ERR_IRQ; 472 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 473 mask |= (1 << bit_off); 474 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 475 } 476 477 static void 478 mpic_mask_irq_err(uintptr_t nb) 479 { 480 uint32_t mask; 481 uint8_t bit_off; 482 483 bit_off = nb - ERR_IRQ; 484 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 485 mask &= ~(1 << bit_off); 486 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 487 } 488 489 static boolean_t 490 mpic_irq_is_percpu(uintptr_t nb) 491 { 492 if (nb < MPIC_PPI) 493 return TRUE; 494 495 return FALSE; 496 } 497 498 static void 499 mpic_unmask_irq(uintptr_t nb) 500 { 501 502 #ifdef SMP 503 int cpu; 504 505 if (nb == MPIC_INT_LOCAL) { 506 for (cpu = 0; cpu < mp_ncpus; cpu++) 507 MPIC_CPU_WRITE(mv_mpic_sc, 508 MPIC_CPU(cpu) + MPIC_ICM, nb); 509 return; 510 } 511 #endif 512 if (mpic_irq_is_percpu(nb)) 513 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 514 else if (nb < ERR_IRQ) 515 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); 516 else if (nb < MSI_IRQ) 517 mpic_unmask_irq_err(nb); 518 519 if (nb == 0) 520 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 521 } 522 523 static void 524 mpic_mask_irq(uintptr_t nb) 525 { 526 527 #ifdef SMP 528 int cpu; 529 530 if (nb == MPIC_INT_LOCAL) { 531 for (cpu = 0; cpu < mp_ncpus; cpu++) 532 MPIC_CPU_WRITE(mv_mpic_sc, 533 MPIC_CPU(cpu) + MPIC_ISM, nb); 534 return; 535 } 536 #endif 537 if (mpic_irq_is_percpu(nb)) 538 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 539 else if (nb < ERR_IRQ) 540 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); 541 else if (nb < MSI_IRQ) 542 mpic_mask_irq_err(nb); 543 } 544 545 uint32_t 546 mv_mpic_get_cause(void) 547 { 548 549 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 550 } 551 552 uint32_t 553 mv_mpic_get_cause_err(void) 554 { 555 uint32_t err_cause; 556 uint8_t bit_off; 557 558 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE); 559 560 if (err_cause) 561 bit_off = ffs(err_cause) - 1; 562 else 563 return (-1); 564 565 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 566 return (ERR_IRQ + bit_off); 567 } 568 569 uint32_t 570 mv_mpic_get_msi(void) 571 { 572 uint32_t cause; 573 uint8_t bit_off; 574 575 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 576 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 577 578 if (cause) 579 bit_off = ffs(cause) - 1; 580 else 581 return (-1); 582 583 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 584 585 cause &= ~(1 << bit_off); 586 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 587 588 return (MSI_IRQ + bit_off); 589 } 590 591 int 592 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 593 { 594 u_long phys, base, size; 595 phandle_t node; 596 int error; 597 598 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 599 600 /* Get physical address of register space */ 601 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 602 if (error) { 603 printf("%s: Cannot get register physical address, err:%d", 604 __func__, error); 605 return (error); 606 } 607 608 /* Get offset of MPIC register space */ 609 error = fdt_regsize(node, &base, &size); 610 if (error) { 611 printf("%s: Cannot get MPIC register offset, err:%d", 612 __func__, error); 613 return (error); 614 } 615 616 *addr = phys + base + MPIC_SOFT_INT; 617 *data = MPIC_SOFT_INT_DRBL1 | irq; 618 619 return (0); 620 } 621 622 623 #if defined(SMP) && defined(SOC_MV_ARMADAXP) 624 void 625 intr_pic_init_secondary(void) 626 { 627 } 628 629 void 630 pic_ipi_send(cpuset_t cpus, u_int ipi) 631 { 632 uint32_t val, i; 633 634 val = 0x00000000; 635 for (i = 0; i < MAXCPU; i++) 636 if (CPU_ISSET(i, &cpus)) 637 val |= (1 << (8 + i)); 638 val |= ipi; 639 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val); 640 } 641 642 int 643 pic_ipi_read(int i __unused) 644 { 645 uint32_t val; 646 int ipi; 647 648 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 649 if (val) { 650 ipi = ffs(val) - 1; 651 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 652 return (ipi); 653 } 654 655 return (0x3ff); 656 } 657 658 void 659 pic_ipi_clear(int ipi) 660 { 661 } 662 663 #endif 664