1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 6 * All rights reserved. 7 * 8 * Adapted and extended to Marvell SoCs by Semihalf. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/kernel.h> 40 #include <sys/ktr.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 struct mv_ic_softc { 53 struct resource * ic_res[1]; 54 bus_space_tag_t ic_bst; 55 bus_space_handle_t ic_bsh; 56 int ic_high_regs; 57 int ic_error_regs; 58 }; 59 60 static struct resource_spec mv_ic_spec[] = { 61 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 62 { -1, 0 } 63 }; 64 65 static struct mv_ic_softc *mv_ic_sc = NULL; 66 67 static int mv_ic_probe(device_t); 68 static int mv_ic_attach(device_t); 69 70 uint32_t mv_ic_get_cause(void); 71 uint32_t mv_ic_get_mask(void); 72 void mv_ic_set_mask(uint32_t); 73 uint32_t mv_ic_get_cause_hi(void); 74 uint32_t mv_ic_get_mask_hi(void); 75 void mv_ic_set_mask_hi(uint32_t); 76 uint32_t mv_ic_get_cause_error(void); 77 uint32_t mv_ic_get_mask_error(void); 78 void mv_ic_set_mask_error(uint32_t); 79 static void arm_mask_irq_all(void); 80 81 static int 82 mv_ic_probe(device_t dev) 83 { 84 85 if (!ofw_bus_status_okay(dev)) 86 return (ENXIO); 87 88 if (!ofw_bus_is_compatible(dev, "mrvl,pic")) 89 return (ENXIO); 90 91 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 92 return (0); 93 } 94 95 static int 96 mv_ic_attach(device_t dev) 97 { 98 struct mv_ic_softc *sc; 99 uint32_t dev_id, rev_id; 100 int error; 101 102 sc = (struct mv_ic_softc *)device_get_softc(dev); 103 104 if (mv_ic_sc != NULL) 105 return (ENXIO); 106 mv_ic_sc = sc; 107 108 soc_id(&dev_id, &rev_id); 109 110 sc->ic_high_regs = 0; 111 sc->ic_error_regs = 0; 112 113 if (dev_id == MV_DEV_88F6281 || 114 dev_id == MV_DEV_88F6282 || 115 dev_id == MV_DEV_MV78100 || 116 dev_id == MV_DEV_MV78100_Z0) 117 sc->ic_high_regs = 1; 118 119 if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0) 120 sc->ic_error_regs = 1; 121 122 error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res); 123 if (error) { 124 device_printf(dev, "could not allocate resources\n"); 125 return (ENXIO); 126 } 127 128 sc->ic_bst = rman_get_bustag(sc->ic_res[0]); 129 sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]); 130 131 /* Mask all interrupts */ 132 arm_mask_irq_all(); 133 134 return (0); 135 } 136 137 static device_method_t mv_ic_methods[] = { 138 DEVMETHOD(device_probe, mv_ic_probe), 139 DEVMETHOD(device_attach, mv_ic_attach), 140 { 0, 0 } 141 }; 142 143 static driver_t mv_ic_driver = { 144 "ic", 145 mv_ic_methods, 146 sizeof(struct mv_ic_softc), 147 }; 148 149 DRIVER_MODULE(ic, simplebus, mv_ic_driver, 0, 0); 150 151 int 152 arm_get_next_irq(int last) 153 { 154 u_int filt, irq; 155 int next; 156 157 filt = ~((last >= 0) ? (2 << last) - 1 : 0); 158 irq = mv_ic_get_cause() & mv_ic_get_mask(); 159 if (irq & filt) { 160 next = ffs(irq & filt) - 1; 161 goto out; 162 } 163 if (mv_ic_sc->ic_high_regs) { 164 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0); 165 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi(); 166 if (irq & filt) { 167 next = ffs(irq & filt) + 31; 168 goto out; 169 } 170 } 171 if (mv_ic_sc->ic_error_regs) { 172 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0); 173 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error(); 174 if (irq & filt) { 175 next = ffs(irq & filt) + 63; 176 goto out; 177 } 178 } 179 next = -1; 180 181 out: 182 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 183 return (next); 184 } 185 186 static void 187 arm_mask_irq_all(void) 188 { 189 190 mv_ic_set_mask(0); 191 192 if (mv_ic_sc->ic_high_regs) 193 mv_ic_set_mask_hi(0); 194 195 if (mv_ic_sc->ic_error_regs) 196 mv_ic_set_mask_error(0); 197 } 198 199 void 200 arm_mask_irq(uintptr_t nb) 201 { 202 uint32_t mr; 203 204 if (nb < 32) { 205 mr = mv_ic_get_mask(); 206 mr &= ~(1 << nb); 207 mv_ic_set_mask(mr); 208 209 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) { 210 mr = mv_ic_get_mask_hi(); 211 mr &= ~(1 << (nb - 32)); 212 mv_ic_set_mask_hi(mr); 213 214 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) { 215 mr = mv_ic_get_mask_error(); 216 mr &= ~(1 << (nb - 64)); 217 mv_ic_set_mask_error(mr); 218 } 219 } 220 221 void 222 arm_unmask_irq(uintptr_t nb) 223 { 224 uint32_t mr; 225 226 if (nb < 32) { 227 mr = mv_ic_get_mask(); 228 mr |= (1 << nb); 229 mv_ic_set_mask(mr); 230 231 } else if ((nb < 64) && mv_ic_sc->ic_high_regs) { 232 mr = mv_ic_get_mask_hi(); 233 mr |= (1 << (nb - 32)); 234 mv_ic_set_mask_hi(mr); 235 236 } else if ((nb < 96) && mv_ic_sc->ic_error_regs) { 237 mr = mv_ic_get_mask_error(); 238 mr |= (1 << (nb - 64)); 239 mv_ic_set_mask_error(mr); 240 } 241 } 242 243 void 244 mv_ic_set_mask(uint32_t val) 245 { 246 247 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh, 248 IRQ_MASK, val); 249 } 250 251 uint32_t 252 mv_ic_get_mask(void) 253 { 254 255 return (bus_space_read_4(mv_ic_sc->ic_bst, 256 mv_ic_sc->ic_bsh, IRQ_MASK)); 257 } 258 259 uint32_t 260 mv_ic_get_cause(void) 261 { 262 263 return (bus_space_read_4(mv_ic_sc->ic_bst, 264 mv_ic_sc->ic_bsh, IRQ_CAUSE)); 265 } 266 267 void 268 mv_ic_set_mask_hi(uint32_t val) 269 { 270 271 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh, 272 IRQ_MASK_HI, val); 273 } 274 275 uint32_t 276 mv_ic_get_mask_hi(void) 277 { 278 279 return (bus_space_read_4(mv_ic_sc->ic_bst, 280 mv_ic_sc->ic_bsh, IRQ_MASK_HI)); 281 } 282 283 uint32_t 284 mv_ic_get_cause_hi(void) 285 { 286 287 return (bus_space_read_4(mv_ic_sc->ic_bst, 288 mv_ic_sc->ic_bsh, IRQ_CAUSE_HI)); 289 } 290 291 void 292 mv_ic_set_mask_error(uint32_t val) 293 { 294 295 bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh, 296 IRQ_MASK_ERROR, val); 297 } 298 299 uint32_t 300 mv_ic_get_mask_error(void) 301 { 302 303 return (bus_space_read_4(mv_ic_sc->ic_bst, 304 mv_ic_sc->ic_bsh, IRQ_MASK_ERROR)); 305 } 306 307 uint32_t 308 mv_ic_get_cause_error(void) 309 { 310 311 return (bus_space_read_4(mv_ic_sc->ic_bst, 312 mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR)); 313 } 314