1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include "gpio_if.h" 62 63 #define GPIO_MAX_INTR_COUNT 8 64 #define GPIO_PINS_PER_REG 32 65 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 66 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 67 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ 68 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ 69 GPIO_PIN_INVOUT) 70 71 #define DEBOUNCE_CHECK_MS 1 72 #define DEBOUNCE_LO_HI_MS 2 73 #define DEBOUNCE_HI_LO_MS 2 74 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 75 76 struct mv_gpio_softc { 77 device_t dev; 78 device_t sc_busdev; 79 struct resource * mem_res; 80 int mem_rid; 81 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 82 int irq_rid[GPIO_MAX_INTR_COUNT]; 83 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 84 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 85 bus_space_tag_t bst; 86 bus_space_handle_t bsh; 87 uint32_t offset; 88 struct mtx mutex; 89 uint8_t pin_num; /* number of GPIO pins */ 90 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 91 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 92 93 /* Used for debouncing. */ 94 uint32_t debounced_state_lo; 95 uint32_t debounced_state_hi; 96 struct callout **debounce_callouts; 97 int *debounce_counters; 98 }; 99 100 struct mv_gpio_pindev { 101 device_t dev; 102 int pin; 103 }; 104 105 static int mv_gpio_probe(device_t); 106 static int mv_gpio_attach(device_t); 107 static int mv_gpio_intr(device_t, void *); 108 109 static void mv_gpio_double_edge_init(device_t, int); 110 111 static int mv_gpio_debounce_setup(device_t, int); 112 static int mv_gpio_debounce_prepare(device_t, int); 113 static int mv_gpio_debounce_init(device_t, int); 114 static void mv_gpio_debounce_start(device_t, int); 115 static void mv_gpio_debounce(void *); 116 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 117 static uint32_t mv_gpio_debounced_state_get(device_t, int); 118 119 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 120 static void mv_gpio_intr_handler(device_t, int); 121 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 122 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 123 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 124 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 125 126 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 127 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 128 static void mv_gpio_level(device_t, uint32_t, uint8_t); 129 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 130 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 131 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 132 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 133 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 134 135 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 136 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 137 138 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 139 int mv_gpio_setup_intrhandler(device_t, const char *, 140 driver_filter_t *, void (*)(void *), void *, 141 int, int, void **); 142 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 143 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 144 uint8_t mv_gpio_in(device_t, uint32_t); 145 146 /* 147 * GPIO interface 148 */ 149 static device_t mv_gpio_get_bus(device_t); 150 static int mv_gpio_pin_max(device_t, int *); 151 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 152 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 153 static int mv_gpio_pin_getname(device_t, uint32_t, char *); 154 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); 155 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); 156 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); 157 static int mv_gpio_pin_toggle(device_t, uint32_t); 158 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, 159 int, pcell_t *, uint32_t *, uint32_t *); 160 161 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 162 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 163 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 164 165 static device_method_t mv_gpio_methods[] = { 166 DEVMETHOD(device_probe, mv_gpio_probe), 167 DEVMETHOD(device_attach, mv_gpio_attach), 168 169 /* GPIO protocol */ 170 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), 171 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), 172 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), 173 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), 174 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), 175 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), 176 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), 177 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), 178 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), 179 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), 180 181 DEVMETHOD_END 182 }; 183 184 static driver_t mv_gpio_driver = { 185 "gpio", 186 mv_gpio_methods, 187 sizeof(struct mv_gpio_softc), 188 }; 189 190 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, 0, 0, 191 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 192 193 struct ofw_compat_data compat_data[] = { 194 { "mrvl,gpio", 1 }, 195 { "marvell,orion-gpio", 1 }, 196 { NULL, 0 } 197 }; 198 199 static int 200 mv_gpio_probe(device_t dev) 201 { 202 if (!ofw_bus_status_okay(dev)) 203 return (ENXIO); 204 205 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 206 return (ENXIO); 207 208 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 209 return (0); 210 } 211 212 static int 213 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node) 214 { 215 phandle_t iparent; 216 pcell_t irq_cells; 217 int i, size; 218 219 /* Find root interrupt controller */ 220 iparent = ofw_bus_find_iparent(node); 221 if (iparent == 0) { 222 device_printf(sc->dev, "No interrupt-parrent found. " 223 "Error in DTB\n"); 224 return (ENXIO); 225 } else { 226 /* While at parent - store interrupt cells prop */ 227 if (OF_searchencprop(OF_node_from_xref(iparent), 228 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 229 device_printf(sc->dev, "DTB: Missing #interrupt-cells " 230 "property in interrupt parent node\n"); 231 return (ENXIO); 232 } 233 } 234 235 size = OF_getproplen(node, "interrupts"); 236 if (size != -1) { 237 size = size / sizeof(pcell_t); 238 size = size / irq_cells; 239 sc->irq_num = size; 240 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num); 241 } else { 242 device_printf(sc->dev, "ERROR: no interrupts entry found!\n"); 243 return (ENXIO); 244 } 245 246 for (i = 0; i < sc->irq_num; i++) { 247 sc->irq_rid[i] = i; 248 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 249 &sc->irq_rid[i], RF_ACTIVE); 250 if (!sc->irq_res[i]) { 251 mtx_destroy(&sc->mutex); 252 device_printf(sc->dev, 253 "could not allocate gpio%d interrupt\n", i+1); 254 return (ENXIO); 255 } 256 } 257 258 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset); 259 /* Disable all interrupts */ 260 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0); 261 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset); 262 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0); 263 264 for (i = 0; i < sc->irq_num; i++) { 265 device_printf(sc->dev, "Setup intr %d\n", i); 266 if (bus_setup_intr(sc->dev, sc->irq_res[i], 267 INTR_TYPE_MISC, 268 (driver_filter_t *)mv_gpio_intr, NULL, 269 sc, &sc->ih_cookie[i]) != 0) { 270 mtx_destroy(&sc->mutex); 271 bus_release_resource(sc->dev, SYS_RES_IRQ, 272 sc->irq_rid[i], sc->irq_res[i]); 273 device_printf(sc->dev, "could not set up intr %d\n", i); 274 return (ENXIO); 275 } 276 } 277 278 /* Clear interrupt status. */ 279 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset); 280 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0); 281 282 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 283 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 284 if (sc->debounce_callouts == NULL) 285 return (ENOMEM); 286 287 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 288 M_DEVBUF, M_WAITOK); 289 if (sc->debounce_counters == NULL) 290 return (ENOMEM); 291 292 return (0); 293 } 294 295 static int 296 mv_gpio_attach(device_t dev) 297 { 298 int i, rv; 299 struct mv_gpio_softc *sc; 300 phandle_t node; 301 pcell_t pincnt = 0; 302 303 sc = (struct mv_gpio_softc *)device_get_softc(dev); 304 if (sc == NULL) 305 return (ENXIO); 306 307 node = ofw_bus_get_node(dev); 308 sc->dev = dev; 309 310 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 || 311 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) { 312 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); 313 if (bootverbose) 314 device_printf(dev, "%d pins available\n", sc->pin_num); 315 } else { 316 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); 317 return (ENXIO); 318 } 319 320 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1) 321 sc->offset = 0; 322 323 /* Assign generic capabilities to every gpio pin */ 324 for(i = 0; i < sc->pin_num; i++) 325 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; 326 327 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 328 329 sc->mem_rid = 0; 330 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 331 RF_ACTIVE | RF_SHAREABLE ); 332 333 if (!sc->mem_res) { 334 mtx_destroy(&sc->mutex); 335 device_printf(dev, "could not allocate memory window\n"); 336 return (ENXIO); 337 } 338 339 sc->bst = rman_get_bustag(sc->mem_res); 340 sc->bsh = rman_get_bushandle(sc->mem_res); 341 342 rv = mv_gpio_setup_interrupts(sc, node); 343 if (rv != 0) 344 return (rv); 345 346 sc->sc_busdev = gpiobus_attach_bus(dev); 347 if (sc->sc_busdev == NULL) { 348 mtx_destroy(&sc->mutex); 349 bus_release_resource(dev, SYS_RES_IRQ, 350 sc->irq_rid[i], sc->irq_res[i]); 351 return (ENXIO); 352 } 353 354 return (0); 355 } 356 357 static int 358 mv_gpio_intr(device_t dev, void *arg) 359 { 360 uint32_t int_cause, gpio_val; 361 struct mv_gpio_softc *sc; 362 sc = (struct mv_gpio_softc *)device_get_softc(dev); 363 364 MV_GPIO_LOCK(); 365 366 /* 367 * According to documentation, edge sensitive interrupts are asserted 368 * when unmasked GPIO_INT_CAUSE register bits are set. 369 */ 370 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 371 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 372 373 /* 374 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 375 * register bits are set. 376 */ 377 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 378 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 379 380 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 381 382 MV_GPIO_UNLOCK(); 383 384 return (FILTER_HANDLED); 385 } 386 387 /* 388 * GPIO interrupt handling 389 */ 390 391 void 392 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 393 { 394 /* When we acheive full interrupt support 395 * This function will be opposite to 396 * mv_gpio_setup_intrhandler 397 */ 398 399 /* Now it exists only to remind that 400 * there should be place to free mv_gpio_pindev 401 * allocated by mv_gpio_setup_intrhandler 402 */ 403 free(s, M_DEVBUF); 404 } 405 406 int 407 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 408 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 409 { 410 struct intr_event *event; 411 int error; 412 struct mv_gpio_pindev *s; 413 struct mv_gpio_softc *sc; 414 sc = (struct mv_gpio_softc *)device_get_softc(dev); 415 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 416 417 if (pin < 0 || pin >= sc->pin_num) 418 return (ENXIO); 419 event = sc->gpio_events[pin]; 420 if (event == NULL) { 421 MV_GPIO_LOCK(); 422 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 423 error = mv_gpio_debounce_init(dev, pin); 424 if (error != 0) { 425 MV_GPIO_UNLOCK(); 426 return (error); 427 } 428 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 429 mv_gpio_double_edge_init(dev, pin); 430 MV_GPIO_UNLOCK(); 431 error = intr_event_create(&event, (void *)s, 0, pin, 432 (void (*)(void *))mv_gpio_intr_mask, 433 (void (*)(void *))mv_gpio_intr_unmask, 434 (void (*)(void *))mv_gpio_int_ack, 435 NULL, 436 "gpio%d:", pin); 437 if (error != 0) 438 return (error); 439 sc->gpio_events[pin] = event; 440 } 441 442 intr_event_add_handler(event, name, filt, hand, arg, 443 intr_priority(flags), flags, cookiep); 444 return (0); 445 } 446 447 static void 448 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 449 { 450 struct mv_gpio_softc *sc; 451 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 452 453 if (s->pin >= sc->pin_num) 454 return; 455 456 MV_GPIO_LOCK(); 457 458 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 459 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 460 mv_gpio_edge(s->dev, s->pin, 0); 461 else 462 mv_gpio_level(s->dev, s->pin, 0); 463 464 /* 465 * The interrupt has to be acknowledged before scheduling an interrupt 466 * thread. This way we allow for interrupt source to trigger again 467 * (which can happen with shared IRQs e.g. PCI) while processing the 468 * current event. 469 */ 470 mv_gpio_int_ack(s); 471 472 MV_GPIO_UNLOCK(); 473 474 return; 475 } 476 477 static void 478 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 479 { 480 struct mv_gpio_softc *sc; 481 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 482 483 if (s->pin >= sc->pin_num) 484 return; 485 486 MV_GPIO_LOCK(); 487 488 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 489 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 490 mv_gpio_edge(s->dev, s->pin, 1); 491 else 492 mv_gpio_level(s->dev, s->pin, 1); 493 494 MV_GPIO_UNLOCK(); 495 496 return; 497 } 498 499 static void 500 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 501 { 502 int i, pin; 503 struct mv_gpio_softc *sc; 504 sc = (struct mv_gpio_softc *)device_get_softc(dev); 505 506 MV_GPIO_ASSERT_LOCKED(); 507 508 i = 0; 509 while (status != 0) { 510 if (status & 1) { 511 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 512 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 513 mv_gpio_debounce_start(dev, pin); 514 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 515 mv_gpio_polarity(dev, pin, 0, 1); 516 mv_gpio_intr_handler(dev, pin); 517 } else 518 mv_gpio_intr_handler(dev, pin); 519 } 520 status >>= 1; 521 i++; 522 } 523 } 524 525 static void 526 mv_gpio_intr_handler(device_t dev, int pin) 527 { 528 struct intr_irqsrc isrc; 529 struct mv_gpio_softc *sc; 530 sc = (struct mv_gpio_softc *)device_get_softc(dev); 531 532 MV_GPIO_ASSERT_LOCKED(); 533 534 #ifdef INTR_SOLO 535 isrc.isrc_filter = NULL; 536 #endif 537 isrc.isrc_event = sc->gpio_events[pin]; 538 539 if (isrc.isrc_event == NULL || 540 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers)) 541 return; 542 543 intr_isrc_dispatch(&isrc, NULL); 544 } 545 546 int 547 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 548 { 549 int error; 550 struct mv_gpio_softc *sc; 551 sc = (struct mv_gpio_softc *)device_get_softc(dev); 552 error = 0; 553 554 if (pin >= sc->pin_num) 555 return (EINVAL); 556 557 /* check flags consistency */ 558 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 559 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 560 return (EINVAL); 561 562 if (mask & MV_GPIO_IN_DEBOUNCE) { 563 if (sc->irq_num == 0) 564 return (EINVAL); 565 error = mv_gpio_debounce_prepare(dev, pin); 566 if (error != 0) 567 return (error); 568 } 569 570 MV_GPIO_LOCK(); 571 572 if ((mask & flags) & GPIO_PIN_INPUT) 573 mv_gpio_out_en(dev, pin, 0); 574 if ((mask & flags) & GPIO_PIN_OUTPUT) { 575 if ((flags & mask) & GPIO_PIN_OPENDRAIN) 576 mv_gpio_value_set(dev, pin, 0); 577 else 578 mv_gpio_value_set(dev, pin, 1); 579 mv_gpio_out_en(dev, pin, 1); 580 } 581 582 if (mask & MV_GPIO_OUT_BLINK) 583 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 584 if (mask & MV_GPIO_IN_POL_LOW) 585 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 586 if (mask & MV_GPIO_IN_DEBOUNCE) { 587 error = mv_gpio_debounce_setup(dev, pin); 588 if (error) { 589 MV_GPIO_UNLOCK(); 590 return (error); 591 } 592 } 593 594 sc->gpio_setup[pin].gp_flags &= ~(mask); 595 sc->gpio_setup[pin].gp_flags |= (flags & mask); 596 597 MV_GPIO_UNLOCK(); 598 599 return (0); 600 } 601 602 static void 603 mv_gpio_double_edge_init(device_t dev, int pin) 604 { 605 uint8_t raw_read; 606 struct mv_gpio_softc *sc __unused; 607 sc = (struct mv_gpio_softc *)device_get_softc(dev); 608 609 MV_GPIO_ASSERT_LOCKED(); 610 611 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 612 613 if (raw_read) 614 mv_gpio_polarity(dev, pin, 1, 0); 615 else 616 mv_gpio_polarity(dev, pin, 0, 0); 617 } 618 619 static int 620 mv_gpio_debounce_setup(device_t dev, int pin) 621 { 622 struct callout *c; 623 struct mv_gpio_softc *sc; 624 625 sc = (struct mv_gpio_softc *)device_get_softc(dev); 626 627 MV_GPIO_ASSERT_LOCKED(); 628 629 c = sc->debounce_callouts[pin]; 630 if (c == NULL) 631 return (ENXIO); 632 633 if (callout_active(c)) 634 callout_deactivate(c); 635 636 callout_stop(c); 637 638 return (0); 639 } 640 641 static int 642 mv_gpio_debounce_prepare(device_t dev, int pin) 643 { 644 struct callout *c; 645 struct mv_gpio_softc *sc; 646 647 sc = (struct mv_gpio_softc *)device_get_softc(dev); 648 649 c = sc->debounce_callouts[pin]; 650 if (c == NULL) { 651 c = (struct callout *)malloc(sizeof(struct callout), 652 M_DEVBUF, M_WAITOK); 653 sc->debounce_callouts[pin] = c; 654 if (c == NULL) 655 return (ENOMEM); 656 callout_init(c, 1); 657 } 658 659 return (0); 660 } 661 662 static int 663 mv_gpio_debounce_init(device_t dev, int pin) 664 { 665 uint8_t raw_read; 666 int *cnt; 667 struct mv_gpio_softc *sc; 668 669 sc = (struct mv_gpio_softc *)device_get_softc(dev); 670 671 MV_GPIO_ASSERT_LOCKED(); 672 673 cnt = &sc->debounce_counters[pin]; 674 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 675 if (raw_read) { 676 mv_gpio_polarity(dev, pin, 1, 0); 677 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 678 } else { 679 mv_gpio_polarity(dev, pin, 0, 0); 680 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 681 } 682 683 mv_gpio_debounced_state_set(dev, pin, raw_read); 684 685 return (0); 686 } 687 688 static void 689 mv_gpio_debounce_start(device_t dev, int pin) 690 { 691 struct callout *c; 692 struct mv_gpio_pindev s = {dev, pin}; 693 struct mv_gpio_pindev *sd; 694 struct mv_gpio_softc *sc; 695 sc = (struct mv_gpio_softc *)device_get_softc(dev); 696 697 MV_GPIO_ASSERT_LOCKED(); 698 699 c = sc->debounce_callouts[pin]; 700 if (c == NULL) { 701 mv_gpio_int_ack(&s); 702 return; 703 } 704 705 if (callout_pending(c) || callout_active(c)) { 706 mv_gpio_int_ack(&s); 707 return; 708 } 709 710 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 711 M_DEVBUF, M_WAITOK); 712 if (sd == NULL) { 713 mv_gpio_int_ack(&s); 714 return; 715 } 716 sd->pin = pin; 717 sd->dev = dev; 718 719 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 720 } 721 722 static void 723 mv_gpio_debounce(void *arg) 724 { 725 uint8_t raw_read, last_state; 726 int pin; 727 device_t dev; 728 int *debounce_counter; 729 struct mv_gpio_softc *sc; 730 struct mv_gpio_pindev *s; 731 732 s = (struct mv_gpio_pindev *)arg; 733 dev = s->dev; 734 pin = s->pin; 735 sc = (struct mv_gpio_softc *)device_get_softc(dev); 736 737 MV_GPIO_LOCK(); 738 739 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 740 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 741 debounce_counter = &sc->debounce_counters[pin]; 742 743 if (raw_read == last_state) { 744 if (last_state) 745 *debounce_counter = DEBOUNCE_HI_LO_MS / 746 DEBOUNCE_CHECK_MS; 747 else 748 *debounce_counter = DEBOUNCE_LO_HI_MS / 749 DEBOUNCE_CHECK_MS; 750 751 callout_reset(sc->debounce_callouts[pin], 752 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 753 } else { 754 *debounce_counter = *debounce_counter - 1; 755 if (*debounce_counter != 0) 756 callout_reset(sc->debounce_callouts[pin], 757 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 758 else { 759 mv_gpio_debounced_state_set(dev, pin, raw_read); 760 761 if (last_state) 762 *debounce_counter = DEBOUNCE_HI_LO_MS / 763 DEBOUNCE_CHECK_MS; 764 else 765 *debounce_counter = DEBOUNCE_LO_HI_MS / 766 DEBOUNCE_CHECK_MS; 767 768 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 769 (raw_read == 0)) || 770 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 771 raw_read) || 772 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 773 mv_gpio_intr_handler(dev, pin); 774 775 /* Toggle polarity for next edge. */ 776 mv_gpio_polarity(dev, pin, 0, 1); 777 778 free(arg, M_DEVBUF); 779 callout_deactivate(sc->debounce_callouts[pin]); 780 } 781 } 782 783 MV_GPIO_UNLOCK(); 784 } 785 786 static void 787 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 788 { 789 uint32_t *old_state; 790 struct mv_gpio_softc *sc; 791 sc = (struct mv_gpio_softc *)device_get_softc(dev); 792 793 MV_GPIO_ASSERT_LOCKED(); 794 795 if (pin >= GPIO_PINS_PER_REG) { 796 old_state = &sc->debounced_state_hi; 797 pin -= GPIO_PINS_PER_REG; 798 } else 799 old_state = &sc->debounced_state_lo; 800 801 if (new_state) 802 *old_state |= (1 << pin); 803 else 804 *old_state &= ~(1 << pin); 805 } 806 807 static uint32_t 808 mv_gpio_debounced_state_get(device_t dev, int pin) 809 { 810 uint32_t *state; 811 struct mv_gpio_softc *sc; 812 sc = (struct mv_gpio_softc *)device_get_softc(dev); 813 814 MV_GPIO_ASSERT_LOCKED(); 815 816 if (pin >= GPIO_PINS_PER_REG) { 817 state = &sc->debounced_state_hi; 818 pin -= GPIO_PINS_PER_REG; 819 } else 820 state = &sc->debounced_state_lo; 821 822 return (*state & (1 << pin)); 823 } 824 825 void 826 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 827 { 828 struct mv_gpio_softc *sc; 829 sc = (struct mv_gpio_softc *)device_get_softc(dev); 830 831 MV_GPIO_LOCK(); 832 833 mv_gpio_value_set(dev, pin, val); 834 mv_gpio_out_en(dev, pin, enable); 835 836 MV_GPIO_UNLOCK(); 837 } 838 839 uint8_t 840 mv_gpio_in(device_t dev, uint32_t pin) 841 { 842 uint8_t state; 843 struct mv_gpio_softc *sc; 844 sc = (struct mv_gpio_softc *)device_get_softc(dev); 845 846 MV_GPIO_ASSERT_LOCKED(); 847 848 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 849 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 850 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 851 else 852 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 853 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 854 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 855 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 856 else 857 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 858 } else 859 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 860 861 return (state); 862 } 863 864 static uint32_t 865 mv_gpio_reg_read(device_t dev, uint32_t reg) 866 { 867 struct mv_gpio_softc *sc; 868 sc = (struct mv_gpio_softc *)device_get_softc(dev); 869 870 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg)); 871 } 872 873 static void 874 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 875 { 876 struct mv_gpio_softc *sc; 877 sc = (struct mv_gpio_softc *)device_get_softc(dev); 878 879 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val); 880 } 881 882 static void 883 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 884 { 885 uint32_t reg_val; 886 887 reg_val = mv_gpio_reg_read(dev, reg); 888 reg_val |= GPIO(pin); 889 mv_gpio_reg_write(dev, reg, reg_val); 890 } 891 892 static void 893 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 894 { 895 uint32_t reg_val; 896 897 reg_val = mv_gpio_reg_read(dev, reg); 898 reg_val &= ~(GPIO(pin)); 899 mv_gpio_reg_write(dev, reg, reg_val); 900 } 901 902 static void 903 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 904 { 905 uint32_t reg; 906 struct mv_gpio_softc *sc; 907 sc = (struct mv_gpio_softc *)device_get_softc(dev); 908 909 if (pin >= sc->pin_num) 910 return; 911 912 reg = GPIO_DATA_OUT_EN_CTRL; 913 914 if (enable) 915 mv_gpio_reg_clear(dev, reg, pin); 916 else 917 mv_gpio_reg_set(dev, reg, pin); 918 } 919 920 static void 921 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 922 { 923 uint32_t reg; 924 struct mv_gpio_softc *sc; 925 sc = (struct mv_gpio_softc *)device_get_softc(dev); 926 927 if (pin >= sc->pin_num) 928 return; 929 930 reg = GPIO_BLINK_EN; 931 932 if (enable) 933 mv_gpio_reg_set(dev, reg, pin); 934 else 935 mv_gpio_reg_clear(dev, reg, pin); 936 } 937 938 static void 939 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 940 { 941 uint32_t reg, reg_val; 942 struct mv_gpio_softc *sc; 943 sc = (struct mv_gpio_softc *)device_get_softc(dev); 944 945 if (pin >= sc->pin_num) 946 return; 947 948 reg = GPIO_DATA_IN_POLAR; 949 950 if (toggle) { 951 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 952 if (reg_val) 953 mv_gpio_reg_clear(dev, reg, pin); 954 else 955 mv_gpio_reg_set(dev, reg, pin); 956 } else if (enable) 957 mv_gpio_reg_set(dev, reg, pin); 958 else 959 mv_gpio_reg_clear(dev, reg, pin); 960 } 961 962 static void 963 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 964 { 965 uint32_t reg; 966 struct mv_gpio_softc *sc; 967 sc = (struct mv_gpio_softc *)device_get_softc(dev); 968 969 if (pin >= sc->pin_num) 970 return; 971 972 reg = GPIO_INT_LEV_MASK; 973 974 if (enable) 975 mv_gpio_reg_set(dev, reg, pin); 976 else 977 mv_gpio_reg_clear(dev, reg, pin); 978 } 979 980 static void 981 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 982 { 983 uint32_t reg; 984 struct mv_gpio_softc *sc; 985 sc = (struct mv_gpio_softc *)device_get_softc(dev); 986 987 if (pin >= sc->pin_num) 988 return; 989 990 reg = GPIO_INT_EDGE_MASK; 991 992 if (enable) 993 mv_gpio_reg_set(dev, reg, pin); 994 else 995 mv_gpio_reg_clear(dev, reg, pin); 996 } 997 998 static void 999 mv_gpio_int_ack(struct mv_gpio_pindev *s) 1000 { 1001 uint32_t reg, pin; 1002 struct mv_gpio_softc *sc; 1003 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 1004 pin = s->pin; 1005 1006 if (pin >= sc->pin_num) 1007 return; 1008 1009 reg = GPIO_INT_CAUSE; 1010 1011 mv_gpio_reg_clear(s->dev, reg, pin); 1012 } 1013 1014 static uint32_t 1015 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 1016 { 1017 uint32_t reg, polar_reg, reg_val, polar_reg_val; 1018 struct mv_gpio_softc *sc; 1019 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1020 1021 if (pin >= sc->pin_num) 1022 return (0); 1023 1024 reg = GPIO_DATA_IN; 1025 polar_reg = GPIO_DATA_IN_POLAR; 1026 1027 reg_val = mv_gpio_reg_read(dev, reg); 1028 1029 if (exclude_polar) { 1030 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 1031 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 1032 } else 1033 return (reg_val & GPIO(pin)); 1034 } 1035 1036 static void 1037 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 1038 { 1039 uint32_t reg; 1040 struct mv_gpio_softc *sc; 1041 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1042 1043 MV_GPIO_ASSERT_LOCKED(); 1044 1045 if (pin >= sc->pin_num) 1046 return; 1047 1048 reg = GPIO_DATA_OUT; 1049 1050 if (val) 1051 mv_gpio_reg_set(dev, reg, pin); 1052 else 1053 mv_gpio_reg_clear(dev, reg, pin); 1054 } 1055 1056 /* 1057 * GPIO interface methods 1058 */ 1059 1060 static int 1061 mv_gpio_pin_max(device_t dev, int *maxpin) 1062 { 1063 struct mv_gpio_softc *sc; 1064 if (maxpin == NULL) 1065 return (EINVAL); 1066 1067 sc = device_get_softc(dev); 1068 *maxpin = sc->pin_num; 1069 1070 return (0); 1071 } 1072 1073 static int 1074 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 1075 { 1076 struct mv_gpio_softc *sc = device_get_softc(dev); 1077 if (caps == NULL) 1078 return (EINVAL); 1079 1080 if (pin >= sc->pin_num) 1081 return (EINVAL); 1082 1083 MV_GPIO_LOCK(); 1084 *caps = sc->gpio_setup[pin].gp_caps; 1085 MV_GPIO_UNLOCK(); 1086 1087 return (0); 1088 } 1089 1090 static int 1091 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 1092 { 1093 struct mv_gpio_softc *sc = device_get_softc(dev); 1094 if (flags == NULL) 1095 return (EINVAL); 1096 1097 if (pin >= sc->pin_num) 1098 return (EINVAL); 1099 1100 MV_GPIO_LOCK(); 1101 *flags = sc->gpio_setup[pin].gp_flags; 1102 MV_GPIO_UNLOCK(); 1103 1104 return (0); 1105 } 1106 1107 static int 1108 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 1109 { 1110 struct mv_gpio_softc *sc = device_get_softc(dev); 1111 if (name == NULL) 1112 return (EINVAL); 1113 1114 if (pin >= sc->pin_num) 1115 return (EINVAL); 1116 1117 MV_GPIO_LOCK(); 1118 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); 1119 MV_GPIO_UNLOCK(); 1120 1121 return (0); 1122 } 1123 1124 static int 1125 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 1126 { 1127 int ret; 1128 struct mv_gpio_softc *sc = device_get_softc(dev); 1129 if (pin >= sc->pin_num) 1130 return (EINVAL); 1131 1132 /* Check for unwanted flags. */ 1133 if ((flags & sc->gpio_setup[pin].gp_caps) != flags) 1134 return (EINVAL); 1135 1136 ret = mv_gpio_configure(dev, pin, flags, ~0); 1137 1138 return (ret); 1139 } 1140 1141 static int 1142 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 1143 { 1144 struct mv_gpio_softc *sc = device_get_softc(dev); 1145 if (pin >= sc->pin_num) 1146 return (EINVAL); 1147 1148 MV_GPIO_LOCK(); 1149 mv_gpio_value_set(dev, pin, value); 1150 MV_GPIO_UNLOCK(); 1151 1152 return (0); 1153 } 1154 1155 static int 1156 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 1157 { 1158 struct mv_gpio_softc *sc = device_get_softc(dev); 1159 if (value == NULL) 1160 return (EINVAL); 1161 1162 if (pin >= sc->pin_num) 1163 return (EINVAL); 1164 1165 MV_GPIO_LOCK(); 1166 *value = mv_gpio_in(dev, pin); 1167 MV_GPIO_UNLOCK(); 1168 1169 return (0); 1170 } 1171 1172 static int 1173 mv_gpio_pin_toggle(device_t dev, uint32_t pin) 1174 { 1175 struct mv_gpio_softc *sc = device_get_softc(dev); 1176 uint32_t value; 1177 if (pin >= sc->pin_num) 1178 return (EINVAL); 1179 1180 MV_GPIO_LOCK(); 1181 value = mv_gpio_in(dev, pin); 1182 value = (~value) & 1; 1183 mv_gpio_value_set(dev, pin, value); 1184 MV_GPIO_UNLOCK(); 1185 1186 return (0); 1187 } 1188 1189 static device_t 1190 mv_gpio_get_bus(device_t dev) 1191 { 1192 struct mv_gpio_softc *sc = device_get_softc(dev); 1193 1194 return (sc->sc_busdev); 1195 } 1196 1197 static int 1198 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1199 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1200 { 1201 struct mv_gpio_softc *sc = device_get_softc(bus); 1202 1203 if (gpios[0] >= sc->pin_num) 1204 return (EINVAL); 1205 1206 *pin = gpios[0]; 1207 *flags = gpios[1]; 1208 mv_gpio_configure(bus, *pin, *flags, ~0); 1209 1210 return (0); 1211 } 1212