1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/gpio/gpiobusvar.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include "gpio_if.h" 62 63 #ifdef __aarch64__ 64 #include "opt_soc.h" 65 #endif 66 67 #define GPIO_MAX_INTR_COUNT 8 68 #define GPIO_PINS_PER_REG 32 69 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 70 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 71 GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ 72 GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ 73 GPIO_PIN_INVOUT) 74 75 #define DEBOUNCE_CHECK_MS 1 76 #define DEBOUNCE_LO_HI_MS 2 77 #define DEBOUNCE_HI_LO_MS 2 78 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 79 80 struct mv_gpio_softc { 81 device_t dev; 82 device_t sc_busdev; 83 struct resource * mem_res; 84 int mem_rid; 85 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 86 int irq_rid[GPIO_MAX_INTR_COUNT]; 87 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 88 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 89 bus_space_tag_t bst; 90 bus_space_handle_t bsh; 91 uint32_t offset; 92 struct mtx mutex; 93 uint8_t pin_num; /* number of GPIO pins */ 94 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 95 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 96 97 /* Used for debouncing. */ 98 uint32_t debounced_state_lo; 99 uint32_t debounced_state_hi; 100 struct callout **debounce_callouts; 101 int *debounce_counters; 102 }; 103 104 struct mv_gpio_pindev { 105 device_t dev; 106 int pin; 107 }; 108 109 static int mv_gpio_probe(device_t); 110 static int mv_gpio_attach(device_t); 111 static int mv_gpio_intr(device_t, void *); 112 113 static void mv_gpio_double_edge_init(device_t, int); 114 115 static int mv_gpio_debounce_setup(device_t, int); 116 static int mv_gpio_debounce_prepare(device_t, int); 117 static int mv_gpio_debounce_init(device_t, int); 118 static void mv_gpio_debounce_start(device_t, int); 119 static void mv_gpio_debounce(void *); 120 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 121 static uint32_t mv_gpio_debounced_state_get(device_t, int); 122 123 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 124 static void mv_gpio_intr_handler(device_t, int); 125 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 126 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 127 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 128 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 129 130 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 131 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 132 static void mv_gpio_level(device_t, uint32_t, uint8_t); 133 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 134 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 135 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 136 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 137 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 138 139 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 140 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 141 142 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 143 int mv_gpio_setup_intrhandler(device_t, const char *, 144 driver_filter_t *, void (*)(void *), void *, 145 int, int, void **); 146 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 147 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 148 uint8_t mv_gpio_in(device_t, uint32_t); 149 150 /* 151 * GPIO interface 152 */ 153 static device_t mv_gpio_get_bus(device_t); 154 static int mv_gpio_pin_max(device_t, int *); 155 static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 156 static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 157 static int mv_gpio_pin_getname(device_t, uint32_t, char *); 158 static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); 159 static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); 160 static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); 161 static int mv_gpio_pin_toggle(device_t, uint32_t); 162 static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, 163 int, pcell_t *, uint32_t *, uint32_t *); 164 165 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 166 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 167 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 168 169 static device_method_t mv_gpio_methods[] = { 170 DEVMETHOD(device_probe, mv_gpio_probe), 171 DEVMETHOD(device_attach, mv_gpio_attach), 172 173 /* GPIO protocol */ 174 DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), 175 DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), 176 DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), 177 DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), 178 DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), 179 DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), 180 DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), 181 DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), 182 DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), 183 DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), 184 185 DEVMETHOD_END 186 }; 187 188 static driver_t mv_gpio_driver = { 189 "gpio", 190 mv_gpio_methods, 191 sizeof(struct mv_gpio_softc), 192 }; 193 194 static devclass_t mv_gpio_devclass; 195 196 EARLY_DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0, 197 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 198 199 struct ofw_compat_data compat_data[] = { 200 { "mrvl,gpio", 1 }, 201 { "marvell,orion-gpio", 1 }, 202 #ifdef SOC_MARVELL_8K 203 { "marvell,armada-8k-gpio", 1 }, 204 #endif 205 { NULL, 0 } 206 }; 207 208 static int 209 mv_gpio_probe(device_t dev) 210 { 211 if (!ofw_bus_status_okay(dev)) 212 return (ENXIO); 213 214 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 215 return (ENXIO); 216 217 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 218 return (0); 219 } 220 221 static int 222 mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node) 223 { 224 phandle_t iparent; 225 pcell_t irq_cells; 226 int i, size; 227 228 /* Find root interrupt controller */ 229 iparent = ofw_bus_find_iparent(node); 230 if (iparent == 0) { 231 device_printf(sc->dev, "No interrupt-parrent found. " 232 "Error in DTB\n"); 233 return (ENXIO); 234 } else { 235 /* While at parent - store interrupt cells prop */ 236 if (OF_searchencprop(OF_node_from_xref(iparent), 237 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 238 device_printf(sc->dev, "DTB: Missing #interrupt-cells " 239 "property in interrupt parent node\n"); 240 return (ENXIO); 241 } 242 } 243 244 size = OF_getproplen(node, "interrupts"); 245 if (size != -1) { 246 size = size / sizeof(pcell_t); 247 size = size / irq_cells; 248 sc->irq_num = size; 249 device_printf(sc->dev, "%d IRQs available\n", sc->irq_num); 250 } else { 251 device_printf(sc->dev, "ERROR: no interrupts entry found!\n"); 252 return (ENXIO); 253 } 254 255 for (i = 0; i < sc->irq_num; i++) { 256 sc->irq_rid[i] = i; 257 sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 258 &sc->irq_rid[i], RF_ACTIVE); 259 if (!sc->irq_res[i]) { 260 mtx_destroy(&sc->mutex); 261 device_printf(sc->dev, 262 "could not allocate gpio%d interrupt\n", i+1); 263 return (ENXIO); 264 } 265 } 266 267 device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset); 268 /* Disable all interrupts */ 269 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0); 270 device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset); 271 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0); 272 273 for (i = 0; i < sc->irq_num; i++) { 274 device_printf(sc->dev, "Setup intr %d\n", i); 275 if (bus_setup_intr(sc->dev, sc->irq_res[i], 276 INTR_TYPE_MISC, 277 (driver_filter_t *)mv_gpio_intr, NULL, 278 sc, &sc->ih_cookie[i]) != 0) { 279 mtx_destroy(&sc->mutex); 280 bus_release_resource(sc->dev, SYS_RES_IRQ, 281 sc->irq_rid[i], sc->irq_res[i]); 282 device_printf(sc->dev, "could not set up intr %d\n", i); 283 return (ENXIO); 284 } 285 } 286 287 /* Clear interrupt status. */ 288 device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset); 289 bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0); 290 291 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 292 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 293 if (sc->debounce_callouts == NULL) 294 return (ENOMEM); 295 296 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 297 M_DEVBUF, M_WAITOK); 298 if (sc->debounce_counters == NULL) 299 return (ENOMEM); 300 301 return (0); 302 } 303 304 static int 305 mv_gpio_attach(device_t dev) 306 { 307 int i, rv; 308 struct mv_gpio_softc *sc; 309 phandle_t node; 310 pcell_t pincnt = 0; 311 312 sc = (struct mv_gpio_softc *)device_get_softc(dev); 313 if (sc == NULL) 314 return (ENXIO); 315 316 node = ofw_bus_get_node(dev); 317 sc->dev = dev; 318 319 if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 || 320 OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) { 321 sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); 322 if (bootverbose) 323 device_printf(dev, "%d pins available\n", sc->pin_num); 324 } else { 325 device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); 326 return (ENXIO); 327 } 328 329 if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1) 330 sc->offset = 0; 331 332 /* Assign generic capabilities to every gpio pin */ 333 for(i = 0; i < sc->pin_num; i++) 334 sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; 335 336 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 337 338 sc->mem_rid = 0; 339 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 340 RF_ACTIVE | RF_SHAREABLE ); 341 342 if (!sc->mem_res) { 343 mtx_destroy(&sc->mutex); 344 device_printf(dev, "could not allocate memory window\n"); 345 return (ENXIO); 346 } 347 348 sc->bst = rman_get_bustag(sc->mem_res); 349 sc->bsh = rman_get_bushandle(sc->mem_res); 350 351 rv = mv_gpio_setup_interrupts(sc, node); 352 if (rv != 0) 353 return (rv); 354 355 sc->sc_busdev = gpiobus_attach_bus(dev); 356 if (sc->sc_busdev == NULL) { 357 mtx_destroy(&sc->mutex); 358 bus_release_resource(dev, SYS_RES_IRQ, 359 sc->irq_rid[i], sc->irq_res[i]); 360 return (ENXIO); 361 } 362 363 return (0); 364 } 365 366 static int 367 mv_gpio_intr(device_t dev, void *arg) 368 { 369 uint32_t int_cause, gpio_val; 370 struct mv_gpio_softc *sc; 371 sc = (struct mv_gpio_softc *)device_get_softc(dev); 372 373 MV_GPIO_LOCK(); 374 375 /* 376 * According to documentation, edge sensitive interrupts are asserted 377 * when unmasked GPIO_INT_CAUSE register bits are set. 378 */ 379 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 380 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 381 382 /* 383 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 384 * register bits are set. 385 */ 386 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 387 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 388 389 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 390 391 MV_GPIO_UNLOCK(); 392 393 return (FILTER_HANDLED); 394 } 395 396 /* 397 * GPIO interrupt handling 398 */ 399 400 void 401 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 402 { 403 /* When we acheive full interrupt support 404 * This function will be opposite to 405 * mv_gpio_setup_intrhandler 406 */ 407 408 /* Now it exists only to remind that 409 * there should be place to free mv_gpio_pindev 410 * allocated by mv_gpio_setup_intrhandler 411 */ 412 free(s, M_DEVBUF); 413 } 414 415 int 416 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 417 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 418 { 419 struct intr_event *event; 420 int error; 421 struct mv_gpio_pindev *s; 422 struct mv_gpio_softc *sc; 423 sc = (struct mv_gpio_softc *)device_get_softc(dev); 424 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 425 426 if (pin < 0 || pin >= sc->pin_num) 427 return (ENXIO); 428 event = sc->gpio_events[pin]; 429 if (event == NULL) { 430 MV_GPIO_LOCK(); 431 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 432 error = mv_gpio_debounce_init(dev, pin); 433 if (error != 0) { 434 MV_GPIO_UNLOCK(); 435 return (error); 436 } 437 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 438 mv_gpio_double_edge_init(dev, pin); 439 MV_GPIO_UNLOCK(); 440 error = intr_event_create(&event, (void *)s, 0, pin, 441 (void (*)(void *))mv_gpio_intr_mask, 442 (void (*)(void *))mv_gpio_intr_unmask, 443 (void (*)(void *))mv_gpio_int_ack, 444 NULL, 445 "gpio%d:", pin); 446 if (error != 0) 447 return (error); 448 sc->gpio_events[pin] = event; 449 } 450 451 intr_event_add_handler(event, name, filt, hand, arg, 452 intr_priority(flags), flags, cookiep); 453 return (0); 454 } 455 456 static void 457 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 458 { 459 struct mv_gpio_softc *sc; 460 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 461 462 if (s->pin >= sc->pin_num) 463 return; 464 465 MV_GPIO_LOCK(); 466 467 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 468 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 469 mv_gpio_edge(s->dev, s->pin, 0); 470 else 471 mv_gpio_level(s->dev, s->pin, 0); 472 473 /* 474 * The interrupt has to be acknowledged before scheduling an interrupt 475 * thread. This way we allow for interrupt source to trigger again 476 * (which can happen with shared IRQs e.g. PCI) while processing the 477 * current event. 478 */ 479 mv_gpio_int_ack(s); 480 481 MV_GPIO_UNLOCK(); 482 483 return; 484 } 485 486 static void 487 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 488 { 489 struct mv_gpio_softc *sc; 490 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 491 492 if (s->pin >= sc->pin_num) 493 return; 494 495 MV_GPIO_LOCK(); 496 497 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 498 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 499 mv_gpio_edge(s->dev, s->pin, 1); 500 else 501 mv_gpio_level(s->dev, s->pin, 1); 502 503 MV_GPIO_UNLOCK(); 504 505 return; 506 } 507 508 static void 509 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 510 { 511 int i, pin; 512 struct mv_gpio_softc *sc; 513 sc = (struct mv_gpio_softc *)device_get_softc(dev); 514 515 MV_GPIO_ASSERT_LOCKED(); 516 517 i = 0; 518 while (status != 0) { 519 if (status & 1) { 520 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 521 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 522 mv_gpio_debounce_start(dev, pin); 523 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 524 mv_gpio_polarity(dev, pin, 0, 1); 525 mv_gpio_intr_handler(dev, pin); 526 } else 527 mv_gpio_intr_handler(dev, pin); 528 } 529 status >>= 1; 530 i++; 531 } 532 } 533 534 static void 535 mv_gpio_intr_handler(device_t dev, int pin) 536 { 537 #ifdef INTRNG 538 struct intr_irqsrc isrc; 539 struct mv_gpio_softc *sc; 540 sc = (struct mv_gpio_softc *)device_get_softc(dev); 541 542 MV_GPIO_ASSERT_LOCKED(); 543 544 #ifdef INTR_SOLO 545 isrc.isrc_filter = NULL; 546 #endif 547 isrc.isrc_event = sc->gpio_events[pin]; 548 549 if (isrc.isrc_event == NULL || 550 CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers)) 551 return; 552 553 intr_isrc_dispatch(&isrc, NULL); 554 #endif 555 } 556 557 int 558 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 559 { 560 int error; 561 struct mv_gpio_softc *sc; 562 sc = (struct mv_gpio_softc *)device_get_softc(dev); 563 error = 0; 564 565 if (pin >= sc->pin_num) 566 return (EINVAL); 567 568 /* check flags consistency */ 569 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 570 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 571 return (EINVAL); 572 573 if (mask & MV_GPIO_IN_DEBOUNCE) { 574 if (sc->irq_num == 0) 575 return (EINVAL); 576 error = mv_gpio_debounce_prepare(dev, pin); 577 if (error != 0) 578 return (error); 579 } 580 581 MV_GPIO_LOCK(); 582 583 if ((mask & flags) & GPIO_PIN_INPUT) 584 mv_gpio_out_en(dev, pin, 0); 585 if ((mask & flags) & GPIO_PIN_OUTPUT) { 586 if ((flags & mask) & GPIO_PIN_OPENDRAIN) 587 mv_gpio_value_set(dev, pin, 0); 588 else 589 mv_gpio_value_set(dev, pin, 1); 590 mv_gpio_out_en(dev, pin, 1); 591 } 592 593 if (mask & MV_GPIO_OUT_BLINK) 594 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 595 if (mask & MV_GPIO_IN_POL_LOW) 596 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 597 if (mask & MV_GPIO_IN_DEBOUNCE) { 598 error = mv_gpio_debounce_setup(dev, pin); 599 if (error) { 600 MV_GPIO_UNLOCK(); 601 return (error); 602 } 603 } 604 605 sc->gpio_setup[pin].gp_flags &= ~(mask); 606 sc->gpio_setup[pin].gp_flags |= (flags & mask); 607 608 MV_GPIO_UNLOCK(); 609 610 return (0); 611 } 612 613 static void 614 mv_gpio_double_edge_init(device_t dev, int pin) 615 { 616 uint8_t raw_read; 617 struct mv_gpio_softc *sc; 618 sc = (struct mv_gpio_softc *)device_get_softc(dev); 619 620 MV_GPIO_ASSERT_LOCKED(); 621 622 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 623 624 if (raw_read) 625 mv_gpio_polarity(dev, pin, 1, 0); 626 else 627 mv_gpio_polarity(dev, pin, 0, 0); 628 } 629 630 static int 631 mv_gpio_debounce_setup(device_t dev, int pin) 632 { 633 struct callout *c; 634 struct mv_gpio_softc *sc; 635 636 sc = (struct mv_gpio_softc *)device_get_softc(dev); 637 638 MV_GPIO_ASSERT_LOCKED(); 639 640 c = sc->debounce_callouts[pin]; 641 if (c == NULL) 642 return (ENXIO); 643 644 if (callout_active(c)) 645 callout_deactivate(c); 646 647 callout_stop(c); 648 649 return (0); 650 } 651 652 static int 653 mv_gpio_debounce_prepare(device_t dev, int pin) 654 { 655 struct callout *c; 656 struct mv_gpio_softc *sc; 657 658 sc = (struct mv_gpio_softc *)device_get_softc(dev); 659 660 c = sc->debounce_callouts[pin]; 661 if (c == NULL) { 662 c = (struct callout *)malloc(sizeof(struct callout), 663 M_DEVBUF, M_WAITOK); 664 sc->debounce_callouts[pin] = c; 665 if (c == NULL) 666 return (ENOMEM); 667 callout_init(c, 1); 668 } 669 670 return (0); 671 } 672 673 static int 674 mv_gpio_debounce_init(device_t dev, int pin) 675 { 676 uint8_t raw_read; 677 int *cnt; 678 struct mv_gpio_softc *sc; 679 680 sc = (struct mv_gpio_softc *)device_get_softc(dev); 681 682 MV_GPIO_ASSERT_LOCKED(); 683 684 cnt = &sc->debounce_counters[pin]; 685 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 686 if (raw_read) { 687 mv_gpio_polarity(dev, pin, 1, 0); 688 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 689 } else { 690 mv_gpio_polarity(dev, pin, 0, 0); 691 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 692 } 693 694 mv_gpio_debounced_state_set(dev, pin, raw_read); 695 696 return (0); 697 } 698 699 static void 700 mv_gpio_debounce_start(device_t dev, int pin) 701 { 702 struct callout *c; 703 struct mv_gpio_pindev s = {dev, pin}; 704 struct mv_gpio_pindev *sd; 705 struct mv_gpio_softc *sc; 706 sc = (struct mv_gpio_softc *)device_get_softc(dev); 707 708 MV_GPIO_ASSERT_LOCKED(); 709 710 c = sc->debounce_callouts[pin]; 711 if (c == NULL) { 712 mv_gpio_int_ack(&s); 713 return; 714 } 715 716 if (callout_pending(c) || callout_active(c)) { 717 mv_gpio_int_ack(&s); 718 return; 719 } 720 721 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 722 M_DEVBUF, M_WAITOK); 723 if (sd == NULL) { 724 mv_gpio_int_ack(&s); 725 return; 726 } 727 sd->pin = pin; 728 sd->dev = dev; 729 730 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 731 } 732 733 static void 734 mv_gpio_debounce(void *arg) 735 { 736 uint8_t raw_read, last_state; 737 int pin; 738 device_t dev; 739 int *debounce_counter; 740 struct mv_gpio_softc *sc; 741 struct mv_gpio_pindev *s; 742 743 s = (struct mv_gpio_pindev *)arg; 744 dev = s->dev; 745 pin = s->pin; 746 sc = (struct mv_gpio_softc *)device_get_softc(dev); 747 748 MV_GPIO_LOCK(); 749 750 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 751 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 752 debounce_counter = &sc->debounce_counters[pin]; 753 754 if (raw_read == last_state) { 755 if (last_state) 756 *debounce_counter = DEBOUNCE_HI_LO_MS / 757 DEBOUNCE_CHECK_MS; 758 else 759 *debounce_counter = DEBOUNCE_LO_HI_MS / 760 DEBOUNCE_CHECK_MS; 761 762 callout_reset(sc->debounce_callouts[pin], 763 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 764 } else { 765 *debounce_counter = *debounce_counter - 1; 766 if (*debounce_counter != 0) 767 callout_reset(sc->debounce_callouts[pin], 768 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 769 else { 770 mv_gpio_debounced_state_set(dev, pin, raw_read); 771 772 if (last_state) 773 *debounce_counter = DEBOUNCE_HI_LO_MS / 774 DEBOUNCE_CHECK_MS; 775 else 776 *debounce_counter = DEBOUNCE_LO_HI_MS / 777 DEBOUNCE_CHECK_MS; 778 779 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 780 (raw_read == 0)) || 781 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 782 raw_read) || 783 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 784 mv_gpio_intr_handler(dev, pin); 785 786 /* Toggle polarity for next edge. */ 787 mv_gpio_polarity(dev, pin, 0, 1); 788 789 free(arg, M_DEVBUF); 790 callout_deactivate(sc->debounce_callouts[pin]); 791 } 792 } 793 794 MV_GPIO_UNLOCK(); 795 } 796 797 static void 798 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 799 { 800 uint32_t *old_state; 801 struct mv_gpio_softc *sc; 802 sc = (struct mv_gpio_softc *)device_get_softc(dev); 803 804 MV_GPIO_ASSERT_LOCKED(); 805 806 if (pin >= GPIO_PINS_PER_REG) { 807 old_state = &sc->debounced_state_hi; 808 pin -= GPIO_PINS_PER_REG; 809 } else 810 old_state = &sc->debounced_state_lo; 811 812 if (new_state) 813 *old_state |= (1 << pin); 814 else 815 *old_state &= ~(1 << pin); 816 } 817 818 static uint32_t 819 mv_gpio_debounced_state_get(device_t dev, int pin) 820 { 821 uint32_t *state; 822 struct mv_gpio_softc *sc; 823 sc = (struct mv_gpio_softc *)device_get_softc(dev); 824 825 MV_GPIO_ASSERT_LOCKED(); 826 827 if (pin >= GPIO_PINS_PER_REG) { 828 state = &sc->debounced_state_hi; 829 pin -= GPIO_PINS_PER_REG; 830 } else 831 state = &sc->debounced_state_lo; 832 833 return (*state & (1 << pin)); 834 } 835 836 void 837 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 838 { 839 struct mv_gpio_softc *sc; 840 sc = (struct mv_gpio_softc *)device_get_softc(dev); 841 842 MV_GPIO_LOCK(); 843 844 mv_gpio_value_set(dev, pin, val); 845 mv_gpio_out_en(dev, pin, enable); 846 847 MV_GPIO_UNLOCK(); 848 } 849 850 uint8_t 851 mv_gpio_in(device_t dev, uint32_t pin) 852 { 853 uint8_t state; 854 struct mv_gpio_softc *sc; 855 sc = (struct mv_gpio_softc *)device_get_softc(dev); 856 857 MV_GPIO_ASSERT_LOCKED(); 858 859 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 860 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 861 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 862 else 863 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 864 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 865 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 866 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 867 else 868 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 869 } else 870 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 871 872 return (state); 873 } 874 875 static uint32_t 876 mv_gpio_reg_read(device_t dev, uint32_t reg) 877 { 878 struct mv_gpio_softc *sc; 879 sc = (struct mv_gpio_softc *)device_get_softc(dev); 880 881 return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg)); 882 } 883 884 static void 885 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 886 { 887 struct mv_gpio_softc *sc; 888 sc = (struct mv_gpio_softc *)device_get_softc(dev); 889 890 bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val); 891 } 892 893 static void 894 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 895 { 896 uint32_t reg_val; 897 898 reg_val = mv_gpio_reg_read(dev, reg); 899 reg_val |= GPIO(pin); 900 mv_gpio_reg_write(dev, reg, reg_val); 901 } 902 903 static void 904 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 905 { 906 uint32_t reg_val; 907 908 reg_val = mv_gpio_reg_read(dev, reg); 909 reg_val &= ~(GPIO(pin)); 910 mv_gpio_reg_write(dev, reg, reg_val); 911 } 912 913 static void 914 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 915 { 916 uint32_t reg; 917 struct mv_gpio_softc *sc; 918 sc = (struct mv_gpio_softc *)device_get_softc(dev); 919 920 if (pin >= sc->pin_num) 921 return; 922 923 reg = GPIO_DATA_OUT_EN_CTRL; 924 925 if (enable) 926 mv_gpio_reg_clear(dev, reg, pin); 927 else 928 mv_gpio_reg_set(dev, reg, pin); 929 } 930 931 static void 932 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 933 { 934 uint32_t reg; 935 struct mv_gpio_softc *sc; 936 sc = (struct mv_gpio_softc *)device_get_softc(dev); 937 938 if (pin >= sc->pin_num) 939 return; 940 941 reg = GPIO_BLINK_EN; 942 943 if (enable) 944 mv_gpio_reg_set(dev, reg, pin); 945 else 946 mv_gpio_reg_clear(dev, reg, pin); 947 } 948 949 static void 950 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 951 { 952 uint32_t reg, reg_val; 953 struct mv_gpio_softc *sc; 954 sc = (struct mv_gpio_softc *)device_get_softc(dev); 955 956 if (pin >= sc->pin_num) 957 return; 958 959 reg = GPIO_DATA_IN_POLAR; 960 961 if (toggle) { 962 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 963 if (reg_val) 964 mv_gpio_reg_clear(dev, reg, pin); 965 else 966 mv_gpio_reg_set(dev, reg, pin); 967 } else if (enable) 968 mv_gpio_reg_set(dev, reg, pin); 969 else 970 mv_gpio_reg_clear(dev, reg, pin); 971 } 972 973 static void 974 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 975 { 976 uint32_t reg; 977 struct mv_gpio_softc *sc; 978 sc = (struct mv_gpio_softc *)device_get_softc(dev); 979 980 if (pin >= sc->pin_num) 981 return; 982 983 reg = GPIO_INT_LEV_MASK; 984 985 if (enable) 986 mv_gpio_reg_set(dev, reg, pin); 987 else 988 mv_gpio_reg_clear(dev, reg, pin); 989 } 990 991 static void 992 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 993 { 994 uint32_t reg; 995 struct mv_gpio_softc *sc; 996 sc = (struct mv_gpio_softc *)device_get_softc(dev); 997 998 if (pin >= sc->pin_num) 999 return; 1000 1001 reg = GPIO_INT_EDGE_MASK; 1002 1003 if (enable) 1004 mv_gpio_reg_set(dev, reg, pin); 1005 else 1006 mv_gpio_reg_clear(dev, reg, pin); 1007 } 1008 1009 static void 1010 mv_gpio_int_ack(struct mv_gpio_pindev *s) 1011 { 1012 uint32_t reg, pin; 1013 struct mv_gpio_softc *sc; 1014 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 1015 pin = s->pin; 1016 1017 if (pin >= sc->pin_num) 1018 return; 1019 1020 reg = GPIO_INT_CAUSE; 1021 1022 mv_gpio_reg_clear(s->dev, reg, pin); 1023 } 1024 1025 static uint32_t 1026 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 1027 { 1028 uint32_t reg, polar_reg, reg_val, polar_reg_val; 1029 struct mv_gpio_softc *sc; 1030 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1031 1032 if (pin >= sc->pin_num) 1033 return (0); 1034 1035 reg = GPIO_DATA_IN; 1036 polar_reg = GPIO_DATA_IN_POLAR; 1037 1038 reg_val = mv_gpio_reg_read(dev, reg); 1039 1040 if (exclude_polar) { 1041 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 1042 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 1043 } else 1044 return (reg_val & GPIO(pin)); 1045 } 1046 1047 static void 1048 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 1049 { 1050 uint32_t reg; 1051 struct mv_gpio_softc *sc; 1052 sc = (struct mv_gpio_softc *)device_get_softc(dev); 1053 1054 MV_GPIO_ASSERT_LOCKED(); 1055 1056 if (pin >= sc->pin_num) 1057 return; 1058 1059 reg = GPIO_DATA_OUT; 1060 1061 if (val) 1062 mv_gpio_reg_set(dev, reg, pin); 1063 else 1064 mv_gpio_reg_clear(dev, reg, pin); 1065 } 1066 1067 /* 1068 * GPIO interface methods 1069 */ 1070 1071 static int 1072 mv_gpio_pin_max(device_t dev, int *maxpin) 1073 { 1074 struct mv_gpio_softc *sc; 1075 if (maxpin == NULL) 1076 return (EINVAL); 1077 1078 sc = device_get_softc(dev); 1079 *maxpin = sc->pin_num; 1080 1081 return (0); 1082 } 1083 1084 static int 1085 mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 1086 { 1087 struct mv_gpio_softc *sc = device_get_softc(dev); 1088 if (caps == NULL) 1089 return (EINVAL); 1090 1091 if (pin >= sc->pin_num) 1092 return (EINVAL); 1093 1094 MV_GPIO_LOCK(); 1095 *caps = sc->gpio_setup[pin].gp_caps; 1096 MV_GPIO_UNLOCK(); 1097 1098 return (0); 1099 } 1100 1101 static int 1102 mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 1103 { 1104 struct mv_gpio_softc *sc = device_get_softc(dev); 1105 if (flags == NULL) 1106 return (EINVAL); 1107 1108 if (pin >= sc->pin_num) 1109 return (EINVAL); 1110 1111 MV_GPIO_LOCK(); 1112 *flags = sc->gpio_setup[pin].gp_flags; 1113 MV_GPIO_UNLOCK(); 1114 1115 return (0); 1116 } 1117 1118 static int 1119 mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 1120 { 1121 struct mv_gpio_softc *sc = device_get_softc(dev); 1122 if (name == NULL) 1123 return (EINVAL); 1124 1125 if (pin >= sc->pin_num) 1126 return (EINVAL); 1127 1128 MV_GPIO_LOCK(); 1129 memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); 1130 MV_GPIO_UNLOCK(); 1131 1132 return (0); 1133 } 1134 1135 static int 1136 mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 1137 { 1138 int ret; 1139 struct mv_gpio_softc *sc = device_get_softc(dev); 1140 if (pin >= sc->pin_num) 1141 return (EINVAL); 1142 1143 /* Check for unwanted flags. */ 1144 if ((flags & sc->gpio_setup[pin].gp_caps) != flags) 1145 return (EINVAL); 1146 1147 ret = mv_gpio_configure(dev, pin, flags, ~0); 1148 1149 return (ret); 1150 } 1151 1152 static int 1153 mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 1154 { 1155 struct mv_gpio_softc *sc = device_get_softc(dev); 1156 if (pin >= sc->pin_num) 1157 return (EINVAL); 1158 1159 MV_GPIO_LOCK(); 1160 mv_gpio_value_set(dev, pin, value); 1161 MV_GPIO_UNLOCK(); 1162 1163 return (0); 1164 } 1165 1166 static int 1167 mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 1168 { 1169 struct mv_gpio_softc *sc = device_get_softc(dev); 1170 if (value == NULL) 1171 return (EINVAL); 1172 1173 if (pin >= sc->pin_num) 1174 return (EINVAL); 1175 1176 MV_GPIO_LOCK(); 1177 *value = mv_gpio_in(dev, pin); 1178 MV_GPIO_UNLOCK(); 1179 1180 return (0); 1181 } 1182 1183 static int 1184 mv_gpio_pin_toggle(device_t dev, uint32_t pin) 1185 { 1186 struct mv_gpio_softc *sc = device_get_softc(dev); 1187 uint32_t value; 1188 if (pin >= sc->pin_num) 1189 return (EINVAL); 1190 1191 MV_GPIO_LOCK(); 1192 value = mv_gpio_in(dev, pin); 1193 value = (~value) & 1; 1194 mv_gpio_value_set(dev, pin, value); 1195 MV_GPIO_UNLOCK(); 1196 1197 return (0); 1198 } 1199 1200 static device_t 1201 mv_gpio_get_bus(device_t dev) 1202 { 1203 struct mv_gpio_softc *sc = device_get_softc(dev); 1204 1205 return (sc->sc_busdev); 1206 } 1207 1208 static int 1209 mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 1210 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 1211 { 1212 struct mv_gpio_softc *sc = device_get_softc(bus); 1213 1214 if (gpios[0] >= sc->pin_num) 1215 return (EINVAL); 1216 1217 *pin = gpios[0]; 1218 *flags = gpios[1]; 1219 mv_gpio_configure(bus, *pin, *flags, ~0); 1220 1221 return (0); 1222 } 1223