1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2017 Semihalf. 7 * All rights reserved. 8 * 9 * Adapted and extended for Marvell SoCs by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/interrupt.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/mutex.h> 46 #include <sys/rman.h> 47 #include <sys/queue.h> 48 #include <sys/timetc.h> 49 #include <sys/callout.h> 50 #include <sys/gpio.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 54 #include <dev/fdt/fdt_common.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #define GPIO_MAX_INTR_COUNT 8 62 #define GPIO_PINS_PER_REG 32 63 64 #define DEBOUNCE_CHECK_MS 1 65 #define DEBOUNCE_LO_HI_MS 2 66 #define DEBOUNCE_HI_LO_MS 2 67 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) 68 69 struct mv_gpio_softc { 70 struct resource * mem_res; 71 int mem_rid; 72 struct resource * irq_res[GPIO_MAX_INTR_COUNT]; 73 int irq_rid[GPIO_MAX_INTR_COUNT]; 74 struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; 75 void *ih_cookie[GPIO_MAX_INTR_COUNT]; 76 bus_space_tag_t bst; 77 bus_space_handle_t bsh; 78 struct mtx mutex; 79 uint8_t pin_num; /* number of GPIO pins */ 80 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ 81 struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; 82 83 /* Used for debouncing. */ 84 uint32_t debounced_state_lo; 85 uint32_t debounced_state_hi; 86 struct callout **debounce_callouts; 87 int *debounce_counters; 88 }; 89 90 struct mv_gpio_pindev { 91 device_t dev; 92 int pin; 93 }; 94 95 static int mv_gpio_probe(device_t); 96 static int mv_gpio_attach(device_t); 97 static int mv_gpio_intr(device_t, void *); 98 static int mv_gpio_init(device_t); 99 100 static void mv_gpio_double_edge_init(device_t, int); 101 102 static int mv_gpio_debounce_setup(device_t, int); 103 static int mv_gpio_debounce_prepare(device_t, int); 104 static int mv_gpio_debounce_init(device_t, int); 105 static void mv_gpio_debounce_start(device_t, int); 106 static void mv_gpio_debounce(void *); 107 static void mv_gpio_debounced_state_set(device_t, int, uint8_t); 108 static uint32_t mv_gpio_debounced_state_get(device_t, int); 109 110 static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); 111 static void mv_gpio_intr_handler(device_t, int); 112 static uint32_t mv_gpio_reg_read(device_t, uint32_t); 113 static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); 114 static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); 115 static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); 116 117 static void mv_gpio_blink(device_t, uint32_t, uint8_t); 118 static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); 119 static void mv_gpio_level(device_t, uint32_t, uint8_t); 120 static void mv_gpio_edge(device_t, uint32_t, uint8_t); 121 static void mv_gpio_out_en(device_t, uint32_t, uint8_t); 122 static void mv_gpio_int_ack(struct mv_gpio_pindev *); 123 static void mv_gpio_value_set(device_t, uint32_t, uint8_t); 124 static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); 125 126 static void mv_gpio_intr_mask(struct mv_gpio_pindev *); 127 static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); 128 129 void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); 130 int mv_gpio_setup_intrhandler(device_t, const char *, 131 driver_filter_t *, void (*)(void *), void *, 132 int, int, void **); 133 int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); 134 void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); 135 uint8_t mv_gpio_in(device_t, uint32_t); 136 137 #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) 138 #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) 139 #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) 140 141 static device_method_t mv_gpio_methods[] = { 142 DEVMETHOD(device_probe, mv_gpio_probe), 143 DEVMETHOD(device_attach, mv_gpio_attach), 144 { 0, 0 } 145 }; 146 147 static driver_t mv_gpio_driver = { 148 "gpio", 149 mv_gpio_methods, 150 sizeof(struct mv_gpio_softc), 151 }; 152 153 static devclass_t mv_gpio_devclass; 154 155 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); 156 157 typedef int (*gpios_phandler_t)(device_t, phandle_t, pcell_t *, int); 158 159 struct gpio_ctrl_entry { 160 const char *compat; 161 gpios_phandler_t handler; 162 }; 163 164 static int mv_handle_gpios_prop(device_t, phandle_t, pcell_t *, int); 165 int gpio_get_config_from_dt(void); 166 167 struct gpio_ctrl_entry gpio_controllers[] = { 168 { "mrvl,gpio", &mv_handle_gpios_prop }, 169 { NULL, NULL } 170 }; 171 172 static int 173 mv_gpio_probe(device_t dev) 174 { 175 176 if (!ofw_bus_status_okay(dev)) 177 return (ENXIO); 178 179 if (!ofw_bus_is_compatible(dev, "mrvl,gpio")) 180 return (ENXIO); 181 182 device_set_desc(dev, "Marvell Integrated GPIO Controller"); 183 return (0); 184 } 185 186 static int 187 mv_gpio_attach(device_t dev) 188 { 189 int error, i, size; 190 struct mv_gpio_softc *sc; 191 uint32_t dev_id, rev_id; 192 pcell_t pincnt = 0; 193 pcell_t irq_cells = 0; 194 phandle_t iparent; 195 196 sc = (struct mv_gpio_softc *)device_get_softc(dev); 197 if (sc == NULL) 198 return (ENXIO); 199 200 /* Get chip id and revision */ 201 soc_id(&dev_id, &rev_id); 202 203 if (dev_id == MV_DEV_88F5182 || 204 dev_id == MV_DEV_88F5281 || 205 dev_id == MV_DEV_MV78100 || 206 dev_id == MV_DEV_MV78100_Z0 ) { 207 sc->pin_num = 32; 208 sc->irq_num = 4; 209 210 } else if (dev_id == MV_DEV_88F6281 || 211 dev_id == MV_DEV_88F6282) { 212 sc->pin_num = 50; 213 sc->irq_num = 7; 214 215 } else { 216 if (OF_getencprop(ofw_bus_get_node(dev), "pin-count", &pincnt, 217 sizeof(pcell_t)) >= 0 || 218 OF_getencprop(ofw_bus_get_node(dev), "ngpios", &pincnt, 219 sizeof(pcell_t)) >= 0) { 220 sc->pin_num = pincnt; 221 device_printf(dev, "%d pins available\n", sc->pin_num); 222 } else { 223 device_printf(dev, "ERROR: no pin-count entry found!\n"); 224 return (ENXIO); 225 } 226 } 227 228 /* Find root interrupt controller */ 229 iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev)); 230 if (iparent == 0) { 231 device_printf(dev, "No interrupt-parrent found. " 232 "Error in DTB\n"); 233 return (ENXIO); 234 } else { 235 /* While at parent - store interrupt cells prop */ 236 if (OF_searchencprop(OF_node_from_xref(iparent), 237 "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { 238 device_printf(dev, "DTB: Missing #interrupt-cells " 239 "property in interrupt parent node\n"); 240 return (ENXIO); 241 } 242 } 243 244 size = OF_getproplen(ofw_bus_get_node(dev), "interrupts"); 245 if (size != -1) { 246 size = size / sizeof(pcell_t); 247 size = size / irq_cells; 248 sc->irq_num = size; 249 device_printf(dev, "%d IRQs available\n", sc->irq_num); 250 } else { 251 device_printf(dev, "ERROR: no interrupts entry found!\n"); 252 return (ENXIO); 253 } 254 255 sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * 256 sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); 257 if (sc->debounce_callouts == NULL) 258 return (ENOMEM); 259 260 sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), 261 M_DEVBUF, M_WAITOK); 262 if (sc->debounce_counters == NULL) 263 return (ENOMEM); 264 265 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 266 267 sc->mem_rid = 0; 268 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 269 RF_ACTIVE); 270 271 if (!sc->mem_res) { 272 mtx_destroy(&sc->mutex); 273 device_printf(dev, "could not allocate memory window\n"); 274 return (ENXIO); 275 } 276 277 sc->bst = rman_get_bustag(sc->mem_res); 278 sc->bsh = rman_get_bushandle(sc->mem_res); 279 280 for (i = 0; i < sc->irq_num; i++) { 281 sc->irq_rid[i] = i; 282 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, 283 &sc->irq_rid[i], RF_ACTIVE); 284 if (!sc->irq_res[i]) { 285 mtx_destroy(&sc->mutex); 286 device_printf(dev, 287 "could not allocate gpio%d interrupt\n", i+1); 288 return (ENXIO); 289 } 290 } 291 292 /* Disable all interrupts */ 293 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0); 294 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0); 295 296 for (i = 0; i < sc->irq_num; i++) { 297 if (bus_setup_intr(dev, sc->irq_res[i], 298 INTR_TYPE_MISC, 299 (driver_filter_t *)mv_gpio_intr, NULL, 300 sc, &sc->ih_cookie[i]) != 0) { 301 mtx_destroy(&sc->mutex); 302 bus_release_resource(dev, SYS_RES_IRQ, 303 sc->irq_rid[i], sc->irq_res[i]); 304 device_printf(dev, "could not set up intr %d\n", i); 305 return (ENXIO); 306 } 307 } 308 309 error = mv_gpio_init(dev); 310 if (error) { 311 device_printf(dev, "WARNING: failed to initialize GPIO pins, " 312 "error = %d\n", error); 313 } 314 315 /* Clear interrupt status. */ 316 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0); 317 318 device_add_child(dev, "gpioc", device_get_unit(dev)); 319 device_add_child(dev, "gpiobus", device_get_unit(dev)); 320 321 return (0); 322 } 323 324 static int 325 mv_gpio_intr(device_t dev, void *arg) 326 { 327 uint32_t int_cause, gpio_val; 328 struct mv_gpio_softc *sc; 329 sc = (struct mv_gpio_softc *)device_get_softc(dev); 330 331 MV_GPIO_LOCK(); 332 333 /* 334 * According to documentation, edge sensitive interrupts are asserted 335 * when unmasked GPIO_INT_CAUSE register bits are set. 336 */ 337 int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); 338 int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); 339 340 /* 341 * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN 342 * register bits are set. 343 */ 344 gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); 345 gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); 346 347 mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); 348 349 MV_GPIO_UNLOCK(); 350 351 return (FILTER_HANDLED); 352 } 353 354 /* 355 * GPIO interrupt handling 356 */ 357 358 void 359 mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) 360 { 361 /* When we acheive full interrupt support 362 * This function will be opposite to 363 * mv_gpio_setup_intrhandler 364 */ 365 366 /* Now it exists only to remind that 367 * there should be place to free mv_gpio_pindev 368 * allocated by mv_gpio_setup_intrhandler 369 */ 370 free(s, M_DEVBUF); 371 } 372 373 int 374 mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, 375 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) 376 { 377 struct intr_event *event; 378 int error; 379 struct mv_gpio_pindev *s; 380 struct mv_gpio_softc *sc; 381 sc = (struct mv_gpio_softc *)device_get_softc(dev); 382 s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); 383 384 if (pin < 0 || pin >= sc->pin_num) 385 return (ENXIO); 386 event = sc->gpio_events[pin]; 387 if (event == NULL) { 388 MV_GPIO_LOCK(); 389 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 390 error = mv_gpio_debounce_init(dev, pin); 391 if (error != 0) { 392 MV_GPIO_UNLOCK(); 393 return (error); 394 } 395 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) 396 mv_gpio_double_edge_init(dev, pin); 397 MV_GPIO_UNLOCK(); 398 error = intr_event_create(&event, (void *)s, 0, pin, 399 (void (*)(void *))mv_gpio_intr_mask, 400 (void (*)(void *))mv_gpio_intr_unmask, 401 (void (*)(void *))mv_gpio_int_ack, 402 NULL, 403 "gpio%d:", pin); 404 if (error != 0) 405 return (error); 406 sc->gpio_events[pin] = event; 407 } 408 409 intr_event_add_handler(event, name, filt, hand, arg, 410 intr_priority(flags), flags, cookiep); 411 return (0); 412 } 413 414 static void 415 mv_gpio_intr_mask(struct mv_gpio_pindev *s) 416 { 417 struct mv_gpio_softc *sc; 418 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 419 420 if (s->pin >= sc->pin_num) 421 return; 422 423 MV_GPIO_LOCK(); 424 425 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 426 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 427 mv_gpio_edge(s->dev, s->pin, 0); 428 else 429 mv_gpio_level(s->dev, s->pin, 0); 430 431 /* 432 * The interrupt has to be acknowledged before scheduling an interrupt 433 * thread. This way we allow for interrupt source to trigger again 434 * (which can happen with shared IRQs e.g. PCI) while processing the 435 * current event. 436 */ 437 mv_gpio_int_ack(s); 438 439 MV_GPIO_UNLOCK(); 440 441 return; 442 } 443 444 static void 445 mv_gpio_intr_unmask(struct mv_gpio_pindev *s) 446 { 447 struct mv_gpio_softc *sc; 448 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 449 450 if (s->pin >= sc->pin_num) 451 return; 452 453 MV_GPIO_LOCK(); 454 455 if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | 456 MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 457 mv_gpio_edge(s->dev, s->pin, 1); 458 else 459 mv_gpio_level(s->dev, s->pin, 1); 460 461 MV_GPIO_UNLOCK(); 462 463 return; 464 } 465 466 static void 467 mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) 468 { 469 int i, pin; 470 struct mv_gpio_softc *sc; 471 sc = (struct mv_gpio_softc *)device_get_softc(dev); 472 473 MV_GPIO_ASSERT_LOCKED(); 474 475 i = 0; 476 while (status != 0) { 477 if (status & 1) { 478 pin = (high ? (i + GPIO_PINS_PER_REG) : i); 479 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) 480 mv_gpio_debounce_start(dev, pin); 481 else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 482 mv_gpio_polarity(dev, pin, 0, 1); 483 mv_gpio_intr_handler(dev, pin); 484 } else 485 mv_gpio_intr_handler(dev, pin); 486 } 487 status >>= 1; 488 i++; 489 } 490 } 491 492 static void 493 mv_gpio_intr_handler(device_t dev, int pin) 494 { 495 #ifdef INTRNG 496 struct intr_irqsrc isrc; 497 struct mv_gpio_softc *sc; 498 sc = (struct mv_gpio_softc *)device_get_softc(dev); 499 500 MV_GPIO_ASSERT_LOCKED(); 501 502 #ifdef INTR_SOLO 503 isrc.isrc_filter = NULL; 504 #endif 505 isrc.isrc_event = sc->gpio_events[pin]; 506 507 if (isrc.isrc_event == NULL || TAILQ_EMPTY(&isrc.isrc_event->ie_handlers)) 508 return; 509 510 intr_isrc_dispatch(&isrc, NULL); 511 #endif 512 } 513 514 int 515 mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) 516 { 517 int error; 518 struct mv_gpio_softc *sc; 519 sc = (struct mv_gpio_softc *)device_get_softc(dev); 520 error = 0; 521 522 if (pin >= sc->pin_num) 523 return (EINVAL); 524 525 /* check flags consistency */ 526 if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 527 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) 528 return (EINVAL); 529 530 if (mask & MV_GPIO_IN_DEBOUNCE) { 531 error = mv_gpio_debounce_prepare(dev, pin); 532 if (error != 0) 533 return (error); 534 } 535 536 MV_GPIO_LOCK(); 537 538 if (mask & MV_GPIO_OUT_BLINK) 539 mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); 540 if (mask & MV_GPIO_IN_POL_LOW) 541 mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); 542 if (mask & MV_GPIO_IN_DEBOUNCE) { 543 error = mv_gpio_debounce_setup(dev, pin); 544 if (error) { 545 MV_GPIO_UNLOCK(); 546 return (error); 547 } 548 } 549 550 sc->gpio_setup[pin].gp_flags &= ~(mask); 551 sc->gpio_setup[pin].gp_flags |= (flags & mask); 552 553 MV_GPIO_UNLOCK(); 554 555 return (0); 556 } 557 558 static void 559 mv_gpio_double_edge_init(device_t dev, int pin) 560 { 561 uint8_t raw_read; 562 struct mv_gpio_softc *sc; 563 sc = (struct mv_gpio_softc *)device_get_softc(dev); 564 565 MV_GPIO_ASSERT_LOCKED(); 566 567 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 568 569 if (raw_read) 570 mv_gpio_polarity(dev, pin, 1, 0); 571 else 572 mv_gpio_polarity(dev, pin, 0, 0); 573 } 574 575 static int 576 mv_gpio_debounce_setup(device_t dev, int pin) 577 { 578 struct callout *c; 579 struct mv_gpio_softc *sc; 580 581 sc = (struct mv_gpio_softc *)device_get_softc(dev); 582 583 MV_GPIO_ASSERT_LOCKED(); 584 585 c = sc->debounce_callouts[pin]; 586 if (c == NULL) 587 return (ENXIO); 588 589 if (callout_active(c)) 590 callout_deactivate(c); 591 592 callout_stop(c); 593 594 return (0); 595 } 596 597 static int 598 mv_gpio_debounce_prepare(device_t dev, int pin) 599 { 600 struct callout *c; 601 struct mv_gpio_softc *sc; 602 603 sc = (struct mv_gpio_softc *)device_get_softc(dev); 604 605 c = sc->debounce_callouts[pin]; 606 if (c == NULL) { 607 c = (struct callout *)malloc(sizeof(struct callout), 608 M_DEVBUF, M_WAITOK); 609 sc->debounce_callouts[pin] = c; 610 if (c == NULL) 611 return (ENOMEM); 612 callout_init(c, 1); 613 } 614 615 return (0); 616 } 617 618 static int 619 mv_gpio_debounce_init(device_t dev, int pin) 620 { 621 uint8_t raw_read; 622 int *cnt; 623 struct mv_gpio_softc *sc; 624 625 sc = (struct mv_gpio_softc *)device_get_softc(dev); 626 627 MV_GPIO_ASSERT_LOCKED(); 628 629 cnt = &sc->debounce_counters[pin]; 630 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 631 if (raw_read) { 632 mv_gpio_polarity(dev, pin, 1, 0); 633 *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; 634 } else { 635 mv_gpio_polarity(dev, pin, 0, 0); 636 *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; 637 } 638 639 mv_gpio_debounced_state_set(dev, pin, raw_read); 640 641 return (0); 642 } 643 644 static void 645 mv_gpio_debounce_start(device_t dev, int pin) 646 { 647 struct callout *c; 648 struct mv_gpio_pindev s = {dev, pin}; 649 struct mv_gpio_pindev *sd; 650 struct mv_gpio_softc *sc; 651 sc = (struct mv_gpio_softc *)device_get_softc(dev); 652 653 MV_GPIO_ASSERT_LOCKED(); 654 655 c = sc->debounce_callouts[pin]; 656 if (c == NULL) { 657 mv_gpio_int_ack(&s); 658 return; 659 } 660 661 if (callout_pending(c) || callout_active(c)) { 662 mv_gpio_int_ack(&s); 663 return; 664 } 665 666 sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), 667 M_DEVBUF, M_WAITOK); 668 if (sd == NULL) { 669 mv_gpio_int_ack(&s); 670 return; 671 } 672 sd->pin = pin; 673 sd->dev = dev; 674 675 callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); 676 } 677 678 static void 679 mv_gpio_debounce(void *arg) 680 { 681 uint8_t raw_read, last_state; 682 int pin; 683 device_t dev; 684 int *debounce_counter; 685 struct mv_gpio_softc *sc; 686 struct mv_gpio_pindev *s; 687 688 s = (struct mv_gpio_pindev *)arg; 689 dev = s->dev; 690 pin = s->pin; 691 sc = (struct mv_gpio_softc *)device_get_softc(dev); 692 693 MV_GPIO_LOCK(); 694 695 raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 696 last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 697 debounce_counter = &sc->debounce_counters[pin]; 698 699 if (raw_read == last_state) { 700 if (last_state) 701 *debounce_counter = DEBOUNCE_HI_LO_MS / 702 DEBOUNCE_CHECK_MS; 703 else 704 *debounce_counter = DEBOUNCE_LO_HI_MS / 705 DEBOUNCE_CHECK_MS; 706 707 callout_reset(sc->debounce_callouts[pin], 708 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 709 } else { 710 *debounce_counter = *debounce_counter - 1; 711 if (*debounce_counter != 0) 712 callout_reset(sc->debounce_callouts[pin], 713 DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); 714 else { 715 mv_gpio_debounced_state_set(dev, pin, raw_read); 716 717 if (last_state) 718 *debounce_counter = DEBOUNCE_HI_LO_MS / 719 DEBOUNCE_CHECK_MS; 720 else 721 *debounce_counter = DEBOUNCE_LO_HI_MS / 722 DEBOUNCE_CHECK_MS; 723 724 if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && 725 (raw_read == 0)) || 726 (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && 727 raw_read) || 728 (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) 729 mv_gpio_intr_handler(dev, pin); 730 731 /* Toggle polarity for next edge. */ 732 mv_gpio_polarity(dev, pin, 0, 1); 733 734 free(arg, M_DEVBUF); 735 callout_deactivate(sc->debounce_callouts[pin]); 736 } 737 } 738 739 MV_GPIO_UNLOCK(); 740 } 741 742 static void 743 mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) 744 { 745 uint32_t *old_state; 746 struct mv_gpio_softc *sc; 747 sc = (struct mv_gpio_softc *)device_get_softc(dev); 748 749 MV_GPIO_ASSERT_LOCKED(); 750 751 if (pin >= GPIO_PINS_PER_REG) { 752 old_state = &sc->debounced_state_hi; 753 pin -= GPIO_PINS_PER_REG; 754 } else 755 old_state = &sc->debounced_state_lo; 756 757 if (new_state) 758 *old_state |= (1 << pin); 759 else 760 *old_state &= ~(1 << pin); 761 } 762 763 static uint32_t 764 mv_gpio_debounced_state_get(device_t dev, int pin) 765 { 766 uint32_t *state; 767 struct mv_gpio_softc *sc; 768 sc = (struct mv_gpio_softc *)device_get_softc(dev); 769 770 MV_GPIO_ASSERT_LOCKED(); 771 772 if (pin >= GPIO_PINS_PER_REG) { 773 state = &sc->debounced_state_hi; 774 pin -= GPIO_PINS_PER_REG; 775 } else 776 state = &sc->debounced_state_lo; 777 778 return (*state & (1 << pin)); 779 } 780 781 void 782 mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) 783 { 784 struct mv_gpio_softc *sc; 785 sc = (struct mv_gpio_softc *)device_get_softc(dev); 786 787 MV_GPIO_LOCK(); 788 789 mv_gpio_value_set(dev, pin, val); 790 mv_gpio_out_en(dev, pin, enable); 791 792 MV_GPIO_UNLOCK(); 793 } 794 795 uint8_t 796 mv_gpio_in(device_t dev, uint32_t pin) 797 { 798 uint8_t state; 799 struct mv_gpio_softc *sc; 800 sc = (struct mv_gpio_softc *)device_get_softc(dev); 801 802 MV_GPIO_LOCK(); 803 804 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { 805 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 806 state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); 807 else 808 state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); 809 } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { 810 if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) 811 state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); 812 else 813 state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); 814 } else 815 state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); 816 817 818 return (state); 819 } 820 821 static uint32_t 822 mv_gpio_reg_read(device_t dev, uint32_t reg) 823 { 824 struct mv_gpio_softc *sc; 825 sc = (struct mv_gpio_softc *)device_get_softc(dev); 826 827 return (bus_space_read_4(sc->bst, sc->bsh, reg)); 828 } 829 830 static void 831 mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) 832 { 833 struct mv_gpio_softc *sc; 834 sc = (struct mv_gpio_softc *)device_get_softc(dev); 835 836 bus_space_write_4(sc->bst, sc->bsh, reg, val); 837 } 838 839 static void 840 mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) 841 { 842 uint32_t reg_val; 843 844 reg_val = mv_gpio_reg_read(dev, reg); 845 reg_val |= GPIO(pin); 846 mv_gpio_reg_write(dev, reg, reg_val); 847 } 848 849 static void 850 mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) 851 { 852 uint32_t reg_val; 853 854 reg_val = mv_gpio_reg_read(dev, reg); 855 reg_val &= ~(GPIO(pin)); 856 mv_gpio_reg_write(dev, reg, reg_val); 857 } 858 859 static void 860 mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) 861 { 862 uint32_t reg; 863 struct mv_gpio_softc *sc; 864 sc = (struct mv_gpio_softc *)device_get_softc(dev); 865 866 if (pin >= sc->pin_num) 867 return; 868 869 reg = GPIO_DATA_OUT_EN_CTRL; 870 871 if (enable) 872 mv_gpio_reg_clear(dev, reg, pin); 873 else 874 mv_gpio_reg_set(dev, reg, pin); 875 } 876 877 static void 878 mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) 879 { 880 uint32_t reg; 881 struct mv_gpio_softc *sc; 882 sc = (struct mv_gpio_softc *)device_get_softc(dev); 883 884 if (pin >= sc->pin_num) 885 return; 886 887 reg = GPIO_BLINK_EN; 888 889 if (enable) 890 mv_gpio_reg_set(dev, reg, pin); 891 else 892 mv_gpio_reg_clear(dev, reg, pin); 893 } 894 895 static void 896 mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) 897 { 898 uint32_t reg, reg_val; 899 struct mv_gpio_softc *sc; 900 sc = (struct mv_gpio_softc *)device_get_softc(dev); 901 902 if (pin >= sc->pin_num) 903 return; 904 905 reg = GPIO_DATA_IN_POLAR; 906 907 if (toggle) { 908 reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); 909 if (reg_val) 910 mv_gpio_reg_clear(dev, reg, pin); 911 else 912 mv_gpio_reg_set(dev, reg, pin); 913 } else if (enable) 914 mv_gpio_reg_set(dev, reg, pin); 915 else 916 mv_gpio_reg_clear(dev, reg, pin); 917 } 918 919 static void 920 mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) 921 { 922 uint32_t reg; 923 struct mv_gpio_softc *sc; 924 sc = (struct mv_gpio_softc *)device_get_softc(dev); 925 926 if (pin >= sc->pin_num) 927 return; 928 929 reg = GPIO_INT_LEV_MASK; 930 931 if (enable) 932 mv_gpio_reg_set(dev, reg, pin); 933 else 934 mv_gpio_reg_clear(dev, reg, pin); 935 } 936 937 static void 938 mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) 939 { 940 uint32_t reg; 941 struct mv_gpio_softc *sc; 942 sc = (struct mv_gpio_softc *)device_get_softc(dev); 943 944 if (pin >= sc->pin_num) 945 return; 946 947 reg = GPIO_INT_EDGE_MASK; 948 949 if (enable) 950 mv_gpio_reg_set(dev, reg, pin); 951 else 952 mv_gpio_reg_clear(dev, reg, pin); 953 } 954 955 static void 956 mv_gpio_int_ack(struct mv_gpio_pindev *s) 957 { 958 uint32_t reg, pin; 959 struct mv_gpio_softc *sc; 960 sc = (struct mv_gpio_softc *)device_get_softc(s->dev); 961 pin = s->pin; 962 963 if (pin >= sc->pin_num) 964 return; 965 966 reg = GPIO_INT_CAUSE; 967 968 mv_gpio_reg_clear(s->dev, reg, pin); 969 } 970 971 static uint32_t 972 mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) 973 { 974 uint32_t reg, polar_reg, reg_val, polar_reg_val; 975 struct mv_gpio_softc *sc; 976 sc = (struct mv_gpio_softc *)device_get_softc(dev); 977 978 if (pin >= sc->pin_num) 979 return (0); 980 981 reg = GPIO_DATA_IN; 982 polar_reg = GPIO_DATA_IN_POLAR; 983 984 reg_val = mv_gpio_reg_read(dev, reg); 985 986 if (exclude_polar) { 987 polar_reg_val = mv_gpio_reg_read(dev, polar_reg); 988 return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); 989 } else 990 return (reg_val & GPIO(pin)); 991 } 992 993 static void 994 mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) 995 { 996 uint32_t reg; 997 struct mv_gpio_softc *sc; 998 sc = (struct mv_gpio_softc *)device_get_softc(dev); 999 1000 if (pin >= sc->pin_num) 1001 return; 1002 1003 reg = GPIO_DATA_OUT; 1004 1005 if (val) 1006 mv_gpio_reg_set(dev, reg, pin); 1007 else 1008 mv_gpio_reg_clear(dev, reg, pin); 1009 } 1010 1011 static int 1012 mv_handle_gpios_prop(device_t dev, phandle_t ctrl, pcell_t *gpios, int len) 1013 { 1014 pcell_t gpio_cells, pincnt; 1015 int inc, t, tuples, tuple_size; 1016 int dir, flags, pin; 1017 u_long gpio_ctrl, size; 1018 struct mv_gpio_softc sc; 1019 1020 pincnt = 0; 1021 if (!OF_hasprop(ctrl, "gpio-controller")) 1022 /* Node is not a GPIO controller. */ 1023 return (ENXIO); 1024 1025 if (OF_getencprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0) 1026 return (ENXIO); 1027 if (gpio_cells != 3) 1028 return (ENXIO); 1029 1030 tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t); 1031 tuples = len / tuple_size; 1032 1033 if (fdt_regsize(ctrl, &gpio_ctrl, &size)) 1034 return (ENXIO); 1035 1036 if (OF_getencprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0) 1037 return (ENXIO); 1038 sc.pin_num = pincnt; 1039 1040 /* 1041 * Skip controller reference, since controller's phandle is given 1042 * explicitly (in a function argument). 1043 */ 1044 inc = sizeof(ihandle_t) / sizeof(pcell_t); 1045 gpios += inc; 1046 1047 for (t = 0; t < tuples; t++) { 1048 pin = gpios[0]; 1049 dir = gpios[1]; 1050 flags = gpios[2]; 1051 1052 mv_gpio_configure(dev, pin, flags, ~0); 1053 1054 if (dir == 1) 1055 /* Input. */ 1056 mv_gpio_out_en(dev, pin, 0); 1057 else { 1058 /* Output. */ 1059 if (flags & MV_GPIO_OUT_OPEN_DRAIN) 1060 mv_gpio_out(dev, pin, 0, 1); 1061 1062 if (flags & MV_GPIO_OUT_OPEN_SRC) 1063 mv_gpio_out(dev, pin, 1, 1); 1064 } 1065 gpios += gpio_cells + inc; 1066 } 1067 1068 return (0); 1069 } 1070 1071 #define MAX_PINS_PER_NODE 5 1072 #define GPIOS_PROP_CELLS 4 1073 static int 1074 mv_gpio_init(device_t dev) 1075 { 1076 phandle_t child, parent, root, ctrl; 1077 pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS]; 1078 struct gpio_ctrl_entry *e; 1079 int len, rv; 1080 1081 root = OF_finddevice("/"); 1082 len = 0; 1083 parent = root; 1084 1085 /* Traverse through entire tree to find nodes with 'gpios' prop */ 1086 for (child = OF_child(parent); child != 0; child = OF_peer(child)) { 1087 1088 /* Find a 'leaf'. Start the search from this node. */ 1089 while (OF_child(child)) { 1090 parent = child; 1091 child = OF_child(child); 1092 } 1093 if ((len = OF_getproplen(child, "gpios")) > 0) { 1094 1095 if (len > sizeof(gpios)) 1096 return (ENXIO); 1097 1098 /* Get 'gpios' property. */ 1099 OF_getencprop(child, "gpios", gpios, len); 1100 1101 e = (struct gpio_ctrl_entry *)&gpio_controllers; 1102 1103 /* Find and call a handler. */ 1104 for (; e->compat; e++) { 1105 /* 1106 * First cell of 'gpios' property should 1107 * contain a ref. to a node defining GPIO 1108 * controller. 1109 */ 1110 ctrl = OF_node_from_xref(gpios[0]); 1111 1112 if (ofw_bus_node_is_compatible(ctrl, e->compat)) 1113 /* Call a handler. */ 1114 if ((rv = e->handler(dev, ctrl, 1115 (pcell_t *)&gpios, len))) 1116 return (rv); 1117 } 1118 } 1119 1120 if (OF_peer(child) == 0) { 1121 /* No more siblings. */ 1122 child = parent; 1123 parent = OF_parent(child); 1124 } 1125 } 1126 return (0); 1127 } 1128