1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 #include <machine/bus.h> 36 37 #include <dev/fdt/simplebus.h> 38 39 #include <dev/extres/clk/clk.h> 40 #include <dev/extres/clk/clk_div.h> 41 #include <dev/extres/clk/clk_fixed.h> 42 #include <dev/extres/clk/clk_gate.h> 43 #include <dev/extres/clk/clk_mux.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "clkdev_if.h" 49 #include "periph.h" 50 51 #define PARENT_CNT 2 52 #define TBG_A_S_OFW_INDEX 0 53 54 /* 55 * Register chain: fixed (freq/2) -> mux (choose fixed or parent frequency) -> 56 * gate (enable or disable clock). 57 */ 58 59 int 60 a37x0_periph_register_mux_gate(struct clkdom *clkdom, 61 struct a37x0_periph_clknode_def *device_def) 62 { 63 const char *parent_names[PARENT_CNT]; 64 struct clk_fixed_def fixed; 65 struct clk_gate_def *gate; 66 struct clk_mux_def *mux; 67 int error, dev_id; 68 69 dev_id = device_def->common_def.device_id; 70 mux = &device_def->clk_def.mux_gate.mux; 71 gate = &device_def->clk_def.mux_gate.gate; 72 fixed = device_def->clk_def.fixed.fixed; 73 74 fixed.clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); 75 fixed.clkdef.parent_names = &device_def->common_def.pname; 76 fixed.clkdef.parent_cnt = 1; 77 fixed.clkdef.flags = 0x0; 78 fixed.mult = 1; 79 fixed.div = 2; 80 fixed.freq = 0; 81 82 error = clknode_fixed_register(clkdom, &fixed); 83 if (error) 84 goto fail; 85 86 parent_names[0] = device_def->common_def.pname; 87 parent_names[1] = fixed.clkdef.name; 88 89 a37x0_periph_set_props(&mux->clkdef, parent_names, PARENT_CNT); 90 error = a37x0_periph_create_mux(clkdom, mux, 91 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 92 if (error) 93 goto fail; 94 95 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); 96 error = a37x0_periph_create_gate(clkdom, gate, 97 dev_id); 98 if (error) 99 goto fail; 100 101 fail: 102 103 return (error); 104 } 105 106 /* 107 * Register chain: fixed1 (freq/2) -> mux (fixed1 or TBG-A-S frequency) -> 108 * gate -> fixed2 (freq/2). 109 */ 110 111 int 112 a37x0_periph_register_mux_gate_fixed(struct clkdom * clkdom, 113 struct a37x0_periph_clknode_def *device_def) 114 { 115 struct clk_fixed_def *fixed1, *fixed2; 116 const char *parent_names[PARENT_CNT]; 117 struct clk_gate_def *gate; 118 struct clk_mux_def *mux; 119 int error, dev_id; 120 121 dev_id = device_def->common_def.device_id; 122 mux = &device_def->clk_def.mux_gate_fixed.mux; 123 gate = &device_def->clk_def.mux_gate_fixed.gate; 124 fixed1 = &device_def->clk_def.mux_gate_fixed.fixed1; 125 fixed2 = &device_def->clk_def.mux_gate_fixed.fixed2; 126 127 fixed1->clkdef.parent_names = &device_def->common_def.pname; 128 fixed1->clkdef.id = A37x0_INTERNAL_CLK_ID(dev_id, FIXED1_POS); 129 fixed1->clkdef.flags = 0x0; 130 fixed1->mult = 1; 131 fixed1->div = 2; 132 fixed1->freq = 0; 133 134 error = clknode_fixed_register(clkdom, fixed1); 135 if (error) 136 goto fail; 137 138 parent_names[0] = device_def->common_def.tbgs[TBG_A_S_OFW_INDEX]; 139 parent_names[1] = fixed1->clkdef.name; 140 141 a37x0_periph_set_props(&mux->clkdef, parent_names, PARENT_CNT); 142 error = a37x0_periph_create_mux(clkdom, mux, 143 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 144 if (error) 145 goto fail; 146 147 a37x0_periph_set_props(&gate->clkdef, &mux->clkdef.name, 1); 148 error = a37x0_periph_create_gate(clkdom, gate, 149 A37x0_INTERNAL_CLK_ID(dev_id, GATE_POS)); 150 if (error) 151 goto fail; 152 153 fixed2->clkdef.parent_names = &gate->clkdef.name; 154 fixed2->clkdef.parent_cnt = 1; 155 fixed2->clkdef.id = dev_id; 156 157 error = clknode_fixed_register(clkdom, fixed2); 158 if (error) 159 goto fail; 160 161 fail: 162 163 return (error); 164 } 165