1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/kernel.h> 32 #include <sys/module.h> 33 #include <sys/mutex.h> 34 #include <sys/rman.h> 35 #include <machine/bus.h> 36 37 #include <dev/fdt/simplebus.h> 38 39 #include <dev/extres/clk/clk.h> 40 #include <dev/extres/clk/clk_div.h> 41 #include <dev/extres/clk/clk_fixed.h> 42 #include <dev/extres/clk/clk_gate.h> 43 #include <dev/extres/clk/clk_mux.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "clkdev_if.h" 49 #include "periph.h" 50 51 #define PARENT_CNT 2 52 53 /* 54 * Register chain: mux (select proper TBG) -> div1 (first frequency divider) -> 55 * div2 (second frequency divider) -> mux (select divided freq. 56 * or xtal output) -> gate (enable or disable clock), which is also final node 57 */ 58 59 int 60 a37x0_periph_d_register_full_clk_dd(struct clkdom *clkdom, 61 struct a37x0_periph_clknode_def *device_def) 62 { 63 const char *parent_names[PARENT_CNT]; 64 struct clk_mux_def *clk_mux; 65 struct clk_mux_def *tbg_mux; 66 struct clk_gate_def *gate; 67 struct clk_div_def *div1; 68 struct clk_div_def *div2; 69 int error, dev_id; 70 71 dev_id = device_def->common_def.device_id; 72 tbg_mux = &device_def->clk_def.full_dd.tbg_mux; 73 div1 = &device_def->clk_def.full_dd.div1; 74 div2 = &device_def->clk_def.full_dd.div2; 75 gate = &device_def->clk_def.full_dd.gate; 76 clk_mux = &device_def->clk_def.full_dd.clk_mux; 77 78 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, 79 device_def->common_def.tbg_cnt); 80 81 error = a37x0_periph_create_mux(clkdom, 82 tbg_mux, A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 83 if (error) 84 goto fail; 85 86 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); 87 error = a37x0_periph_create_div(clkdom, div1, 88 A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS)); 89 if (error) 90 goto fail; 91 92 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); 93 error = a37x0_periph_create_div(clkdom, div2, 94 A37x0_INTERNAL_CLK_ID(dev_id, DIV2_POS)); 95 if (error) 96 goto fail; 97 98 parent_names[0] = device_def->common_def.xtal; 99 parent_names[1] = div2->clkdef.name; 100 101 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); 102 error = a37x0_periph_create_mux(clkdom, clk_mux, 103 A37x0_INTERNAL_CLK_ID(dev_id, CLK_MUX_POS)); 104 if (error) 105 goto fail; 106 107 a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1); 108 error = a37x0_periph_create_gate(clkdom, gate, 109 dev_id); 110 if (error) 111 goto fail; 112 113 fail: 114 115 return (error); 116 } 117 118 /* 119 * Register chain: mux (select proper TBG) -> div1 (first frequency divider) -> 120 * mux (select divided freq. or xtal output) -> gate (enable or disable clock), 121 * which is also final node 122 */ 123 124 int 125 a37x0_periph_d_register_full_clk(struct clkdom *clkdom, 126 struct a37x0_periph_clknode_def *device_def) 127 { 128 const char *parent_names[PARENT_CNT]; 129 struct clk_mux_def *tbg_mux; 130 struct clk_mux_def *clk_mux; 131 struct clk_gate_def *gate; 132 struct clk_div_def *div; 133 int error, dev_id; 134 135 dev_id = device_def->common_def.device_id; 136 tbg_mux = &device_def->clk_def.full_d.tbg_mux; 137 div = &device_def->clk_def.full_d.div; 138 gate = &device_def->clk_def.full_d.gate; 139 clk_mux = &device_def->clk_def.full_d. clk_mux; 140 141 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, 142 device_def->common_def.tbg_cnt); 143 error = a37x0_periph_create_mux(clkdom, tbg_mux, 144 A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, MUX_POS)); 145 if (error) 146 goto fail; 147 148 a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1); 149 error = a37x0_periph_create_div(clkdom, div, 150 A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, DIV1_POS)); 151 if (error) 152 goto fail; 153 154 parent_names[0] = device_def->common_def.xtal; 155 parent_names[1] = div->clkdef.name; 156 157 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); 158 error = a37x0_periph_create_mux(clkdom, clk_mux, 159 A37x0_INTERNAL_CLK_ID(dev_id, CLK_MUX_POS)); 160 if (error) 161 goto fail; 162 163 a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1); 164 error = a37x0_periph_create_gate(clkdom, gate, 165 dev_id); 166 if (error) 167 goto fail; 168 169 fail: 170 171 return (error); 172 } 173 174 /* 175 * Register CPU clock. It consists of mux (select proper TBG) -> div (frequency 176 * divider) -> mux (choose divided or xtal output). 177 */ 178 179 int 180 a37x0_periph_d_register_periph_cpu(struct clkdom *clkdom, 181 struct a37x0_periph_clknode_def *device_def) 182 { 183 const char *parent_names[PARENT_CNT]; 184 struct clk_mux_def *clk_mux; 185 struct clk_mux_def *tbg_mux; 186 struct clk_div_def *div; 187 int error, dev_id; 188 189 dev_id = device_def->common_def.device_id; 190 tbg_mux = &device_def->clk_def.cpu.tbg_mux; 191 div = &device_def->clk_def.cpu.div; 192 clk_mux = &device_def->clk_def.cpu.clk_mux; 193 194 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, 195 device_def->common_def.tbg_cnt); 196 error = a37x0_periph_create_mux(clkdom, tbg_mux, 197 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 198 if (error) 199 goto fail; 200 201 a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1); 202 error = a37x0_periph_create_div(clkdom, div, 203 A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS)); 204 if (error) 205 goto fail; 206 207 parent_names[0] = device_def->common_def.xtal; 208 parent_names[1] = div->clkdef.name; 209 210 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); 211 error = a37x0_periph_create_mux(clkdom, clk_mux, 212 dev_id); 213 214 fail: 215 216 return (error); 217 } 218 219 /* 220 * Register chain: mux (choose proper TBG) -> div1 (first frequency divider) -> 221 * div2 (second frequency divider) -> mux (choose divided or xtal output). 222 */ 223 int 224 a37x0_periph_d_register_mdd(struct clkdom *clkdom, 225 struct a37x0_periph_clknode_def *device_def) 226 { 227 const char *parent_names[PARENT_CNT]; 228 struct clk_mux_def *tbg_mux; 229 struct clk_mux_def *clk_mux; 230 struct clk_div_def *div1; 231 struct clk_div_def *div2; 232 int error, dev_id; 233 234 dev_id = device_def->common_def.device_id; 235 tbg_mux = &device_def->clk_def.mdd.tbg_mux; 236 div1 = &device_def->clk_def.mdd.div1; 237 div2 = &device_def->clk_def.mdd.div2; 238 clk_mux = &device_def->clk_def.mdd.clk_mux; 239 240 a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs, 241 device_def->common_def.tbg_cnt); 242 error = a37x0_periph_create_mux(clkdom, tbg_mux, 243 A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS)); 244 if (error) 245 goto fail; 246 247 a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1); 248 error = a37x0_periph_create_div(clkdom, div1, 249 A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS)); 250 if (error) 251 goto fail; 252 253 a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1); 254 error = a37x0_periph_create_div(clkdom, div2, 255 A37x0_INTERNAL_CLK_ID(dev_id, DIV2_POS)); 256 257 if (error) 258 goto fail; 259 260 parent_names[0] = device_def->common_def.xtal; 261 parent_names[1] = div2->clkdef.name; 262 263 a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT); 264 error = a37x0_periph_create_mux(clkdom, clk_mux, 265 dev_id); 266 if (error) 267 goto fail; 268 269 fail: 270 271 return (error); 272 } 273