1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/rman.h> 31 #include <machine/bus.h> 32 33 #include <dev/clk/clk.h> 34 35 #include <dev/ofw/ofw_bus.h> 36 #include <dev/ofw/ofw_bus_subr.h> 37 38 #include "clkdev_if.h" 39 40 #include "a37x0_tbg_pll.h" 41 42 #define RD4(_clk, offset, val) \ 43 CLKDEV_READ_4(clknode_get_device(_clk), offset, val) 44 45 struct a37x0_tbg_pll_softc { 46 struct a37x0_tbg_pll_reg_def vcodiv; 47 struct a37x0_tbg_pll_reg_def refdiv; 48 struct a37x0_tbg_pll_reg_def fbdiv; 49 struct a37x0_tbg_pll_reg_def tbg_bypass; 50 }; 51 52 static int 53 a37x0_tbg_pll_recalc_freq(struct clknode *clk, uint64_t *freq) 54 { 55 struct a37x0_tbg_pll_softc *sc; 56 uint32_t vcodiv, fbdiv, refdiv; 57 unsigned int val; 58 59 sc = clknode_get_softc(clk); 60 61 RD4(clk, sc->tbg_bypass.offset, &val); 62 if ((val >> sc->tbg_bypass.shift) & sc->tbg_bypass.mask) 63 return 0; 64 65 RD4(clk, sc->vcodiv.offset, &val); 66 vcodiv = 1 << ((val >> sc->vcodiv.shift) & sc->vcodiv.mask); 67 68 RD4(clk, sc->refdiv.offset, &val); 69 refdiv = (val >> sc->refdiv.shift) & sc->refdiv.mask; 70 71 RD4(clk, sc->fbdiv.offset, &val); 72 fbdiv = (val >> sc->fbdiv.shift) & sc->fbdiv.mask; 73 74 if (refdiv == 0) 75 refdiv = 1; 76 77 *freq = *freq * (fbdiv / refdiv) * 4; 78 *freq /= vcodiv; 79 80 return (0); 81 } 82 83 static int 84 a37x0_tbg_pll_init(struct clknode *clk, device_t dev) 85 { 86 87 clknode_init_parent_idx(clk, 0); 88 89 return (0); 90 } 91 92 static clknode_method_t a37x0_tbg_pll_clknode_methods[] = { 93 CLKNODEMETHOD(clknode_recalc_freq, a37x0_tbg_pll_recalc_freq), 94 CLKNODEMETHOD(clknode_init, a37x0_tbg_pll_init), 95 96 CLKNODEMETHOD_END 97 }; 98 99 DEFINE_CLASS_1(a37x0_tbg_pll__clknode, a37x0_tbg_pll_clknode_class, 100 a37x0_tbg_pll_clknode_methods, sizeof(struct a37x0_tbg_pll_softc), 101 clknode_class); 102 103 int 104 a37x0_tbg_pll_clk_register(struct clkdom *clkdom, 105 const struct a37x0_tbg_pll_clk_def *clkdef) 106 { 107 struct a37x0_tbg_pll_softc *sc; 108 struct clknode *clk; 109 110 clk = clknode_create(clkdom, &a37x0_tbg_pll_clknode_class, 111 &clkdef->clkdef); 112 113 if (clk == NULL) 114 return (1); 115 116 sc = clknode_get_softc(clk); 117 118 sc->vcodiv = clkdef->vcodiv; 119 sc->refdiv = clkdef->refdiv; 120 sc->fbdiv = clkdef->fbdiv; 121 sc->tbg_bypass = clkdef->tbg_bypass; 122 123 if (clknode_register(clkdom, clk) == NULL) 124 return (1); 125 126 return (0); 127 } 128