1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2021 Semihalf. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/rman.h> 34 #include <machine/bus.h> 35 36 #include <dev/extres/clk/clk.h> 37 38 #include <dev/ofw/ofw_bus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 41 #include "clkdev_if.h" 42 43 #include "a37x0_tbg_pll.h" 44 45 #define RD4(_clk, offset, val) \ 46 CLKDEV_READ_4(clknode_get_device(_clk), offset, val) 47 48 struct a37x0_tbg_pll_softc { 49 struct a37x0_tbg_pll_reg_def vcodiv; 50 struct a37x0_tbg_pll_reg_def refdiv; 51 struct a37x0_tbg_pll_reg_def fbdiv; 52 struct a37x0_tbg_pll_reg_def tbg_bypass; 53 }; 54 55 static int 56 a37x0_tbg_pll_recalc_freq(struct clknode *clk, uint64_t *freq) 57 { 58 struct a37x0_tbg_pll_softc *sc; 59 uint32_t vcodiv, fbdiv, refdiv; 60 unsigned int val; 61 62 sc = clknode_get_softc(clk); 63 64 RD4(clk, sc->tbg_bypass.offset, &val); 65 if ((val >> sc->tbg_bypass.shift) & sc->tbg_bypass.mask) 66 return 0; 67 68 RD4(clk, sc->vcodiv.offset, &val); 69 vcodiv = 1 << ((val >> sc->vcodiv.shift) & sc->vcodiv.mask); 70 71 RD4(clk, sc->refdiv.offset, &val); 72 refdiv = (val >> sc->refdiv.shift) & sc->refdiv.mask; 73 74 RD4(clk, sc->fbdiv.offset, &val); 75 fbdiv = (val >> sc->fbdiv.shift) & sc->fbdiv.mask; 76 77 if (refdiv == 0) 78 refdiv = 1; 79 80 *freq = *freq * (fbdiv / refdiv) * 4; 81 *freq /= vcodiv; 82 83 return (0); 84 } 85 86 static int 87 a37x0_tbg_pll_init(struct clknode *clk, device_t dev) 88 { 89 90 clknode_init_parent_idx(clk, 0); 91 92 return (0); 93 } 94 95 static clknode_method_t a37x0_tbg_pll_clknode_methods[] = { 96 CLKNODEMETHOD(clknode_recalc_freq, a37x0_tbg_pll_recalc_freq), 97 CLKNODEMETHOD(clknode_init, a37x0_tbg_pll_init), 98 99 CLKNODEMETHOD_END 100 }; 101 102 DEFINE_CLASS_1(a37x0_tbg_pll__clknode, a37x0_tbg_pll_clknode_class, 103 a37x0_tbg_pll_clknode_methods, sizeof(struct a37x0_tbg_pll_softc), 104 clknode_class); 105 106 int 107 a37x0_tbg_pll_clk_register(struct clkdom *clkdom, 108 const struct a37x0_tbg_pll_clk_def *clkdef) 109 { 110 struct a37x0_tbg_pll_softc *sc; 111 struct clknode *clk; 112 113 clk = clknode_create(clkdom, &a37x0_tbg_pll_clknode_class, 114 &clkdef->clkdef); 115 116 if (clk == NULL) 117 return (1); 118 119 sc = clknode_get_softc(clk); 120 121 sc->vcodiv = clkdef->vcodiv; 122 sc->refdiv = clkdef->refdiv; 123 sc->fbdiv = clkdef->fbdiv; 124 sc->tbg_bypass = clkdef->tbg_bypass; 125 126 if (clknode_register(clkdom, clk) == NULL) 127 return (1); 128 129 return (0); 130 } 131