xref: /freebsd/sys/arm/mv/clk/a37x0_tbg.c (revision 22cf89c938886d14f5796fc49f9f020c23ea8eaf)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2021 Semihalf.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/bus.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/rman.h>
34 #include <machine/bus.h>
35 
36 #include <dev/extres/clk/clk.h>
37 #include <dev/ofw/ofw_bus_subr.h>
38 
39 #include "clkdev_if.h"
40 
41 #include "a37x0_tbg_pll.h"
42 
43 #define NUM_TBG			4
44 
45 #define TBG_CTRL0		0x4
46 #define TBG_CTRL1		0x8
47 #define TBG_CTRL7		0x20
48 #define TBG_CTRL8		0x30
49 
50 #define TBG_MASK		0x1FF
51 
52 #define TBG_A_REFDIV		0
53 #define TBG_B_REFDIV		16
54 
55 #define TBG_A_FBDIV		2
56 #define TBG_B_FBDIV		18
57 
58 #define TBG_A_VCODIV_SEL	0
59 #define TBG_B_VCODIV_SEL	16
60 
61 #define TBG_A_VCODIV_DIFF	1
62 #define TBG_B_VCODIV_DIFF	17
63 
64 struct a37x0_tbg_softc {
65 	device_t 		dev;
66 	struct clkdom		*clkdom;
67 	struct resource		*res;
68 };
69 
70 static struct resource_spec a37x0_tbg_clk_spec[] = {
71 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
72 	{ -1, 0 }
73 };
74 
75 struct a37x0_tbg_def {
76 	char 			*name;
77 	uint32_t		refdiv_shift;
78 	uint32_t		fbdiv_shift;
79 	uint32_t		vcodiv_offset;
80 	uint32_t		vcodiv_shift;
81 	uint32_t		tbg_bypass_en;
82 };
83 
84 static const struct a37x0_tbg_def tbg[NUM_TBG] = {
85 	{"TBG-A-P", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL8, TBG_A_VCODIV_DIFF, 9},
86 	{"TBG-B-P", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL8,
87 	    TBG_B_VCODIV_DIFF, 25},
88 	{"TBG-A-S", TBG_A_REFDIV, TBG_A_FBDIV, TBG_CTRL1, TBG_A_VCODIV_SEL, 9},
89 	{"TBG-B-S", TBG_B_REFDIV, TBG_B_FBDIV, TBG_CTRL1, TBG_B_VCODIV_SEL, 25}
90 };
91 
92 static int a37x0_tbg_read_4(device_t, bus_addr_t, uint32_t *);
93 static int a37x0_tbg_attach(device_t);
94 static int a37x0_tbg_detach(device_t);
95 static int a37x0_tbg_probe(device_t);
96 
97 static device_method_t a37x0_tbg_methods [] = {
98 	DEVMETHOD(device_attach,	a37x0_tbg_attach),
99 	DEVMETHOD(device_detach,	a37x0_tbg_detach),
100 	DEVMETHOD(device_probe,		a37x0_tbg_probe),
101 
102 	DEVMETHOD(clkdev_read_4,	a37x0_tbg_read_4),
103 
104 	DEVMETHOD_END
105 };
106 
107 static driver_t a37x0_tbg_driver = {
108 	"a37x0_tbg",
109 	a37x0_tbg_methods,
110 	sizeof(struct a37x0_tbg_softc)
111 };
112 
113 EARLY_DRIVER_MODULE(a37x0_tbg, simplebus, a37x0_tbg_driver, 0, 0,
114     BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
115 
116 static int
117 a37x0_tbg_read_4(device_t dev, bus_addr_t offset, uint32_t *val)
118 {
119 	struct a37x0_tbg_softc *sc;
120 
121 	sc = device_get_softc(dev);
122 
123 	*val = bus_read_4(sc->res, offset);
124 
125 	return (0);
126 }
127 
128 static int
129 a37x0_tbg_attach(device_t dev)
130 {
131 	struct a37x0_tbg_pll_clk_def def;
132 	struct a37x0_tbg_softc *sc;
133 	const char *clkname;
134 	int error, i;
135 	phandle_t node;
136 	clk_t clock;
137 
138 	sc = device_get_softc(dev);
139 	node = ofw_bus_get_node(dev);
140 	sc->dev = dev;
141 
142 	if (bus_alloc_resources(dev, a37x0_tbg_clk_spec, &sc->res) != 0) {
143 		device_printf(dev, "Cannot allocate resources\n");
144 		return (ENXIO);
145 	}
146 
147 	sc->clkdom = clkdom_create(dev);
148 	if (sc->clkdom == NULL) {
149 		device_printf(dev, "Cannot create clock domain.\n");
150 		return (ENXIO);
151 	}
152 
153 	error = clk_get_by_ofw_index(dev, node, 0, &clock);
154 	if (error != 0) {
155 		device_printf(dev, "Cannot find clock parent\n");
156 		bus_release_resources(dev, a37x0_tbg_clk_spec, &sc->res);
157 		return (error);
158 	}
159 
160 	clkname = clk_get_name(clock);
161 
162 	for (i = 0; i < NUM_TBG; i++) {
163 		def.clkdef.parent_names = &clkname;
164 		def.clkdef.parent_cnt = 1;
165 		def.clkdef.id = i;
166 		def.clkdef.name = tbg[i].name;
167 
168 		def.vcodiv.offset = tbg[i].vcodiv_offset;
169 		def.vcodiv.shift = tbg[i].vcodiv_shift;
170 		def.refdiv.offset = TBG_CTRL7;
171 		def.refdiv.shift = tbg[i].refdiv_shift;
172 		def.fbdiv.offset = TBG_CTRL0;
173 		def.fbdiv.shift = tbg[i].fbdiv_shift;
174 		def.vcodiv.mask = def.refdiv.mask = def.fbdiv.mask = TBG_MASK;
175 		def.tbg_bypass.offset = TBG_CTRL1;
176 		def.tbg_bypass.shift = tbg[i].tbg_bypass_en;
177 		def.tbg_bypass.mask = 0x1;
178 
179 		error = a37x0_tbg_pll_clk_register(sc->clkdom, &def);
180 
181 		if (error) {
182 			device_printf(dev, "Cannot register clock node\n");
183 			bus_release_resources(dev, a37x0_tbg_clk_spec,
184 			    &sc->res);
185 			return (ENXIO);
186 		}
187 	}
188 
189 	error = clkdom_finit(sc->clkdom);
190 	if (error) {
191 		device_printf(dev,
192 		    "Cannot finalize clock domain intialization\n");
193 		bus_release_resources(dev, a37x0_tbg_clk_spec, &sc->res);
194 		return (ENXIO);
195 	}
196 
197 	if (bootverbose)
198 		clkdom_dump(sc->clkdom);
199 
200 	return (0);
201 }
202 
203 static int
204 a37x0_tbg_probe(device_t dev)
205 {
206 
207 	if (!ofw_bus_status_okay(dev))
208 		return (ENXIO);
209 
210 	if (!ofw_bus_is_compatible(dev, "marvell,armada-3700-tbg-clock"))
211 		return (ENXIO);
212 
213 	device_set_desc(dev, "Marvell Armada 3700 time base generators");
214 	return (BUS_PROBE_DEFAULT);
215 }
216 
217 static int
218 a37x0_tbg_detach(device_t dev)
219 {
220 
221 	return (EBUSY);
222 }
223